{"id":808135,"url":"http://patchwork.ozlabs.org/api/1.0/covers/808135/?format=json","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/1.0/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>","date":"2017-08-31T08:20:36","name":"[RFC,0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":72263,"url":"http://patchwork.ozlabs.org/api/1.0/people/72263/?format=json","name":"Yisheng Xie","email":"xieyisheng1@huawei.com"},"series":[{"id":770,"url":"http://patchwork.ozlabs.org/api/1.0/series/770/?format=json","date":"2017-08-31T08:20:37","name":"Add platform device SVM support for ARM SMMUv3","version":1,"mbox":"http://patchwork.ozlabs.org/series/770/mbox/"}],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjbD72rnTz9s7c\n\tfor ;\n\tThu, 31 Aug 2017 18:30:31 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751716AbdHaIa2 (ORCPT\n\t);\n\tThu, 31 Aug 2017 04:30:28 -0400","from szxga04-in.huawei.com ([45.249.212.190]:5500 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751242AbdHaI3U (ORCPT\n\t); Thu, 31 Aug 2017 04:29:20 -0400","from 172.30.72.59 (EHLO DGGEMS402-HUB.china.huawei.com)\n\t([172.30.72.59])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DGG21830; Thu, 31 Aug 2017 16:29:12 +0800 (CST)","from linux-ibm.site (10.175.102.37) by\n\tDGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP\n\tServer id 14.3.301.0; Thu, 31 Aug 2017 16:28:58 +0800"],"From":"Yisheng Xie ","To":"","CC":", , ,\n\t, ,\n\t, , ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, , ","Subject":"[RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","Date":"Thu, 31 Aug 2017 16:20:36 +0800","Message-ID":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>","X-Mailer":"git-send-email 1.7.12.4","MIME-Version":"1.0","Content-Type":"text/plain","X-Originating-IP":"[10.175.102.37]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A010204.59A7C8DB.0060, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"9a2cae966031a49c46a2820763498c6d","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:\nhttps://www.spinics.net/lists/arm-kernel/msg565155.html\n\nBut for some platform devices(aka on-chip integrated devices), there is also\nSVM requirement, which works based on the SMMU stall mode.\nJean-Philippe has prepared a prototype patchset to support it:\ngit://linux-arm.org/linux-jpb.git svm/stall\n\nWe tested this patchset with some fixes on a on-chip integrated device. The\nbasic function is ok, so I just send them out for review, although this\npatchset heavily depends on the former patchset (PCIe SVM support for ARM\nSMMUv3), which is still under discussion.\n\nPatch Overview:\n*1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits\n*4 is to realise the SVM function for platform device\n*5 is fix a bug when test SVM function while SMMU donnot support this feature\n*6 avoid ILLEGAL setting of STE and CD entry about stall\n\nAcctually here, I also have a question about SVM on SMMUv3:\n\n1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,\n it will register a mmu_notify. Therefore, when a page range is invalid, we can\n send TLBI or ATC invalid without BTM?\n\n2. According to ACPI IORT spec, named component specific data has a node flags field\n whoes bit0 is for Stall support. However, it do not have any field for pasid bit.\n Can we use other 5 bits[5:1] for pasid bit numbers, so we can have 32 pasid bit for\n a single platform device which should be enough, because SMMU only support 20 bit pasid\n\n3. Presently, the pasid is allocate for a task but not for a context, if a task is trying\n to bind to 2 device A and B:\n a) A support 5 pasid bits\n b) B support 2 pasid bits\n c) when the task bind to device A, it allocate pasid = 16\n d) then it must be fail when trying to bind to task B, for its highest pasid is 4.\n So it should allocate a single pasid for a context to avoid this?\n\n\nJean-Philippe Brucker (3):\n dt-bindings: document stall and PASID properties for IOMMU masters\n iommu/of: Add stall and pasid properties to iommu_fwspec\n iommu/arm-smmu-v3: Add SVM support for platform devices\n\nYisheng Xie (3):\n ACPI: IORT: Add stall and pasid properties to iommu_fwspec\n iommu/arm-smmu-v3: fix panic when handle stall mode irq\n iommu/arm-smmu-v3: Avoid ILLEGAL setting of STE.S1STALLD and CD.S\n\n Documentation/devicetree/bindings/iommu/iommu.txt | 13 ++\n drivers/acpi/arm64/iort.c | 20 ++\n drivers/iommu/arm-smmu-v3.c | 230 ++++++++++++++++++----\n drivers/iommu/of_iommu.c | 11 +\n include/acpi/actbl2.h | 5 +\n include/linux/iommu.h | 2 +\n 6 files changed, 244 insertions(+), 37 deletions(-)\n\n--\n1.7.12.4\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html"}