{"id":808134,"url":"http://patchwork.ozlabs.org/api/1.0/covers/808134/?format=json","project":{"id":19,"url":"http://patchwork.ozlabs.org/api/1.0/projects/19/?format=json","name":"Linux IMX development","link_name":"linux-imx","list_id":"linux-imx-kernel.lists.patchwork.ozlabs.org","list_email":"linux-imx-kernel@lists.patchwork.ozlabs.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>","date":"2017-08-31T08:20:36","name":"[RFC,0/6] Add platform device SVM support for ARM SMMUv3","submitter":{"id":72263,"url":"http://patchwork.ozlabs.org/api/1.0/people/72263/?format=json","name":"Yisheng Xie","email":"xieyisheng1@huawei.com"},"series":[{"id":771,"url":"http://patchwork.ozlabs.org/api/1.0/series/771/?format=json","date":"2017-08-31T08:20:36","name":"Add platform device SVM support for ARM SMMUv3","version":1,"mbox":"http://patchwork.ozlabs.org/series/771/mbox/"}],"headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Thu, 31 Aug 2017 16:29:12 +0800 (CST)","from linux-ibm.site (10.175.102.37) by\n\tDGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP\n\tServer id 14.3.301.0; Thu, 31 Aug 2017 16:28:58 +0800"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To\n\t:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:\n\tResent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:\n\tList-Owner; bh=dhrWvP0dSbKavQrkrHIll7SazQXpxdadX2yuNFrNr+I=;\n\tb=iw80MXzd3nbo7z\n\tY5BDVLiE2x/hgNRpYAyDMLSu5y1Ou+qBE331VTdsbjMzGP6r/jblYCNufC2tEE0yJ+wZHyPXEHUyZ\n\tpbb7KfPMI+Isn4xeFtIeqjz3IuWQSom4KpjGljcsi9tDVnD6q7h3rt1qUZwBl1s3eGi2q+rjIw1++\n\tXLSQ+kdkGrqAU/18HnS/yrjLxGLBHx0Bld7ZMJX+22Er5FMzQxRBSS+pxVBO1ImD02s/HdOCJ0FlX\n\tZcJaMrwWiVnfRN8OYPuTopI0idPECHSjfGEoTku/eSHr9z2EGPzapMILI0GNVkIX8Yz8pot/1bHXq\n\tQL/nFpwNCa1Q3/vFCu1g==;","From":"Yisheng Xie ","To":"","Subject":"[RFC PATCH 0/6] Add platform device SVM support for ARM SMMUv3","Date":"Thu, 31 Aug 2017 16:20:36 +0800","Message-ID":"<1504167642-14922-1-git-send-email-xieyisheng1@huawei.com>","X-Mailer":"git-send-email 1.7.12.4","MIME-Version":"1.0","X-Originating-IP":"[10.175.102.37]","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A010204.59A7C8DB.0060, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"9a2cae966031a49c46a2820763498c6d","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170831_012958_945608_D117B183 ","X-CRM114-Status":"GOOD ( 14.30 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org,\n\tlorenzo.pieralisi@arm.com, \n\tlv.zheng@intel.com, will.deacon@arm.com, joro@8bytes.org,\n\tliubo95@huawei.com, rjw@rjwysocki.net, robert.moore@intel.com,\n\tlinux-kernel@vger.kernel.org, \n\tlinux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org,\n\trobh+dt@kernel.org, hanjun.guo@linaro.org, xieyisheng@huawei.com,\n\tsudeep.holla@arm.com, chenjiankang1@huawei.com, devel@acpica.org,\n\trobin.murphy@arm.com, linux-arm-kernel@lists.infradead.org,\n\tlenb@kernel.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"},"content":"Jean-Philippe has post a patchset for Adding PCIe SVM support to ARM SMMUv3:\nhttps://www.spinics.net/lists/arm-kernel/msg565155.html\n\nBut for some platform devices(aka on-chip integrated devices), there is also\nSVM requirement, which works based on the SMMU stall mode.\nJean-Philippe has prepared a prototype patchset to support it:\ngit://linux-arm.org/linux-jpb.git svm/stall\n\nWe tested this patchset with some fixes on a on-chip integrated device. The\nbasic function is ok, so I just send them out for review, although this\npatchset heavily depends on the former patchset (PCIe SVM support for ARM\nSMMUv3), which is still under discussion.\n\nPatch Overview:\n*1 to 3 prepare for device tree or acpi get the device stall ability and pasid bits\n*4 is to realise the SVM function for platform device\n*5 is fix a bug when test SVM function while SMMU donnot support this feature\n*6 avoid ILLEGAL setting of STE and CD entry about stall\n\nAcctually here, I also have a question about SVM on SMMUv3:\n\n1. Why the SVM feature on SMMUv3 depends on BTM feature? when bind a task to device,\n it will register a mmu_notify. Therefore, when a page range is invalid, we can\n send TLBI or ATC invalid without BTM?\n\n2. According to ACPI IORT spec, named component specific data has a node flags field\n whoes bit0 is for Stall support. However, it do not have any field for pasid bit.\n Can we use other 5 bits[5:1] for pasid bit numbers, so we can have 32 pasid bit for\n a single platform device which should be enough, because SMMU only support 20 bit pasid\n\n3. Presently, the pasid is allocate for a task but not for a context, if a task is trying\n to bind to 2 device A and B:\n a) A support 5 pasid bits\n b) B support 2 pasid bits\n c) when the task bind to device A, it allocate pasid = 16\n d) then it must be fail when trying to bind to task B, for its highest pasid is 4.\n So it should allocate a single pasid for a context to avoid this?\n\n\nJean-Philippe Brucker (3):\n dt-bindings: document stall and PASID properties for IOMMU masters\n iommu/of: Add stall and pasid properties to iommu_fwspec\n iommu/arm-smmu-v3: Add SVM support for platform devices\n\nYisheng Xie (3):\n ACPI: IORT: Add stall and pasid properties to iommu_fwspec\n iommu/arm-smmu-v3: fix panic when handle stall mode irq\n iommu/arm-smmu-v3: Avoid ILLEGAL setting of STE.S1STALLD and CD.S\n\n Documentation/devicetree/bindings/iommu/iommu.txt | 13 ++\n drivers/acpi/arm64/iort.c | 20 ++\n drivers/iommu/arm-smmu-v3.c | 230 ++++++++++++++++++----\n drivers/iommu/of_iommu.c | 11 +\n include/acpi/actbl2.h | 5 +\n include/linux/iommu.h | 2 +\n 6 files changed, 244 insertions(+), 37 deletions(-)\n\n--\n1.7.12.4"}