{"id":807655,"url":"http://patchwork.ozlabs.org/api/1.0/covers/807655/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20170830142454.10971-1-jglauber@cavium.com>","date":"2017-08-30T14:24:51","name":"[v3,0/3] Workaround for bus/slot reset on Cavium cn8xxx root ports","submitter":{"id":68350,"url":"http://patchwork.ozlabs.org/api/1.0/people/68350/?format=json","name":"Jan Glauber","email":"jglauber@cavium.com"},"series":[{"id":624,"url":"http://patchwork.ozlabs.org/api/1.0/series/624/?format=json","date":"2017-08-30T14:24:51","name":"Workaround for bus/slot reset on Cavium cn8xxx root ports","version":3,"mbox":"http://patchwork.ozlabs.org/series/624/mbox/"}],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xj77t1Wh0z9s7f\n\tfor ;\n\tThu, 31 Aug 2017 00:25:14 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751695AbdH3OZL (ORCPT );\n\tWed, 30 Aug 2017 10:25:11 -0400","from mail-wm0-f67.google.com ([74.125.82.67]:38265 \"EHLO\n\tmail-wm0-f67.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751679AbdH3OZK (ORCPT\n\t); Wed, 30 Aug 2017 10:25:10 -0400","by mail-wm0-f67.google.com with SMTP id u26so1957895wma.5;\n\tWed, 30 Aug 2017 07:25:09 -0700 (PDT)","from hc.fritz.box\n\t(HSI-KBW-46-223-66-184.hsi.kabel-badenwuerttemberg.de.\n\t[46.223.66.184]) by smtp.gmail.com with ESMTPSA id\n\tp105sm97012wrc.64.2017.08.30.07.25.07\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tWed, 30 Aug 2017 07:25:08 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id;\n\tbh=m6w87WLKoi6Bwgz7FwmA+KRiIkZJx0F9zB2WqypRhcE=;\n\tb=XxR8vUoaX+ULWZ5X6Ax3OGRtp1cdCiIu/jjnwFx37chhSTOC5Od1HNjCdXrODBehC+\n\tZBQhTzzoKRy1LMgaCHqr4ehhpuqgvoGYxgdSyGyBAUFuNoCl6Jty7Xk2hX0P0AAfApbd\n\tadmOVV8GPEWX/Q0l9wBjIgES84ITqxwMcnhFdqJ3LwMxAkK2gMw/5hfd4mt6BTptONiQ\n\teRRXqkQ3LtN04bIy+23S2tsEmKzT87ZeXB4QhU3IsigfRUc9q+pKxyhfNum3Yo+jvav2\n\taILoCzbXjwrX8vBellXBHxA8zfVPdmkUOjGU6uugdTPv59mGeTwKNmWxbeCDmehCvJSL\n\tNjoQ==","X-Gm-Message-State":"AHYfb5jOSIgZAwRt6RVRJxzN9m5qU7NVA9i7/PPS6ULV6KMIdcxiwV3u\n\twEuAN/UHoVfr/Q==","X-Received":"by 10.28.142.3 with SMTP id q3mr1376320wmd.56.1504103108541;\n\tWed, 30 Aug 2017 07:25:08 -0700 (PDT)","From":"Jan Glauber ","To":"Bjorn Helgaas ","Cc":"linux-pci@vger.kernel.org, Alex Williamson ,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,\n\tJan Glauber ","Subject":"[PATCH v3 0/3] Workaround for bus/slot reset on Cavium cn8xxx root\n\tports","Date":"Wed, 30 Aug 2017 16:24:51 +0200","Message-Id":"<20170830142454.10971-1-jglauber@cavium.com>","X-Mailer":"git-send-email 2.9.0.rc0.21.g7777322","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"Using vfio-pci on a combination of cn8xxx and some PCI devices results in\na kernel panic. This is triggered by issuing a bus or a slot reset\non the PCI device.\n\nThe solution is to prevent the reset. I've dropped the vfio patch from the\nprevious series as vfio-pci already checks in the reset path for\npci_bus_resetable() and pci_slot_resetable().\n\nWith this series both checks indicate that the reset is not possible\npreventing the kernel panic.\n\nDavid Daney (2):\n PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device\n PCI: Avoid bus reset for Cavium cn8xxx root ports\n\nJan Glauber (1):\n PCI: Avoid slot reset for Cavium cn8xxx root ports\n\n drivers/pci/pci.c | 4 ++++\n drivers/pci/quirks.c | 24 ++++++++++++++++++++++++\n 2 files changed, 28 insertions(+)"}