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d=\"scan'208\";a=\"10845606\"","From":"=?utf-8?q?Stefan_Br=C3=BCns?= <stefan.bruens@rwth-aachen.de>","To":"<linux-sunxi@googlegroups.com>","Subject":"[RESEND PATCH 0/2] Enable SPI on A64/Pine64","Date":"Tue, 29 Aug 2017 22:26:50 +0200","Message-ID":"<20170829202652.5476-1-stefan.bruens@rwth-aachen.de>","X-Mailer":"git-send-email 2.14.1","MIME-Version":"1.0","X-Originating-IP":"[92.224.122.214]","X-ClientProxiedBy":"rwthex-s2-b.rwth-ad.de (2002:8682:1a9b::8682:1a9b) To\n\trwthex-w2-b.rwth-ad.de (2002:8682:1a9f::8682:1a9f)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170829_132725_059495_5BAD4DD0 ","X-CRM114-Status":"UNSURE (   3.56  )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details:   (-4.2 points)\n\tpts rule name              description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.130.5.47 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":"<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>","List-Archive":"<http://lists.infradead.org/pipermail/linux-arm-kernel/>","List-Post":"<mailto:linux-arm-kernel@lists.infradead.org>","List-Help":"<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>","List-Subscribe":"<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>","Cc":"Rob Herring <robh+dt@kernel.org>,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>,\n\tChen-Yu Tsai <wens@csie.org>, \n\tlinux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"},"content":"The A64 SPI controller is compatible to the H3/H5 controller, i.e. same\nregisters and same queue depth.\n\nThe Pine64 exposes both controllers on the PI-2 and Euler connectors.\n\nTested/verified with logic analyser and spidev_test using MOSI/MISO loopback.\n\nNote: spi0 on the A64 may conflict with the eMMC controller, as the MISO pin is\nalso used for the HS400 eMMC data strobe. This is only a concern if the board\nuses eMMC (does not apply to the Pine64) *and* is using HS400 mode. The same\npin conflict exists for the H5.\n\nStefan Brüns (2):\n  arm64: allwinner: a64: add SPI nodes\n  arm64: allwinner: pine64: Enable spi0/spi1\n\n .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts |  8 +++++\n arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi      | 40 ++++++++++++++++++++++\n 2 files changed, 48 insertions(+)"}