{"id":2221146,"url":"http://patchwork.ozlabs.org/api/1.0/covers/2221146/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408041953.1899532-1-brian.cain@oss.qualcomm.com>","date":"2026-04-08T04:19:25","name":"[v4,00/28] Hexagon system emulation - Part 2/3","submitter":{"id":89839,"url":"http://patchwork.ozlabs.org/api/1.0/people/89839/?format=json","name":"Brian Cain","email":"brian.cain@oss.qualcomm.com"},"series":[{"id":499179,"url":"http://patchwork.ozlabs.org/api/1.0/series/499179/?format=json","date":"2026-04-08T04:19:31","name":"Hexagon system emulation - Part 2/3","version":4,"mbox":"http://patchwork.ozlabs.org/series/499179/mbox/"}],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=RVxWCm0Y;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=V45bwrEs;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mx0a-0031df01.pphosted.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This is Part 2 of the Hexagon system emulation series. It adds the\nruntime helpers, CPU operations, and translation support needed for\nfull-system emulation of the Hexagon DSP.\n\nThis includes:\n - Software interrupt (SWI) and interrupt handling\n - TLB fill and permission checking\n - System register read/write support in TCG\n - Implicit sysreg writes and translation-block termination\n - Stack overflow exception support\n - Thread scheduling helpers (setprio, resched, resume)\n - k0 lock/unlock for kernel mode\n - idef-parser support for fFRAMECHECK\n - TCG overrides for system transfer instructions\n\nBased on Part 1 v6.\n\nChanges since v3:\n - Rebased onto Part 1 v6\n - Fixed idef-parser fFRAMECHECK implementation (Taylor)\n - Removed pkt_ends_tb from DisasContext, call pkt_ends_tb() directly (Taylor)\n - Changed t_sreg_new_value sizing from NUM_SREGS to\n HEX_SREG_GLB_START (Taylor)\n - Removed unnecessary tcg_gen_mov_tl sreg pre-copy in\n gen_start_packet(); no sreg writes are predicated (Taylor)\n - Added continue after STID/IMASK/IPENDAD writeback in\n gen_sreg_writes() to avoid redundant writeback (Taylor)\n - Moved hexagon_greg_read() declaration to correct commit (Taylor)\n - Fixed set_enable_mask/clear_enable_mask return type consistency (Taylor)\n - Added early return for globalregs==false in set_enable_mask and\n set_wait_mode (Taylor)\n - Fixed bare %x/%d format specifiers across multiple files, using\n PRIx32/PRIu32/TARGET_FMT_lx as appropriate (Taylor)\n - Fixed mid-block variable declarations (C89 style)\n - Removed invalid PRM section references from setprio/resched\n commit message (Taylor)\n - Renamed \"Add TLB, k0 {un,}lock\" to \"Add k0 {un,}lock\" (Taylor)\n - Moved cycle counter/pcycle/modify_ssr commits to Part 1\n - All cycle counter code properly guarded by\n ifndef CONFIG_USER_ONLY (Taylor)\n\nPrevious versions:\n - v3: https://lore.kernel.org/qemu-devel/20260311040758.1068731-1-brian.cain@oss.qualcomm.com/\n - v2: https://lore.kernel.org/qemu-devel/20250902034847.1948010-1-brian.cain@oss.qualcomm.com/\n - v1: https://lore.kernel.org/qemu-devel/20250301052845.1012069-1-brian.cain@oss.qualcomm.com/\n\nBrian Cain (26):\n target/hexagon: Implement {c,}swi helpers\n target/hexagon: Implement iassign{r,w} helpers\n target/hexagon: Implement start/stop helpers, soft reset\n target/hexagon: Implement {g,s}etimask helpers\n target/hexagon: Implement wait helper\n target/hexagon: Implement get_exe_mode()\n target/hexagon: Implement hex_tlb_entry_get_perm()\n target/hexagon: Implement software interrupt\n target/hexagon: Implement stack overflow exception\n target/hexagon: Implement exec_interrupt, set_irq\n target/hexagon: Implement hexagon_tlb_fill()\n target/hexagon: Implement siad inst\n target/hexagon: Implement hexagon_resume_threads()\n target/hexagon: Implement setprio, resched\n target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug()\n target/hexagon: extend hexagon_cpu_mmu_index() for sysemu\n target/hexagon: Decode trap1, rte as COF\n target/hexagon: Implement modify_ssr, resched, pending_interrupt\n target/hexagon: Add pkt_ends_tb to translation\n target/hexagon: Add next_PC, {s,g}reg writes\n target/hexagon: Add implicit sysreg writes\n target/hexagon: Define system, guest reg names\n target/hexagon: Add k0 {un,}lock\n target/hexagon: Add PC to raise_exception, use fTRAP() helper\n target/hexagon: Add TCG overrides for transfer insts\n target/hexagon: Add support for loadw_phys\n\nMatheus Tavares Bernardino (2):\n target/hexagon: add simple cpu_exec_reset and pointer_wrap\n target/hexagon: Add guest reg reading functionality\n\n target/hexagon/cpu.h | 11 +\n target/hexagon/cpu_helper.h | 8 +\n target/hexagon/gen_tcg.h | 7 -\n target/hexagon/gen_tcg_sys.h | 25 ++\n target/hexagon/helper.h | 6 +-\n target/hexagon/hexswi.h | 17 +\n target/hexagon/idef-parser/parser-helpers.h | 2 +\n target/hexagon/internal.h | 4 +\n target/hexagon/macros.h | 3 -\n target/hexagon/sys_macros.h | 7 +\n target/hexagon/translate.h | 5 +-\n target/hexagon/reg_fields_def.h.inc | 11 +\n linux-user/hexagon/cpu_loop.c | 7 +\n target/hexagon/cpu.c | 360 ++++++++++++++-\n target/hexagon/decode.c | 14 +\n target/hexagon/genptr.c | 18 +-\n target/hexagon/hexswi.c | 267 +++++++++++\n target/hexagon/idef-parser/parser-helpers.c | 9 +\n target/hexagon/op_helper.c | 462 +++++++++++++++++++-\n target/hexagon/translate.c | 225 +++++++++-\n target/hexagon/hex_common.py | 3 +\n target/hexagon/idef-parser/idef-parser.y | 3 +\n target/hexagon/imported/encode_pp.def | 1 +\n target/hexagon/imported/ldst.idef | 3 +\n 24 files changed, 1425 insertions(+), 53 deletions(-)\n create mode 100644 target/hexagon/hexswi.h\n create mode 100644 target/hexagon/hexswi.c"}