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a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwMjE3MDA5NCBTYWx0ZWRfX6l521oaN77Q8\n KCaY9/viIvS+T5oAGFYqdzeaVcm9qA6txOz2bk0TxDKh60nw1dG0vrIGd2W7TayMWtamU/MlDt2\n hB9cZvc2fA9clw2c3aRKKK4l4XLcJpYwypj6mdM5KPxbhNrbHft+Hql3XNO90ZfDYd0KZ080ZDt\n psk9lZtWQm+8j3MvpEhvT5lXutUGkBIBdo96g9r/1kNUFQ5MpI0DkCO7BXJlyA1s1qV2B1NpdZB\n OzvLrXeXpuxQT/mPDu6ZgAieo5Ff+YyAGRO/CcyKLpFEme9duTAzMYOWHiU/fZQsE8XmatpOcOs\n 2QUJXsMfydJjUkMgYBzdk0VGxvpT8Vghz0MQeITUgI4SvshHg2Es8+5p79TmUeVeFPHBnWCUdUZ\n ZFkQmR+7S9lBn2AgmxkB9tmVwWU5GNsa6sfMKrdpSvuQEEbAbf4WjRx5P+m1bXKr/z+dJrLWia4\n rYvUf7Ab3G9yMNCVHRA==","X-Proofpoint-ORIG-GUID":"onMJXRuuFGLWm7eNk-jSflSytNc3jPEF","X-Authority-Analysis":"v=2.4 cv=BryQAIX5 c=1 sm=1 tr=0 ts=69944eb2 cx=c_pps\n a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22\n a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=e1WyCQ9WWvu24y8kmCgA:9 a=3ZKOabzyN94A:10\n a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22","X-Proofpoint-GUID":"onMJXRuuFGLWm7eNk-jSflSytNc3jPEF","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n impostorscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0\n clxscore=1015 adultscore=0 bulkscore=0 priorityscore=1501 malwarescore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170094"},"content":"This series adds support for putting Qualcomm PCIe host bridges into D3cold\nwhen downstream conditions allow it, and introduces a small common helper\nto determine D3cold eligibility based on endpoint state.\n\nOn Qualcomm platforms, PCIe host controllers are currently kept powered\neven when there are no active endpoints (i.e. all endpoints are already in\nPCI_D3hot). This prevents the SoC from entering deeper low‑power states\nsuch as CXPC.\n\nWhile PCIe D3cold support exists in the PCI core, host controller drivers\nlack a common mechanism to determine whether it is safe to power off the\nhost bridge without breaking active devices or wakeup functionality.\nAs a result, controllers either avoid entering D3cold or depend on rough,\ndriver‑specific workarounds.\n\nThis series addresses that gap.\n\n1. Introduces pci_host_common_can_enter_d3cold(), a helper that determines\n whether a host bridge may enter D3cold based on downstream PCIe endpoint\n state. The helper permits D3cold only when all *active* endpoints are\n already in PCI_D3hot, and any wakeup‑enabled endpoint supports PME\n from D3cold.\n\n2. Updates the Designware PCIe host driver to use this helper in the\n suspend_noirq() path, replacing the existing heuristic that blocked\n D3cold whenever L1 ASPM was enabled.\n\n3. Enables D3cold support for Qualcomm PCIe controllers by wiring them into\n the DesignWare common suspend/resume flow and explicitly powering down\n controller resources when all endpoints are in D3hot.\n\nThe immediate outcome of this series is that Qualcomm PCIe host bridges can\nenter D3cold when all endpoints are in D3hot.\n\nThis is a necessary but not sufficient step toward unblocking CXPC. With\nthis series applied, CXPC can be achieved on systems with no attached NVMe\ndevices. Support for NVMe‑attached systems requires additional changes\nin NVMe driver, which are being worked on separately.\n\nTested on:\n - Qualcomm Lemans EVK, Monaco & sc7280 platforms.\n\nValidation steps:\n - Boot without NVMe attach:\n * PCIe host enters D3cold during suspend\n * SoC is able to reach CXPC provided other drivers also remove\n\ttheir votes as part of suspend.\n\nSigned-off-by: Krishna Chaitanya Chundru \n---\nChanges in v2:\n- Updated the cover letter (Bjorn Andersson)\n- Add get_ltssm helper function to read LTSSM state from parf.\n- Allow D3cold if there is no driver enabled for a endpoint.\n- Added a seperate patch to make phy down in deinit part to avoid power\n leakage.\n- Revert icc bw voting if resume fails(Bjorn Andersson).\n- Link to v1: https://lore.kernel.org/r/20260128-d3cold-v1-0-dd8f3f0ce824@oss.qualcomm.com\n\n---\nKrishna Chaitanya Chundru (5):\n PCI: host-common: Add helper to determine host bridge D3cold eligibility\n PCI: dwc: Use common D3cold eligibility helper in suspend path\n PCI: qcom: Add .get_ltssm() helper\n PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks\n PCI: qcom: Add D3cold support\n\n drivers/pci/controller/dwc/pcie-designware-host.c | 9 +-\n drivers/pci/controller/dwc/pcie-qcom.c | 162 +++++++++++++++-------\n drivers/pci/controller/pci-host-common.c | 45 ++++++\n drivers/pci/controller/pci-host-common.h | 2 +\n 4 files changed, 162 insertions(+), 56 deletions(-)\n---\nbase-commit: 9702969978695d9a699a1f34771580cdbb153b33\nchange-id: 20251229-d3cold-bf99921960bb\n\nBest regards,"}