From patchwork Sun Mar 24 17:25:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1063315 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44S47H6Wz4z9sRy for ; Mon, 25 Mar 2019 04:26:19 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44S47H5ZQCzDqLZ for ; Mon, 25 Mar 2019 04:26:19 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44S47D4KYrzDqFw for ; Mon, 25 Mar 2019 04:26:16 +1100 (AEDT) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2OHNjXg066886 for ; Sun, 24 Mar 2019 13:26:14 -0400 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0b-001b2d01.pphosted.com with ESMTP id 2ree428bk8-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 24 Mar 2019 13:26:14 -0400 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 24 Mar 2019 17:26:11 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2OHQAkt57737246 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 24 Mar 2019 17:26:10 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DF2A242041; Sun, 24 Mar 2019 17:26:09 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 74A484204B; Sun, 24 Mar 2019 17:26:08 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.199.41.162]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 24 Mar 2019 17:26:08 +0000 (GMT) From: Vaidyanathan Srinivasan To: Stewart Smith Date: Sun, 24 Mar 2019 22:55:36 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> References: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19032417-0012-0000-0000-0000030690FA X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032417-0013-0000-0000-0000213DB1F9 Message-Id: <20190324172543.12625-2-svaidy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-24_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903240134 Subject: [Skiboot] [PATCH v3 1/8] Add basic P9 fused core support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryan Grimm , skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Ryan Grimm P9 cores can be configured into fused core mode where two core chiplets function as an 8-threaded, single core. So, bump four to eight in boot_entry when in fused core mode and cpu_thread_count in init_boot_cpu. The HID, AMOR, TSCR, RPR require the first active thread on that core chiplet to load the copy for that core chiplet. So, send thread 1 of a fused core to init_shared_sprs in boot_entry. The code checks for fused core mode in the core thead state register and puts a field in struct cpu_thread. This flag is checked when updating the HID and in XIVE code when setting the special bar. For XSCOM, the core ID is the non-fused EX. So, create macros to arrange the bits. It's fairly verbose but somewhat readable. This was tested on a P9 ZZ with 16 fused cores and ran HTX for over 24 hours. Signed-off-by: Ryan Grimm Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling --- asm/head.S | 24 +++++++++++++++++++++--- core/chip.c | 15 +++++++++++---- core/cpu.c | 39 ++++++++++++++++++++++++++++++++++----- core/fast-reboot.c | 2 +- hdata/test/hdata_to_dt.c | 9 ++++++++- hw/xive.c | 2 +- include/chip.h | 31 +++++++++++++++++++++++++++++++ include/cpu.h | 6 ++++++ include/xscom.h | 3 +++ 9 files changed, 116 insertions(+), 15 deletions(-) diff --git a/asm/head.S b/asm/head.S index 0ed1acdd..67d493ed 100644 --- a/asm/head.S +++ b/asm/head.S @@ -336,6 +336,7 @@ boot_offset: * r28 : PVR * r27 : DTB pointer (or NULL) * r26 : PIR thread mask + * r25 : P9 fused core flag */ .global boot_entry boot_entry: @@ -354,13 +355,21 @@ boot_entry: cmpwi cr0,%r3,PVR_TYPE_P8NVL beq 2f cmpwi cr0,%r3,PVR_TYPE_P9 - beq 1f + beq 3f cmpwi cr0,%r3,PVR_TYPE_P9P - beq 1f + beq 3f attn /* Unsupported CPU type... what do we do ? */ b . /* loop here, just in case attn is disabled */ - /* P8 -> 8 threads */ + /* Check for fused core and set flag */ +3: + li %r3, 0x1e0 + mtspr SPR_SPRC, %r3 + mfspr %r3, SPR_SPRD + andi. %r25, %r3, 1 + beq 1f + + /* P8 or P9 fused -> 8 threads */ 2: li %r26,7 /* Get our reloc offset into r30 */ @@ -382,6 +391,15 @@ boot_entry: LOAD_IMM64(%r3, (MSR_HV | MSR_SF)) mtmsrd %r3,0 + /* If fused, t1 is primary chiplet and must init shared sprs */ + andi. %r3,%r25,1 + beq not_fused + + mfspr %r31,SPR_PIR + andi. %r3,%r31,1 + bnel init_shared_sprs + +not_fused: /* Check our PIR, avoid threads */ mfspr %r31,SPR_PIR and. %r0,%r31,%r26 diff --git a/core/chip.c b/core/chip.c index 65263253..2b9b6ef9 100644 --- a/core/chip.c +++ b/core/chip.c @@ -20,6 +20,7 @@ #include #include #include +#include static struct proc_chip *chips[MAX_CHIPS]; enum proc_chip_quirks proc_chip_quirks; @@ -37,7 +38,10 @@ uint32_t pir_to_chip_id(uint32_t pir) uint32_t pir_to_core_id(uint32_t pir) { if (proc_gen == proc_gen_p9) - return P9_PIR2COREID(pir); + if (this_cpu()->is_fused_core) + return P9_PIRFUSED2NORMALCOREID(pir); + else + return P9_PIR2COREID(pir); else if (proc_gen == proc_gen_p8) return P8_PIR2COREID(pir); else @@ -46,9 +50,12 @@ uint32_t pir_to_core_id(uint32_t pir) uint32_t pir_to_thread_id(uint32_t pir) { - if (proc_gen == proc_gen_p9) - return P9_PIR2THREADID(pir); - else if (proc_gen == proc_gen_p8) + if (proc_gen == proc_gen_p9) { + if (this_cpu()->is_fused_core) + return P9_PIR2FUSEDTHREADID(pir); + else + return P9_PIR2THREADID(pir); + } else if (proc_gen == proc_gen_p8) return P8_PIR2THREADID(pir); else return P7_PIR2THREADID(pir); diff --git a/core/cpu.c b/core/cpu.c index d9d47133..1bcd2b66 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -922,6 +922,14 @@ void cpu_disable_all_threads(struct cpu_thread *cpu) /* XXX Do something to actually stop the core */ } +static int is_fused_core (void) +{ + unsigned int core_thread_state; + mtspr(SPR_SPRC, 0x00000000000001e0ULL); + core_thread_state = mfspr(SPR_SPRD); + return core_thread_state & PPC_BIT(63); +} + static void init_cpu_thread(struct cpu_thread *t, enum cpu_thread_state state, unsigned int pir) @@ -941,6 +949,7 @@ static void init_cpu_thread(struct cpu_thread *t, #ifdef STACK_CHECK_ENABLED t->stack_bot_mark = LONG_MAX; #endif + t->is_fused_core = is_fused_core(); assert(pir == container_of(t, struct cpu_stack, cpu) - cpu_stacks); } @@ -1034,14 +1043,16 @@ void init_boot_cpu(void) " (max %d threads/core)\n", cpu_thread_count); break; case proc_gen_p9: - cpu_thread_count = 4; + if (is_fused_core()) + cpu_thread_count = 8; + else + cpu_thread_count = 4; prlog(PR_INFO, "CPU: P9 generation processor" " (max %d threads/core)\n", cpu_thread_count); break; default: prerror("CPU: Unknown PVR, assuming 1 thread\n"); cpu_thread_count = 1; - cpu_max_pir = mfspr(SPR_PIR); } if (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) { @@ -1169,7 +1180,7 @@ void init_all_cpus(void) /* Iterate all CPUs in the device-tree */ dt_for_each_child(cpus, cpu) { - unsigned int pir, server_no, chip_id; + unsigned int pir, server_no, chip_id, threads; enum cpu_thread_state state; const struct dt_property *p; struct cpu_thread *t, *pt; @@ -1197,6 +1208,14 @@ void init_all_cpus(void) prlog(PR_INFO, "CPU: CPU from DT PIR=0x%04x Server#=0x%x" " State=%d\n", pir, server_no, state); + /* Check max PIR */ + if (cpu_max_pir < (pir + cpu_thread_count - 1)) { + prlog(PR_WARNING, "CPU: CPU potentially out of range" + "PIR=0x%04x MAX=0x%04x !\n", + pir, cpu_max_pir); + continue; + } + /* Setup thread 0 */ assert(pir <= cpu_max_pir); t = pt = &cpu_stacks[pir].cpu; @@ -1222,11 +1241,21 @@ void init_all_cpus(void) /* Add the decrementer width property */ dt_add_property_cells(cpu, "ibm,dec-bits", dec_bits); + if (t->is_fused_core) + dt_add_property(t->node, "ibm,fused-core", NULL, 0); + /* Iterate threads */ p = dt_find_property(cpu, "ibm,ppc-interrupt-server#s"); if (!p) continue; - for (thread = 1; thread < (p->len / 4); thread++) { + threads = p->len / 4; + if (threads > cpu_thread_count) { + prlog(PR_WARNING, "CPU: Threads out of range for PIR 0x%04x" + " threads=%d max=%d\n", + pir, threads, cpu_thread_count); + threads = cpu_thread_count; + } + for (thread = 1; thread < threads; thread++) { prlog(PR_TRACE, "CPU: secondary thread %d found\n", thread); t = &cpu_stacks[pir + thread].cpu; @@ -1412,7 +1441,7 @@ static int64_t cpu_change_all_hid0(struct hid0_change_req *req) assert(jobs); for_each_available_cpu(cpu) { - if (!cpu_is_thread0(cpu)) + if (!cpu_is_thread0(cpu) && !cpu_is_core_chiplet_primary(cpu)) continue; if (cpu == this_cpu()) continue; diff --git a/core/fast-reboot.c b/core/fast-reboot.c index 22160b65..be70c227 100644 --- a/core/fast-reboot.c +++ b/core/fast-reboot.c @@ -236,7 +236,7 @@ static void cleanup_cpu_state(void) struct cpu_thread *cpu = this_cpu(); /* Per core cleanup */ - if (cpu_is_thread0(cpu)) { + if (cpu_is_thread0(cpu) | cpu_is_core_chiplet_primary(cpu)) { /* Shared SPRs whacked back to normal */ /* XXX Update the SLW copies ! Also dbl check HIDs etc... */ diff --git a/hdata/test/hdata_to_dt.c b/hdata/test/hdata_to_dt.c index a5f152e8..cddb1d43 100644 --- a/hdata/test/hdata_to_dt.c +++ b/hdata/test/hdata_to_dt.c @@ -47,7 +47,11 @@ struct spira_ntuple; static void *ntuple_addr(const struct spira_ntuple *n); /* Stuff which core expects. */ -#define __this_cpu ((struct cpu_thread *)NULL) +struct cpu_thread *my_fake_cpu; +static struct cpu_thread *this_cpu(void) +{ + return my_fake_cpu; +} unsigned long tb_hz = 512000000; @@ -84,6 +88,7 @@ unsigned long tb_hz = 512000000; struct cpu_thread { uint32_t pir; uint32_t chip_id; + bool is_fused_core; }; struct cpu_job *__cpu_queue_job(struct cpu_thread *cpu, const char *name, @@ -105,6 +110,8 @@ static inline struct cpu_job *cpu_queue_job(struct cpu_thread *cpu, struct cpu_thread __boot_cpu, *boot_cpu = &__boot_cpu; static unsigned long fake_pvr = PVR_P7; +unsigned int cpu_thread_count = 8; + static inline unsigned long mfspr(unsigned int spr) { assert(spr == SPR_PVR); diff --git a/hw/xive.c b/hw/xive.c index b863b634..c9f3f07d 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -3299,7 +3299,7 @@ static void xive_init_cpu(struct cpu_thread *c) * of a pair is present we just do the setup for each of them, which * is harmless. */ - if (cpu_is_thread0(c)) + if (cpu_is_thread0(c) || cpu_is_core_chiplet_primary(c)) xive_configure_ex_special_bar(x, c); /* Initialize the state structure */ diff --git a/include/chip.h b/include/chip.h index d6e7e355..a73a52d7 100644 --- a/include/chip.h +++ b/include/chip.h @@ -91,6 +91,26 @@ * thus we have a 6-bit core number. * * Note: XIVE Only supports 4-bit chip numbers ... + * + * Upper PIR Bits + * -------------- + * + * Normal-Core Mode: + * 57:61 CoreID + * 62:63 ThreadID + * + * Fused-Core Mode: + * 57:59 FusedQuadID + * 60 FusedCoreID + * 61:63 FusedThreadID + * + * FusedCoreID 0 contains normal-core chiplet 0 and 1 + * FusedCoreID 1 contains normal-core chiplet 2 and 3 + * + * Fused cores have interleaved threads: + * core chiplet 0/2 = t0, t2, t4, t6 + * core chiplet 1/3 = t1, t3, t5, t7 + * */ #define P9_PIR2GCID(pir) (((pir) >> 8) & 0x7f) @@ -102,6 +122,17 @@ #define P9_GCID2CHIPID(gcid) ((gcid) & 0x7) +#define P9_PIR2FUSEDQUADID(pir) (((pir) >> 4) & 0x7) + +#define P9_PIR2FUSEDCOREID(pir) (((pir) >> 3) & 0x1) + +#define P9_PIR2FUSEDTHREADID(pir) ((pir) & 0x7) + +#define P9_PIRFUSED2NORMALCOREID(pir) \ + (P9_PIR2FUSEDQUADID(pir) << 2) | \ + (P9_PIR2FUSEDCOREID(pir) << 1) | \ + (P9_PIR2FUSEDTHREADID(pir) & 1) + /* P9 specific ones mostly used by XIVE */ #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff) #define P9_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu)) diff --git a/include/cpu.h b/include/cpu.h index 06d5c0d1..009ae52c 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -54,6 +54,7 @@ struct cpu_thread { uint32_t server_no; uint32_t chip_id; bool is_secondary; + bool is_fused_core; struct cpu_thread *primary; enum cpu_thread_state state; struct dt_node *node; @@ -251,6 +252,11 @@ static inline bool cpu_is_thread0(struct cpu_thread *cpu) return cpu->primary == cpu; } +static inline bool cpu_is_core_chiplet_primary(struct cpu_thread *cpu) +{ + return cpu->is_fused_core & (cpu_get_thread_index(cpu) == 1); +} + static inline bool cpu_is_sibling(struct cpu_thread *cpu1, struct cpu_thread *cpu2) { diff --git a/include/xscom.h b/include/xscom.h index 98532240..0885adf3 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -123,6 +123,9 @@ /* * Additional useful definitions for P9 + * + * Note: In all of these, the core numbering is the + * *normal* (small) core number. */ /* An EQ is a quad (also named an EP) */ From patchwork Sun Mar 24 17:25:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1063316 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44S47b2MNmz9sRk for ; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 24 Mar 2019 17:26:13 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2OHQCdx42532988 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 24 Mar 2019 17:26:12 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 83F7542045; Sun, 24 Mar 2019 17:26:12 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4B45142041; Sun, 24 Mar 2019 17:26:11 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.199.41.162]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 24 Mar 2019 17:26:11 +0000 (GMT) From: Vaidyanathan Srinivasan To: Stewart Smith Date: Sun, 24 Mar 2019 22:55:37 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> References: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19032417-0016-0000-0000-000002669414 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032417-0017-0000-0000-000032C1BF66 Message-Id: <20190324172543.12625-3-svaidy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-24_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903240134 Subject: [Skiboot] [PATCH v3 2/8] xive: Set the fused core mode properly X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt Set or clear the fused core mode bit in the XIVE inits properly. While HostBoot is supposed to do it, I prefer not depending on it doing the right thing, since we already configure that register ourselves anyway. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling --- hw/xive.c | 4 ++++ include/xive.h | 1 + 2 files changed, 5 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index c9f3f07d..4444b649 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1733,6 +1733,10 @@ static bool xive_config_init(struct xive *x) val |= PC_TCTXT_CFG_LGS_EN; /* Disable pressure relief as we hijack the field in the VPs */ val &= ~PC_TCTXT_CFG_STORE_ACK; + if (this_cpu()->is_fused_core) + val |= PC_TCTXT_CFG_FUSE_CORE_EN; + else + val &= ~PC_TCTXT_CFG_FUSE_CORE_EN; xive_regw(x, PC_TCTXT_CFG, val); xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val); diff --git a/include/xive.h b/include/xive.h index acc696a4..f4365efc 100644 --- a/include/xive.h +++ b/include/xive.h @@ -86,6 +86,7 @@ #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) #define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) #define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) +#define PC_TCTXT_CFG_FUSE_CORE_EN PPC_BIT(4) #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) #define PC_TCTXT_CHIPID PPC_BITMASK(12,15) From patchwork Sun Mar 24 17:25:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1063317 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44S47q3GPYz9sSG for ; Mon, 25 Mar 2019 04:26:47 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44S47p6ZWRzDqLl for ; Mon, 25 Mar 2019 04:26:46 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44S47N052TzDqLj for ; Mon, 25 Mar 2019 04:26:23 +1100 (AEDT) Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2OHNxN8097640 for ; Sun, 24 Mar 2019 13:26:21 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2re284evr9-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 24 Mar 2019 13:26:21 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 24 Mar 2019 17:26:16 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2OHQFaP58196154 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 24 Mar 2019 17:26:15 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2854D42041; Sun, 24 Mar 2019 17:26:15 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E43A24203F; Sun, 24 Mar 2019 17:26:13 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.199.41.162]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 24 Mar 2019 17:26:13 +0000 (GMT) From: Vaidyanathan Srinivasan To: Stewart Smith Date: Sun, 24 Mar 2019 22:55:38 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> References: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19032417-4275-0000-0000-0000031EB471 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032417-4276-0000-0000-0000382D4407 Message-Id: <20190324172543.12625-4-svaidy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-24_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=822 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903240134 Subject: [Skiboot] [PATCH v3 3/8] chip: Fix pir_to_thread_id for fused cores X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt pir_to_core_id() and pir_to_thread_id() are extensively used by the direct controls code and are expected to return the "normal" (non-fused, aka EC) core/thread IDs. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling --- core/chip.c | 6 +++--- include/chip.h | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/core/chip.c b/core/chip.c index 2b9b6ef9..902327e1 100644 --- a/core/chip.c +++ b/core/chip.c @@ -37,12 +37,12 @@ uint32_t pir_to_chip_id(uint32_t pir) uint32_t pir_to_core_id(uint32_t pir) { - if (proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p9) { if (this_cpu()->is_fused_core) return P9_PIRFUSED2NORMALCOREID(pir); else return P9_PIR2COREID(pir); - else if (proc_gen == proc_gen_p8) + } else if (proc_gen == proc_gen_p8) return P8_PIR2COREID(pir); else return P7_PIR2COREID(pir); @@ -52,7 +52,7 @@ uint32_t pir_to_thread_id(uint32_t pir) { if (proc_gen == proc_gen_p9) { if (this_cpu()->is_fused_core) - return P9_PIR2FUSEDTHREADID(pir); + return P9_PIRFUSED2NORMALTHREADID(pir); else return P9_PIR2THREADID(pir); } else if (proc_gen == proc_gen_p8) diff --git a/include/chip.h b/include/chip.h index a73a52d7..afb2e3e9 100644 --- a/include/chip.h +++ b/include/chip.h @@ -133,6 +133,8 @@ (P9_PIR2FUSEDCOREID(pir) << 1) | \ (P9_PIR2FUSEDTHREADID(pir) & 1) +#define P9_PIRFUSED2NORMALTHREADID(pir) (((pir) >> 1) & 0x3) + /* P9 specific ones mostly used by XIVE */ #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff) #define P9_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu)) @@ -258,6 +260,11 @@ struct proc_chip { }; extern uint32_t pir_to_chip_id(uint32_t pir); + +/* + * Note: In P9 fused-core mode, these will return the "normal" + * core ID and thread ID (ie, thread ID 0..3) + */ extern uint32_t pir_to_core_id(uint32_t pir); extern uint32_t pir_to_thread_id(uint32_t pir); From patchwork Sun Mar 24 17:25:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1063318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44S48364Dhz9sRk for ; Mon, 25 Mar 2019 04:26:59 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44S4834rS6zDqLq for ; Mon, 25 Mar 2019 04:26:59 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44S47Q2KKQzDqMd for ; Mon, 25 Mar 2019 04:26:25 +1100 (AEDT) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2OHNlbT051115 for ; Sun, 24 Mar 2019 13:26:24 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2re28df8dj-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 24 Mar 2019 13:26:23 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 24 Mar 2019 17:26:18 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2OHQHvB37224600 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 24 Mar 2019 17:26:17 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C26564203F; Sun, 24 Mar 2019 17:26:17 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 88D5242041; Sun, 24 Mar 2019 17:26:16 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.199.41.162]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 24 Mar 2019 17:26:16 +0000 (GMT) From: Vaidyanathan Srinivasan To: Stewart Smith Date: Sun, 24 Mar 2019 22:55:39 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> References: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19032417-0008-0000-0000-000002D0FB87 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032417-0009-0000-0000-0000223D209C Message-Id: <20190324172543.12625-5-svaidy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-24_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903240134 Subject: [Skiboot] [PATCH v3 4/8] cpu: Keep track of the "ec_primary" in big core more X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt The "EC" primary is the primary thread of an EC, ie, the corresponding small core "half" of the big core where the thread resides. It will be necessary for the direct controls to target the right half when doing special wakeups among others. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling --- core/cpu.c | 20 ++++++++++++++------ include/cpu.h | 1 + 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index 1bcd2b66..010a2570 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -832,9 +832,11 @@ struct cpu_thread *first_ungarded_cpu(void) struct cpu_thread *next_ungarded_primary(struct cpu_thread *cpu) { + bool is_primary; do { cpu = next_cpu(cpu); - } while(cpu && (cpu->state == cpu_state_unavailable || cpu->primary != cpu)); + is_primary = cpu == cpu->primary || cpu == cpu->ec_primary; + } while(cpu && (cpu->state == cpu_state_unavailable || !is_primary)); return cpu; } @@ -1183,7 +1185,7 @@ void init_all_cpus(void) unsigned int pir, server_no, chip_id, threads; enum cpu_thread_state state; const struct dt_property *p; - struct cpu_thread *t, *pt; + struct cpu_thread *t, *pt0, *pt1; /* Skip cache nodes */ if (strcmp(dt_prop_get(cpu, "device_type"), "cpu")) @@ -1218,14 +1220,18 @@ void init_all_cpus(void) /* Setup thread 0 */ assert(pir <= cpu_max_pir); - t = pt = &cpu_stacks[pir].cpu; + t = pt0 = &cpu_stacks[pir].cpu; if (t != boot_cpu) { init_cpu_thread(t, state, pir); /* Each cpu gets its own later in init_trace_buffers */ t->trace = boot_cpu->trace; } + if (t->is_fused_core) + pt1 = &cpu_stacks[pir + 1].cpu; + else + pt1 = pt0; t->server_no = server_no; - t->primary = t; + t->primary = t->ec_primary = t; t->node = cpu; t->chip_id = chip_id; t->icp_regs = NULL; /* Will be set later */ @@ -1263,10 +1269,12 @@ void init_all_cpus(void) t->trace = boot_cpu->trace; t->server_no = ((const u32 *)p->prop)[thread]; t->is_secondary = true; - t->primary = pt; + t->is_fused_core = pt0->is_fused_core; + t->primary = pt0; + t->ec_primary = (thread & 1) ? pt1 : pt0; t->node = cpu; t->chip_id = chip_id; - t->core_hmi_state_ptr = &pt->core_hmi_state; + t->core_hmi_state_ptr = &pt0->core_hmi_state; } prlog(PR_INFO, "CPU: %d secondary threads\n", thread); } diff --git a/include/cpu.h b/include/cpu.h index 009ae52c..ba222882 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -56,6 +56,7 @@ struct cpu_thread { bool is_secondary; bool is_fused_core; struct cpu_thread *primary; + struct cpu_thread *ec_primary; enum cpu_thread_state state; struct dt_node *node; struct trace_info *trace; From patchwork Sun Mar 24 17:25:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1063319 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44S48K4CZrz9sRy for ; Mon, 25 Mar 2019 04:27:13 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44S48K3DT2zDqMk for ; Mon, 25 Mar 2019 04:27:13 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44S47R1fh8zDqLq for ; Mon, 25 Mar 2019 04:26:27 +1100 (AEDT) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2OHNorh079326 for ; Sun, 24 Mar 2019 13:26:24 -0400 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2re23978xq-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 24 Mar 2019 13:26:24 -0400 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 24 Mar 2019 17:26:21 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2OHQKCU60555438 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 24 Mar 2019 17:26:20 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 689E04203F; Sun, 24 Mar 2019 17:26:20 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2F13F42045; Sun, 24 Mar 2019 17:26:19 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.199.41.162]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 24 Mar 2019 17:26:18 +0000 (GMT) From: Vaidyanathan Srinivasan To: Stewart Smith Date: Sun, 24 Mar 2019 22:55:40 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> References: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19032417-0016-0000-0000-000002669416 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032417-0017-0000-0000-000032C1BF68 Message-Id: <20190324172543.12625-6-svaidy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-24_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=916 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903240134 Subject: [Skiboot] [PATCH v3 5/8] direct-ctl: Use the EC primary for special wakeups X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling --- core/direct-controls.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/core/direct-controls.c b/core/direct-controls.c index 1d0f6818..e8b526c3 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -550,7 +550,7 @@ static int p9_sreset_thread(struct cpu_thread *cpu) int dctl_set_special_wakeup(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc = OPAL_SUCCESS; if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) @@ -572,7 +572,7 @@ int dctl_set_special_wakeup(struct cpu_thread *t) int dctl_clear_special_wakeup(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc = OPAL_SUCCESS; if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) @@ -597,7 +597,7 @@ out: int dctl_core_is_gated(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; uint32_t chip_id = pir_to_chip_id(c->pir); uint32_t core_id = pir_to_core_id(c->pir); uint32_t sshhyp_addr; @@ -620,7 +620,7 @@ int dctl_core_is_gated(struct cpu_thread *t) static int dctl_stop(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc; if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) @@ -644,7 +644,7 @@ static int dctl_stop(struct cpu_thread *t) static int dctl_cont(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc; if (proc_gen != proc_gen_p9) @@ -671,7 +671,7 @@ static int dctl_cont(struct cpu_thread *t) */ static int dctl_sreset(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc; if (proc_gen != proc_gen_p9 && proc_gen != proc_gen_p8) From patchwork Sun Mar 24 17:25:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1063320 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44S48Y1XKLz9sRy for ; Mon, 25 Mar 2019 04:27:25 +1100 (AEDT) Authentication-Results: ozlabs.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 24 Mar 2019 17:26:24 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2OHQN6p13435022 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 24 Mar 2019 17:26:23 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0F71442041; Sun, 24 Mar 2019 17:26:23 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C9B544203F; Sun, 24 Mar 2019 17:26:21 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.199.41.162]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 24 Mar 2019 17:26:21 +0000 (GMT) From: Vaidyanathan Srinivasan To: Stewart Smith Date: Sun, 24 Mar 2019 22:55:41 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> References: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19032417-0020-0000-0000-00000327027A X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032417-0021-0000-0000-00002179347F Message-Id: <20190324172543.12625-7-svaidy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-24_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903240134 Subject: [Skiboot] [PATCH v3 6/8] slw: Limit fused cores P9 to STOP0/1/2 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt Linux doesn't know how to properly restore state on "both halves" of a fused core, so limit ourselves to STOP states that don't require HV state restore for bare metal kernels (KVM is still broken) until we add a new representation for STOP states. The new representation will have per-state versioning so that we can control their individual enablement based on whether the OS has the necessary workarounds to make them work. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling Signed-off-by: Vaidyanathan Srinivasan --- hw/slw.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/hw/slw.c b/hw/slw.c index adbfdce9..c85f2d0f 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -701,6 +701,83 @@ static struct cpu_idle_states power9_mambo_cpu_idle_states[] = { }; +/* + * cpu_idle_states for fused core configuration + * These will be a subset of power9 idle states. + */ +static struct cpu_idle_states power9_fusedcore_cpu_idle_states[] = { + { + .name = "stop0_lite", /* Enter stop0 with no state loss */ + .latency_ns = 1000, + .residency_ns = 10000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 0*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(0) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3), + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + { + .name = "stop0", + .latency_ns = 2000, + .residency_ns = 20000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(0) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + + /* stop1_lite has been removed since it adds no additional benefit over stop0_lite */ + + { + .name = "stop1", + .latency_ns = 5000, + .residency_ns = 50000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(1) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + /* + * stop2_lite has been removed since currently it adds minimal benefit over stop2. + * However, the benefit is eclipsed by the time required to ungate the clocks + */ + + { + .name = "stop2", + .latency_ns = 10000, + .residency_ns = 100000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(2) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, +}; + static void slw_late_init_p9(struct proc_chip *chip) { struct cpu_thread *c; @@ -784,6 +861,9 @@ void add_cpu_idle_state_properties(void) if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) { states = power9_mambo_cpu_idle_states; nr_states = ARRAY_SIZE(power9_mambo_cpu_idle_states); + } else if (this_cpu()->is_fused_core) { + states = power9_fusedcore_cpu_idle_states; + nr_states = ARRAY_SIZE(power9_fusedcore_cpu_idle_states); } else { states = power9_cpu_idle_states; nr_states = ARRAY_SIZE(power9_cpu_idle_states); From patchwork Sun Mar 24 17:25:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1063322 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44S48p4ppxz9sRy for ; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 24 Mar 2019 17:26:26 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2OHQP8A59834604 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 24 Mar 2019 17:26:25 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A9CD24203F; Sun, 24 Mar 2019 17:26:25 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 708B142041; Sun, 24 Mar 2019 17:26:24 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.199.41.162]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 24 Mar 2019 17:26:24 +0000 (GMT) From: Vaidyanathan Srinivasan To: Stewart Smith Date: Sun, 24 Mar 2019 22:55:42 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> References: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19032417-0028-0000-0000-00000357B809 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032417-0029-0000-0000-000024166810 Message-Id: <20190324172543.12625-8-svaidy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-24_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903240134 Subject: [Skiboot] [PATCH v3 7/8] cpu: Make cpu_get_core_index() return the fused core number X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt cpu_get_core_index() currently uses pir_to_core_id() which returns an EC number always (ie, a normal core number) even in fused core mode. This is inconsistent with cpu_get_thread_index() which returns a thread within a fused core (0...7) on P9. So let's make things consistent and document it. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling --- core/chip.c | 13 +++++++++++++ core/cpu.c | 2 +- include/chip.h | 5 +++++ include/cpu.h | 6 ++++++ 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/core/chip.c b/core/chip.c index 902327e1..60c7a6e7 100644 --- a/core/chip.c +++ b/core/chip.c @@ -48,6 +48,19 @@ uint32_t pir_to_core_id(uint32_t pir) return P7_PIR2COREID(pir); } +uint32_t pir_to_fused_core_id(uint32_t pir) +{ + if (proc_gen == proc_gen_p9) { + if (this_cpu()->is_fused_core) + return P9_PIR2FUSEDCOREID(pir); + else + return P9_PIR2COREID(pir); + } else if (proc_gen == proc_gen_p8) + return P8_PIR2COREID(pir); + else + return P7_PIR2COREID(pir); +} + uint32_t pir_to_thread_id(uint32_t pir) { if (proc_gen == proc_gen_p9) { diff --git a/core/cpu.c b/core/cpu.c index 010a2570..0ce09a33 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -875,7 +875,7 @@ struct cpu_thread *first_available_core_in_chip(u32 chip_id) uint32_t cpu_get_core_index(struct cpu_thread *cpu) { - return pir_to_core_id(cpu->pir); + return pir_to_fused_core_id(cpu->pir); } void cpu_remove_node(const struct cpu_thread *t) diff --git a/include/chip.h b/include/chip.h index afb2e3e9..72d4bafe 100644 --- a/include/chip.h +++ b/include/chip.h @@ -268,6 +268,11 @@ extern uint32_t pir_to_chip_id(uint32_t pir); extern uint32_t pir_to_core_id(uint32_t pir); extern uint32_t pir_to_thread_id(uint32_t pir); +/* In P9 fused core mode, this is the "fused" core ID, in + * normal core mode or P8, this is the same as pir_to_core_id + */ +extern uint32_t pir_to_fused_core_id(uint32_t pir); + extern struct proc_chip *next_chip(struct proc_chip *chip); #define for_each_chip(__c) for (__c=next_chip(NULL); __c; __c=next_chip(__c)) diff --git a/include/cpu.h b/include/cpu.h index ba222882..52d424e6 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -233,6 +233,12 @@ static inline __nomcount struct cpu_thread *this_cpu(void) return __this_cpu; } +/* + * Note: On POWER9 fused core, cpu_get_thread_index() and cpu_get_core_index() + * return respectively the thread number within a fused core (0..7) and + * the fused core number. If you want the EC (small core) number, you have + * to use the low level pir_to_core_id() and pir_to_thread_id(). + */ /* Get the thread # of a cpu within the core */ static inline uint32_t cpu_get_thread_index(struct cpu_thread *cpu) { From patchwork Sun Mar 24 17:25:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1063323 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44S493025Xz9sRk for ; Mon, 25 Mar 2019 04:27:51 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44S4925vTTzDqLr for ; Mon, 25 Mar 2019 04:27:50 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44S47c3JbwzDqMG for ; Mon, 25 Mar 2019 04:26:36 +1100 (AEDT) Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2OHO5RS036287 for ; Sun, 24 Mar 2019 13:26:34 -0400 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0b-001b2d01.pphosted.com with ESMTP id 2re21f79qu-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 24 Mar 2019 13:26:33 -0400 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 24 Mar 2019 17:26:29 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2OHQSBl40108104 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 24 Mar 2019 17:26:28 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5265E4203F; Sun, 24 Mar 2019 17:26:28 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 18F3842041; Sun, 24 Mar 2019 17:26:27 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.199.41.162]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 24 Mar 2019 17:26:26 +0000 (GMT) From: Vaidyanathan Srinivasan To: Stewart Smith Date: Sun, 24 Mar 2019 22:55:43 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> References: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19032417-0020-0000-0000-00000327027B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032417-0021-0000-0000-000021793480 Message-Id: <20190324172543.12625-9-svaidy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-24_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903240134 Subject: [Skiboot] [PATCH v3 8/8] imc: Use pir_to_core_id() rather than cpu_get_core_index() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt The IMC HW targets HW ECs, not fused cores on P9 Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling --- hw/imc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/imc.c b/hw/imc.c index 354a5454..cf10701e 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -630,7 +630,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu * pdbar in specific scom ports. port_id are in * pdbar_scom_index[] and htm_scom_index[]. */ - phys_core_id = cpu_get_core_index(c); + phys_core_id = pir_to_core_id(c->pir); port_id = phys_core_id % 4; if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) @@ -750,7 +750,7 @@ static int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir) * Core IMC hardware mandates setting of htm_mode in specific * scom ports (port_id are in htm_scom_index[]) */ - phys_core_id = cpu_get_core_index(c); + phys_core_id = pir_to_core_id(c->pir); port_id = phys_core_id % 4; if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) @@ -811,7 +811,7 @@ static int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir) * Core IMC hardware mandates setting of htm_mode in specific * scom ports (port_id are in htm_scom_index[]) */ - phys_core_id = cpu_get_core_index(c); + phys_core_id = pir_to_core_id(c->pir); port_id = phys_core_id % 4; if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)