From patchwork Tue Mar 12 20:35:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1055748 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Jmvg6b0Lz9s9h for ; Wed, 13 Mar 2019 07:35:59 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44Jmvg4VmZzDqDN for ; Wed, 13 Mar 2019 07:35:59 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Jmv13qWbzDqCH for ; Wed, 13 Mar 2019 07:35:25 +1100 (AEDT) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2CKYNJS051044 for ; Tue, 12 Mar 2019 16:35:23 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2r6kep9j56-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Mar 2019 16:35:22 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Mar 2019 20:35:18 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2CKZHU033882334 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Mar 2019 20:35:17 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 39A5B4204B; Tue, 12 Mar 2019 20:35:17 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E112B42047; Tue, 12 Mar 2019 20:35:16 +0000 (GMT) Received: from borneo.home (unknown [9.145.16.6]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Mar 2019 20:35:16 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org, andrew.donnellan@au1.ibm.com Date: Tue, 12 Mar 2019 21:35:09 +0100 X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190312203515.18520-1-fbarrat@linux.ibm.com> References: <20190312203515.18520-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19031220-4275-0000-0000-0000031A2D66 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19031220-4276-0000-0000-000038289960 Message-Id: <20190312203515.18520-2-fbarrat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-12_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=955 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903120139 Subject: [Skiboot] [PATCH v2 1/7] npu2-opencapi: Rework ODL register access X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clombard@linux.ibm.com, arbab@linux.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" ODL registers used to control the opencapi link state have an address built on a base address and an offset for each brick which can be computed instead of hard-coded individually for each brick. Rework how we access the ODL registers, to avoid repeating switch statements all over the place. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan Reviewed-by: Christophe Lombard --- v2: no change hw/npu2-hw-procedures.c | 17 +------ hw/npu2-opencapi.c | 109 ++++------------------------------------ include/npu2-regs.h | 30 ++++------- 3 files changed, 21 insertions(+), 135 deletions(-) diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 627a8428..a10ccb7c 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -981,22 +981,7 @@ void npu2_opencapi_bump_ui_lane(struct npu2_dev *dev) uint64_t status_xscom; int lane, bit = 7; - switch (dev->brick_index) { - case 2: - status_xscom = OB0_ODL0_TRAINING_STATUS; - break; - case 3: - status_xscom = OB0_ODL1_TRAINING_STATUS; - break; - case 4: - status_xscom = OB3_ODL1_TRAINING_STATUS; - break; - case 5: - status_xscom = OB3_ODL0_TRAINING_STATUS; - break; - default: - assert(false); - } + status_xscom = OB_ODL_TRAINING_STATUS(dev->brick_index); xscom_read(dev->npu->chip_id, status_xscom, ®); reg = GETFIELD(OB_ODL_TRAINING_STATUS_STS_RX_PATTERN_B, reg); diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index aa3c434e..6ad561c4 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -128,24 +128,11 @@ static inline uint64_t index_to_block(uint64_t index) { } } -static uint64_t get_odl_status(uint32_t gcid, uint64_t index) { +static uint64_t get_odl_status(uint32_t gcid, uint64_t index) +{ uint64_t reg, status_xscom; - switch (index) { - case 2: - status_xscom = OB0_ODL0_STATUS; - break; - case 3: - status_xscom = OB0_ODL1_STATUS; - break; - case 4: - status_xscom = OB3_ODL1_STATUS; - break; - case 5: - status_xscom = OB3_ODL0_STATUS; - break; - default: - assert(false); - } + + status_xscom = OB_ODL_STATUS(index); xscom_read(gcid, status_xscom, ®); return reg; } @@ -154,22 +141,7 @@ static uint64_t get_odl_training_status(uint32_t gcid, uint64_t index) { uint64_t status_xscom, reg; - switch (index) { - case 2: - status_xscom = OB0_ODL0_TRAINING_STATUS; - break; - case 3: - status_xscom = OB0_ODL1_TRAINING_STATUS; - break; - case 4: - status_xscom = OB3_ODL1_TRAINING_STATUS; - break; - case 5: - status_xscom = OB3_ODL0_TRAINING_STATUS; - break; - default: - assert(false); - } + status_xscom = OB_ODL_TRAINING_STATUS(index); xscom_read(gcid, status_xscom, ®); return reg; } @@ -178,22 +150,7 @@ static uint64_t get_odl_endpoint_info(uint32_t gcid, uint64_t index) { uint64_t status_xscom, reg; - switch (index) { - case 2: - status_xscom = OB0_ODL0_ENDPOINT_INFO; - break; - case 3: - status_xscom = OB0_ODL1_ENDPOINT_INFO; - break; - case 4: - status_xscom = OB3_ODL1_ENDPOINT_INFO; - break; - case 5: - status_xscom = OB3_ODL0_ENDPOINT_INFO; - break; - default: - assert(false); - } + status_xscom = OB_ODL_ENDPOINT_INFO(index); xscom_read(gcid, status_xscom, ®); return reg; } @@ -936,23 +893,7 @@ static void reset_odl(uint32_t gcid, struct npu2_dev *dev) { uint64_t reg, config_xscom; - switch (dev->brick_index) { - case 2: - config_xscom = OB0_ODL0_CONFIG; - break; - case 3: - config_xscom = OB0_ODL1_CONFIG; - break; - case 4: - config_xscom = OB3_ODL1_CONFIG; - break; - case 5: - config_xscom = OB3_ODL0_CONFIG; - break; - default: - assert(false); - } - + config_xscom = OB_ODL_CONFIG(dev->brick_index); /* Reset ODL */ reg = OB_ODL_CONFIG_RESET; reg = SETFIELD(OB_ODL_CONFIG_VERSION, reg, 0b000001); @@ -972,23 +913,7 @@ static void set_init_pattern(uint32_t gcid, struct npu2_dev *dev) { uint64_t reg, config_xscom; - switch (dev->brick_index) { - case 2: - config_xscom = OB0_ODL0_CONFIG; - break; - case 3: - config_xscom = OB0_ODL1_CONFIG; - break; - case 4: - config_xscom = OB3_ODL1_CONFIG; - break; - case 5: - config_xscom = OB3_ODL0_CONFIG; - break; - default: - assert(false); - } - + config_xscom = OB_ODL_CONFIG(dev->brick_index); /* Transmit Pattern A */ xscom_read(gcid, config_xscom, ®); reg = SETFIELD(OB_ODL_CONFIG_TRAIN_MODE, reg, 0b0001); @@ -999,23 +924,7 @@ static void start_training(uint32_t gcid, struct npu2_dev *dev) { uint64_t reg, config_xscom; - switch (dev->brick_index) { - case 2: - config_xscom = OB0_ODL0_CONFIG; - break; - case 3: - config_xscom = OB0_ODL1_CONFIG; - break; - case 4: - config_xscom = OB3_ODL1_CONFIG; - break; - case 5: - config_xscom = OB3_ODL0_CONFIG; - break; - default: - assert(false); - } - + config_xscom = OB_ODL_CONFIG(dev->brick_index); /* Start training */ xscom_read(gcid, config_xscom, ®); reg = SETFIELD(OB_ODL_CONFIG_TRAIN_MODE, reg, 0b1000); diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 38087aab..5190aeb7 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -725,10 +725,11 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define PU_IOE_PB_FP_CFG_FP1_FMR_DISABLE PPC_BIT(52) #define PU_IOE_PB_FP_CFG_FP1_PRS_DISABLE PPC_BIT(57) -#define OB0_ODL0_CONFIG 0x901082A -#define OB0_ODL1_CONFIG 0x901082B -#define OB3_ODL0_CONFIG 0xC01082A -#define OB3_ODL1_CONFIG 0xC01082B +#define OB_ODL_OFFSET(brick_index) \ + ((((brick_index - 2) >> 1) * 0x3000000) + ((brick_index == 3 || brick_index == 4) ? 1 : 0)) + +#define OB_ODL_CONFIG(brick_index) \ + (0x901082A + OB_ODL_OFFSET(brick_index)) #define OB_ODL_CONFIG_RESET PPC_BIT(0) #define OB_ODL_CONFIG_VERSION PPC_BITMASK(2, 7) #define OB_ODL_CONFIG_TRAIN_MODE PPC_BITMASK(8, 11) @@ -737,26 +738,17 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define OB_ODL_CONFIG_PHY_CNTR_LIMIT PPC_BITMASK(20, 23) #define OB_ODL_CONFIG_DEBUG_ENABLE PPC_BIT(33) #define OB_ODL_CONFIG_FWD_PROGRESS_TIMER PPC_BITMASK(40, 43) - -#define OB0_ODL0_STATUS 0x901082C -#define OB0_ODL1_STATUS 0x901082D -#define OB3_ODL0_STATUS 0xC01082C -#define OB3_ODL1_STATUS 0xC01082D +#define OB_ODL_STATUS(brick_index) \ + (0x901082C + OB_ODL_OFFSET(brick_index)) #define OB_ODL_STATUS_TRAINED_MODE PPC_BITMASK(0,3) #define OB_ODL_STATUS_RX_TRAINED_LANES PPC_BITMASK(16, 23) #define OB_ODL_STATUS_TX_TRAINED_LANES PPC_BITMASK(24, 31) #define OB_ODL_STATUS_TRAINING_STATE_MACHINE PPC_BITMASK(49, 51) - -#define OB0_ODL0_TRAINING_STATUS 0x901082E -#define OB0_ODL1_TRAINING_STATUS 0x901082F -#define OB3_ODL0_TRAINING_STATUS 0xC01082E -#define OB3_ODL1_TRAINING_STATUS 0xC01082F +#define OB_ODL_TRAINING_STATUS(brick_index) \ + (0x901082E + OB_ODL_OFFSET(brick_index)) #define OB_ODL_TRAINING_STATUS_STS_RX_PATTERN_B PPC_BITMASK(8, 15) - -#define OB0_ODL0_ENDPOINT_INFO 0x9010832 -#define OB0_ODL1_ENDPOINT_INFO 0x9010833 -#define OB3_ODL0_ENDPOINT_INFO 0xC010832 -#define OB3_ODL1_ENDPOINT_INFO 0xC010833 +#define OB_ODL_ENDPOINT_INFO(brick_index) \ + (0x9010832 + OB_ODL_OFFSET(brick_index)) /* Registers and bits used to clear the L2 and L3 cache */ #define L2_PRD_PURGE_CMD_REG 0x1080E From patchwork Tue Mar 12 20:35:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1055752 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44JmwR1C2hz9s3q for ; Wed, 13 Mar 2019 07:36:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44JmwR05wSzDqF6 for ; Wed, 13 Mar 2019 07:36:39 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Jmv41wt1zDq77 for ; Wed, 13 Mar 2019 07:35:27 +1100 (AEDT) Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2CKYNF5099142 for ; Tue, 12 Mar 2019 16:35:24 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2r6k3atkew-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Mar 2019 16:35:24 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Mar 2019 20:35:20 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2CKZIlo33685522 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Mar 2019 20:35:18 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 92B4542049; Tue, 12 Mar 2019 20:35:18 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4E4BE4204C; Tue, 12 Mar 2019 20:35:18 +0000 (GMT) Received: from borneo.home (unknown [9.145.16.6]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Mar 2019 20:35:18 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org, andrew.donnellan@au1.ibm.com Date: Tue, 12 Mar 2019 21:35:10 +0100 X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190312203515.18520-1-fbarrat@linux.ibm.com> References: <20190312203515.18520-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19031220-4275-0000-0000-0000031A2D67 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19031220-4276-0000-0000-000038289961 Message-Id: <20190312203515.18520-3-fbarrat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-12_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903120139 Subject: [Skiboot] [PATCH v2 2/7] npu2-opencapi: Setup perf counters to detect CRC errors X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clombard@linux.ibm.com, arbab@linux.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" It's possible to set up performance counters for the PLL to detect various conditions for the links in nvlink or opencapi mode. Since those counters are currently unused, let's configure them when an obus is in opencapi mode to detect CRC errors on the link. Each link has two counters: - CRC error detected by the host - CRC error detected by the DLx (NAK received by the host) We also dump the counters shortly after the link trains, but they can be read multiple times through cronus, pdbg or linux. The counters are configured to be reset after each read. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan Reviewed-by: Christophe Lombard --- v2: no change hw/npu2-opencapi.c | 62 +++++++++++++++++++++++++++++++++++++++++++++ include/npu2-regs.h | 17 +++++++++++++ 2 files changed, 79 insertions(+) diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index 6ad561c4..6d642cde 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -909,6 +909,66 @@ static void reset_odl(uint32_t gcid, struct npu2_dev *dev) xscom_write(gcid, config_xscom, reg); } +static void setup_perf_counters(struct npu2_dev *dev) +{ + uint64_t addr, reg, link; + + /* + * setup the DLL perf counters to check CRC errors detected by + * the NPU or the adapter. + * + * Counter 0: link 0/ODL0, CRC error detected by ODL + * Counter 1: link 0/ODL0, CRC error detected by DLx + * Counter 2: link 1/ODL1, CRC error detected by ODL + * Counter 3: link 1/ODL1, CRC error detected by DLx + */ + if ((dev->brick_index == 2) || (dev->brick_index == 5)) + link = 0; + else + link = 1; + + addr = OB_DLL_PERF_MONITOR_CONFIG(dev->brick_index); + xscom_read(dev->npu->chip_id, addr, ®); + if (link == 0) { + reg = SETFIELD(OB_DLL_PERF_MONITOR_CONFIG_ENABLE, reg, + OB_DLL_PERF_MONITOR_CONFIG_LINK0); + reg = SETFIELD(OB_DLL_PERF_MONITOR_CONFIG_ENABLE >> 2, reg, + OB_DLL_PERF_MONITOR_CONFIG_LINK0); + } else { + reg = SETFIELD(OB_DLL_PERF_MONITOR_CONFIG_ENABLE >> 4, reg, + OB_DLL_PERF_MONITOR_CONFIG_LINK1); + reg = SETFIELD(OB_DLL_PERF_MONITOR_CONFIG_ENABLE >> 6, reg, + OB_DLL_PERF_MONITOR_CONFIG_LINK1); + } + reg = SETFIELD(OB_DLL_PERF_MONITOR_CONFIG_SIZE, reg, + OB_DLL_PERF_MONITOR_CONFIG_SIZE16); + xscom_write(dev->npu->chip_id, + OB_DLL_PERF_MONITOR_CONFIG(dev->brick_index), reg); + OCAPIDBG(dev, "perf counter config %llx = %llx\n", addr, reg); + + addr = OB_DLL_PERF_MONITOR_SELECT(dev->brick_index); + xscom_read(dev->npu->chip_id, addr, ®); + reg = SETFIELD(OB_DLL_PERF_MONITOR_SELECT_COUNTER >> (link * 16), + reg, OB_DLL_PERF_MONITOR_SELECT_CRC_ODL); + reg = SETFIELD(OB_DLL_PERF_MONITOR_SELECT_COUNTER >> ((link * 16) + 8), + reg, OB_DLL_PERF_MONITOR_SELECT_CRC_DLX); + xscom_write(dev->npu->chip_id, addr, reg); + OCAPIDBG(dev, "perf counter select %llx = %llx\n", addr, reg); +} + +static void check_perf_counters(struct npu2_dev *dev) +{ + uint64_t addr, reg, link0, link1; + + addr = OB_DLL_PERF_COUNTER0(dev->brick_index); + xscom_read(dev->npu->chip_id, addr, ®); + link0 = GETFIELD(PPC_BITMASK(0, 31), reg); + link1 = GETFIELD(PPC_BITMASK(32, 63), reg); + if (link0 || link1) + OCAPIERR(dev, "CRC error count link0=%08llx link1=%08llx\n", + link0, link1); +} + static void set_init_pattern(uint32_t gcid, struct npu2_dev *dev) { uint64_t reg, config_xscom; @@ -1048,6 +1108,7 @@ static int64_t npu2_opencapi_poll_link(struct pci_slot *slot) case OCAPI_SLOT_LINK_TRAINED: otl_enabletx(chip_id, dev->npu->xscom_base, dev); pci_slot_set_state(slot, OCAPI_SLOT_NORMAL); + check_perf_counters(dev); dev->phb_ocapi.scan_map = 1; return OPAL_SUCCESS; @@ -1569,6 +1630,7 @@ static void setup_device(struct npu2_dev *dev) setup_afu_mmio_bars(dev->npu->chip_id, dev->npu->xscom_base, dev); /* Procedure 13.1.3.9 - AFU Config BARs */ setup_afu_config_bars(dev->npu->chip_id, dev->npu->xscom_base, dev); + setup_perf_counters(dev); set_fence_control(dev->npu->chip_id, dev->npu->xscom_base, dev->brick_index, 0b00); diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 5190aeb7..ca311097 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -725,6 +725,23 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define PU_IOE_PB_FP_CFG_FP1_FMR_DISABLE PPC_BIT(52) #define PU_IOE_PB_FP_CFG_FP1_PRS_DISABLE PPC_BIT(57) +#define OB_DLL_PERF_MONITOR_CONFIG(brick_index) \ + (0x901081C + ((brick_index - 2) >> 1) * 0x3000000) +#define OB_DLL_PERF_MONITOR_CONFIG_ENABLE PPC_BITMASK(0, 1) +#define OB_DLL_PERF_MONITOR_CONFIG_LINK0 0b10 +#define OB_DLL_PERF_MONITOR_CONFIG_LINK1 0b01 +#define OB_DLL_PERF_MONITOR_CONFIG_SIZE PPC_BITMASK(16, 23) +#define OB_DLL_PERF_MONITOR_CONFIG_SIZE16 0xFF +#define OB_DLL_PERF_MONITOR_SELECT(brick_index) \ + (0x901081D + ((brick_index - 2) >> 1) * 0x3000000) +#define OB_DLL_PERF_MONITOR_SELECT_COUNTER PPC_BITMASK(0, 7) +#define OB_DLL_PERF_MONITOR_SELECT_CRC_ODL 0x44 +#define OB_DLL_PERF_MONITOR_SELECT_CRC_DLX 0x45 +#define OB_DLL_PERF_COUNTER0(brick_index) \ + (0x901081E + ((brick_index - 2) >> 1) * 0x3000000) +#define OB_DLL_PERF_COUNTER0_VAL PPC_BITMASK(0, 31) + + #define OB_ODL_OFFSET(brick_index) \ ((((brick_index - 2) >> 1) * 0x3000000) + ((brick_index == 3 || brick_index == 4) ? 1 : 0)) From patchwork Tue Mar 12 20:35:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1055751 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Jmw60RZkz9s3q for ; Wed, 13 Mar 2019 07:36:22 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44Jmw53CthzDqDt for ; Wed, 13 Mar 2019 07:36:21 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Jmv33bj6zDq77 for ; Wed, 13 Mar 2019 07:35:27 +1100 (AEDT) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2CKYNeJ051040 for ; Tue, 12 Mar 2019 16:35:25 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2r6kep9j79-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Mar 2019 16:35:25 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Mar 2019 20:35:21 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2CKZKw460227610 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Mar 2019 20:35:20 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E878742042; Tue, 12 Mar 2019 20:35:19 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A57F942041; Tue, 12 Mar 2019 20:35:19 +0000 (GMT) Received: from borneo.home (unknown [9.145.16.6]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Mar 2019 20:35:19 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org, andrew.donnellan@au1.ibm.com Date: Tue, 12 Mar 2019 21:35:11 +0100 X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190312203515.18520-1-fbarrat@linux.ibm.com> References: <20190312203515.18520-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19031220-4275-0000-0000-0000031A2D69 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19031220-4276-0000-0000-000038289963 Message-Id: <20190312203515.18520-4-fbarrat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-12_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=927 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903120139 Subject: [Skiboot] [PATCH v2 3/7] npu2-opencapi: Rename functions used to reset an adapter X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clombard@linux.ibm.com, arbab@linux.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This is really to avoid confusion with a later patch and clarify whether we're resetting the ODL or the adapter. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan Reviewed-by: Christophe Lombard --- v2: no change hw/npu2-opencapi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index 6d642cde..9fe5efd6 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -814,7 +814,7 @@ static void otl_enabletx(uint32_t gcid, uint32_t scom_base, /* TODO: Abort if credits are zero */ } -static void assert_reset(struct npu2_dev *dev) +static void assert_adapter_reset(struct npu2_dev *dev) { uint8_t pin, data; int rc; @@ -869,7 +869,7 @@ err: OCAPIERR(dev, "Error writing I2C reset signal: %d\n", rc); } -static void deassert_reset(struct npu2_dev *dev) +static void deassert_adapter_reset(struct npu2_dev *dev) { uint8_t data; int rc; @@ -1164,14 +1164,14 @@ static int64_t npu2_opencapi_freset(struct pci_slot *slot) /* fall-through */ case OCAPI_SLOT_FRESET_INIT: reset_odl(chip_id, dev); - assert_reset(dev); + assert_adapter_reset(dev); pci_slot_set_state(slot, OCAPI_SLOT_FRESET_ASSERT_DELAY); /* assert for 5ms */ return pci_slot_set_sm_timeout(slot, msecs_to_tb(5)); case OCAPI_SLOT_FRESET_ASSERT_DELAY: - deassert_reset(dev); + deassert_adapter_reset(dev); pci_slot_set_state(slot, OCAPI_SLOT_FRESET_DEASSERT_DELAY); /* give another 5ms to device to be ready */ From patchwork Tue Mar 12 20:35:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1055753 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Jmwh4Kcfz9s3q for ; Wed, 13 Mar 2019 07:36:52 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44Jmwh34B8zDqDX for ; Wed, 13 Mar 2019 07:36:52 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Jmv45gPSzDqCH for ; Wed, 13 Mar 2019 07:35:28 +1100 (AEDT) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2CKYNKp113740 for ; Tue, 12 Mar 2019 16:35:27 -0400 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0a-001b2d01.pphosted.com with ESMTP id 2r6jnac75s-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Mar 2019 16:35:26 -0400 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Mar 2019 20:35:22 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2CKZLSR37486624 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Mar 2019 20:35:21 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4E0AA4203F; Tue, 12 Mar 2019 20:35:21 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0A11642041; Tue, 12 Mar 2019 20:35:21 +0000 (GMT) Received: from borneo.home (unknown [9.145.16.6]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Mar 2019 20:35:20 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org, andrew.donnellan@au1.ibm.com Date: Tue, 12 Mar 2019 21:35:12 +0100 X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190312203515.18520-1-fbarrat@linux.ibm.com> References: <20190312203515.18520-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19031220-0028-0000-0000-0000035339BE X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19031220-0029-0000-0000-00002411BEDF Message-Id: <20190312203515.18520-5-fbarrat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-12_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=765 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903120139 Subject: [Skiboot] [PATCH v2 4/7] npu2-opencapi: Keep ODL and adapter in reset at the same time X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clombard@linux.ibm.com, arbab@linux.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Split the function to assert and deassert the reset signal on the ODL, so that we can keep the ODL in reset while we reset the adapter, therefore having a window where both sides are in reset. It is actually not required with our current DLx at boot time, but I need to split the ODL reset function for the following patch and it will become useful/required later when we introduce resetting an opencapi link from the OS. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan Reviewed-by: Christophe Lombard --- v2: add comment hw/npu2-opencapi.c | 68 +++++++++++++++++++++++++++++----------------- 1 file changed, 43 insertions(+), 25 deletions(-) diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index 9fe5efd6..87e64492 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -68,7 +68,8 @@ #define OCAPI_SLOT_FRESET_INIT (OCAPI_SLOT_FRESET + 2) #define OCAPI_SLOT_FRESET_ASSERT_DELAY (OCAPI_SLOT_FRESET + 3) #define OCAPI_SLOT_FRESET_DEASSERT_DELAY (OCAPI_SLOT_FRESET + 4) -#define OCAPI_SLOT_FRESET_INIT_DELAY (OCAPI_SLOT_FRESET + 5) +#define OCAPI_SLOT_FRESET_DEASSERT_DELAY2 (OCAPI_SLOT_FRESET + 5) +#define OCAPI_SLOT_FRESET_INIT_DELAY (OCAPI_SLOT_FRESET + 6) #define OCAPI_LINK_TRAINING_RETRIES 2 #define OCAPI_LINK_TRAINING_TIMEOUT 3000 /* ms */ @@ -261,6 +262,33 @@ static void set_transport_mux_controls(uint32_t gcid, uint32_t scom_base, xscom_write(gcid, PU_IOE_PB_MISC_CFG, reg); } +static void assert_odl_reset(uint32_t gcid, int index) +{ + uint64_t reg, config_xscom; + + config_xscom = OB_ODL_CONFIG(index); + /* Reset ODL */ + reg = OB_ODL_CONFIG_RESET; + reg = SETFIELD(OB_ODL_CONFIG_VERSION, reg, 0b000001); + reg = SETFIELD(OB_ODL_CONFIG_TRAIN_MODE, reg, 0b0110); + reg = SETFIELD(OB_ODL_CONFIG_SUPPORTED_MODES, reg, 0b0010); + reg |= OB_ODL_CONFIG_X4_BACKOFF_ENABLE; + reg = SETFIELD(OB_ODL_CONFIG_PHY_CNTR_LIMIT, reg, 0b1111); + reg |= OB_ODL_CONFIG_DEBUG_ENABLE; + reg = SETFIELD(OB_ODL_CONFIG_FWD_PROGRESS_TIMER, reg, 0b0110); + xscom_write(gcid, config_xscom, reg); +} + +static void deassert_odl_reset(uint32_t gcid, int index) +{ + uint64_t reg, config_xscom; + + config_xscom = OB_ODL_CONFIG(index); + xscom_read(gcid, config_xscom, ®); + reg &= ~OB_ODL_CONFIG_RESET; + xscom_write(gcid, config_xscom, reg); +} + static void enable_odl_phy_mux(uint32_t gcid, int index) { uint64_t reg; @@ -889,26 +917,6 @@ static void deassert_adapter_reset(struct npu2_dev *dev) } } -static void reset_odl(uint32_t gcid, struct npu2_dev *dev) -{ - uint64_t reg, config_xscom; - - config_xscom = OB_ODL_CONFIG(dev->brick_index); - /* Reset ODL */ - reg = OB_ODL_CONFIG_RESET; - reg = SETFIELD(OB_ODL_CONFIG_VERSION, reg, 0b000001); - reg = SETFIELD(OB_ODL_CONFIG_TRAIN_MODE, reg, 0b0110); - reg = SETFIELD(OB_ODL_CONFIG_SUPPORTED_MODES, reg, 0b0010); - reg |= OB_ODL_CONFIG_X4_BACKOFF_ENABLE; - reg = SETFIELD(OB_ODL_CONFIG_PHY_CNTR_LIMIT, reg, 0b1111); - reg |= OB_ODL_CONFIG_DEBUG_ENABLE; - reg = SETFIELD(OB_ODL_CONFIG_FWD_PROGRESS_TIMER, reg, 0b0110); - xscom_write(gcid, config_xscom, reg); - - reg &= ~OB_ODL_CONFIG_RESET; - xscom_write(gcid, config_xscom, reg); -} - static void setup_perf_counters(struct npu2_dev *dev) { uint64_t addr, reg, link; @@ -1163,7 +1171,7 @@ static int64_t npu2_opencapi_freset(struct pci_slot *slot) npu2_opencapi_phy_setup(dev); /* fall-through */ case OCAPI_SLOT_FRESET_INIT: - reset_odl(chip_id, dev); + assert_odl_reset(chip_id, dev->brick_index); assert_adapter_reset(dev); pci_slot_set_state(slot, OCAPI_SLOT_FRESET_ASSERT_DELAY); @@ -1171,13 +1179,23 @@ static int64_t npu2_opencapi_freset(struct pci_slot *slot) return pci_slot_set_sm_timeout(slot, msecs_to_tb(5)); case OCAPI_SLOT_FRESET_ASSERT_DELAY: - deassert_adapter_reset(dev); + deassert_odl_reset(chip_id, dev->brick_index); pci_slot_set_state(slot, OCAPI_SLOT_FRESET_DEASSERT_DELAY); - /* give another 5ms to device to be ready */ - return pci_slot_set_sm_timeout(slot, msecs_to_tb(5)); + /* + * Minimal delay before taking adapter out of + * reset. Could be useless, but doesn't hurt + */ + return pci_slot_set_sm_timeout(slot, msecs_to_tb(1)); case OCAPI_SLOT_FRESET_DEASSERT_DELAY: + deassert_adapter_reset(dev); + pci_slot_set_state(slot, + OCAPI_SLOT_FRESET_DEASSERT_DELAY2); + /* give 5ms to device to be ready */ + return pci_slot_set_sm_timeout(slot, msecs_to_tb(5)); + + case OCAPI_SLOT_FRESET_DEASSERT_DELAY2: if (dev->train_fenced) { OCAPIDBG(dev, "Unfencing OTL after reset\n"); npu2_write(dev->npu, NPU2_MISC_FENCE_STATE, From patchwork Tue Mar 12 20:35:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1055754 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Jmwy4xvjz9s3q for ; Wed, 13 Mar 2019 07:37:06 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44Jmwy1kkvzDqH4 for ; Wed, 13 Mar 2019 07:37:05 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Jmv63KjjzDq77 for ; Wed, 13 Mar 2019 07:35:30 +1100 (AEDT) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2CKYt63115002 for ; Tue, 12 Mar 2019 16:35:28 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0b-001b2d01.pphosted.com with ESMTP id 2r6hdk0f0h-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Mar 2019 16:35:27 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Mar 2019 20:35:24 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2CKZML59502962 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Mar 2019 20:35:22 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AB2A442047; Tue, 12 Mar 2019 20:35:22 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5FFE842041; Tue, 12 Mar 2019 20:35:22 +0000 (GMT) Received: from borneo.home (unknown [9.145.16.6]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Mar 2019 20:35:22 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org, andrew.donnellan@au1.ibm.com Date: Tue, 12 Mar 2019 21:35:13 +0100 X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190312203515.18520-1-fbarrat@linux.ibm.com> References: <20190312203515.18520-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19031220-4275-0000-0000-0000031A2D6B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19031220-4276-0000-0000-000038289966 Message-Id: <20190312203515.18520-6-fbarrat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-12_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=984 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903120139 Subject: [Skiboot] [PATCH v2 5/7] npu2-opencapi: ODL should be in reset when enabled X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clombard@linux.ibm.com, arbab@linux.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We haven't hit any problem so far, but from the ODL designer, the ODL should be in reset when it is enabled. The ODL remains in reset until we start a fundamental reset to initiate link training. We still assert and deassert the ODL reset signal as part of the normal procedure just before training the link. Asserting is therefore useless at boot, since the ODL is already in reset, but we keep it as it's only a scom write and it's needed when we reset/retrain from the OS. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan Reviewed-by: Christophe Lombard --- v2: update commit message hw/npu2-opencapi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index 87e64492..223888e6 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -308,6 +308,12 @@ static void enable_odl_phy_mux(uint32_t gcid, int index) assert(false); } + /* + * ODL must be in reset when enabling. + * It stays in reset until the link is trained + */ + assert_odl_reset(gcid, index); + /* PowerBus OLL PHY Training Config Register */ xscom_read(gcid, phy_config_scom, ®); From patchwork Tue Mar 12 20:35:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1055755 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44JmxG331Mz9s3q for ; Wed, 13 Mar 2019 07:37:22 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44JmxG1lMJzDqDN for ; Wed, 13 Mar 2019 07:37:22 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Jmv73R3vzDq77 for ; Wed, 13 Mar 2019 07:35:31 +1100 (AEDT) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2CKYOj2054593 for ; Tue, 12 Mar 2019 16:35:29 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2r6h93s8yv-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Mar 2019 16:35:29 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Mar 2019 20:35:25 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2CKZOue50593804 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Mar 2019 20:35:24 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 15D9942047; Tue, 12 Mar 2019 20:35:24 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BD73742041; Tue, 12 Mar 2019 20:35:23 +0000 (GMT) Received: from borneo.home (unknown [9.145.16.6]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Mar 2019 20:35:23 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org, andrew.donnellan@au1.ibm.com Date: Tue, 12 Mar 2019 21:35:14 +0100 X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190312203515.18520-1-fbarrat@linux.ibm.com> References: <20190312203515.18520-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19031220-4275-0000-0000-0000031A2D6C X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19031220-4276-0000-0000-000038289967 Message-Id: <20190312203515.18520-7-fbarrat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-12_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=857 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903120139 Subject: [Skiboot] [PATCH v2 6/7] npu2-opencapi: Extend delay after releasing reset on adapter X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clombard@linux.ibm.com, arbab@linux.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Give more time to the FPGA to process the reset signal. The previous delay, 5ms, is too short for newer adapters with bigger FPGAs. Extend it to 250ms. Ultimately, that delay will likely end up being added to the opencapi specification, but we are not there yet. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan --- v2: no change hw/npu2-opencapi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index 223888e6..e4e3ae63 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -1198,8 +1198,8 @@ static int64_t npu2_opencapi_freset(struct pci_slot *slot) deassert_adapter_reset(dev); pci_slot_set_state(slot, OCAPI_SLOT_FRESET_DEASSERT_DELAY2); - /* give 5ms to device to be ready */ - return pci_slot_set_sm_timeout(slot, msecs_to_tb(5)); + /* give 250ms to device to be ready */ + return pci_slot_set_sm_timeout(slot, msecs_to_tb(250)); case OCAPI_SLOT_FRESET_DEASSERT_DELAY2: if (dev->train_fenced) { From patchwork Tue Mar 12 20:35:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1055756 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44JmxX3YPjz9s3q for ; Wed, 13 Mar 2019 07:37:36 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44JmxX2SmZzDqDd for ; Wed, 13 Mar 2019 07:37:36 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44Jmv94xfpzDq77 for ; Wed, 13 Mar 2019 07:35:33 +1100 (AEDT) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2CKYOkn143687 for ; Tue, 12 Mar 2019 16:35:31 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0b-001b2d01.pphosted.com with ESMTP id 2r6jfh4wkf-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 12 Mar 2019 16:35:31 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 12 Mar 2019 20:35:27 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2CKZPWp61538512 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Mar 2019 20:35:25 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6C51E42042; Tue, 12 Mar 2019 20:35:25 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 296E942041; Tue, 12 Mar 2019 20:35:25 +0000 (GMT) Received: from borneo.home (unknown [9.145.16.6]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 12 Mar 2019 20:35:25 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org, andrew.donnellan@au1.ibm.com Date: Tue, 12 Mar 2019 21:35:15 +0100 X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190312203515.18520-1-fbarrat@linux.ibm.com> References: <20190312203515.18520-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19031220-0008-0000-0000-000002CBD429 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19031220-0009-0000-0000-00002237F583 Message-Id: <20190312203515.18520-8-fbarrat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-12_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=708 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903120139 Subject: [Skiboot] [PATCH v2 7/7] npu2-opencapi: Fix adapter reset when using 2 adapters X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clombard@linux.ibm.com, arbab@linux.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" If two opencapi adapters are on the same obus, we may try to train the two links in parallel at boot time, when all the PCI links are being trained. Both links use the same i2c controller to handle the reset signal, so some care is needed to make sure resetting one doesn't interfere with the reset of the other. We need to keep track of the current state of the i2c controller (and use locking). This went mostly unnoticed as you need to have 2 opencapi cards on the same socket and links tended to train anyway because of the retries. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan Reviewed-by: Christophe Lombard --- v2: no change hw/npu2-common.c | 3 +++ hw/npu2-opencapi.c | 34 +++++++++++++++++++++++++++------- include/npu2.h | 4 ++++ 3 files changed, 34 insertions(+), 7 deletions(-) diff --git a/hw/npu2-common.c b/hw/npu2-common.c index ec69953f..3d0b6366 100644 --- a/hw/npu2-common.c +++ b/hw/npu2-common.c @@ -182,6 +182,9 @@ static struct npu2 *setup_npu(struct dt_node *dn) npu->xscom_base = dt_get_address(dn, 0, NULL); npu->phb_index = dt_prop_get_u32(dn, "ibm,phb-index"); + init_lock(&npu->i2c_lock); + npu->i2c_pin_mode = ~0; // input mode by default + npu->i2c_pin_wr_state = ~0; // reset is active low if (platform.ocapi) { /* Find I2C port for handling device presence/reset */ snprintf(port_name, sizeof(port_name), "p8_%08x_e%dp%d", diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c index e4e3ae63..b2740f38 100644 --- a/hw/npu2-opencapi.c +++ b/hw/npu2-opencapi.c @@ -848,10 +848,9 @@ static void otl_enabletx(uint32_t gcid, uint32_t scom_base, /* TODO: Abort if credits are zero */ } -static void assert_adapter_reset(struct npu2_dev *dev) +static uint8_t get_reset_pin(struct npu2_dev *dev) { - uint8_t pin, data; - int rc; + uint8_t pin; switch (dev->brick_index) { case 2: @@ -869,14 +868,25 @@ static void assert_adapter_reset(struct npu2_dev *dev) default: assert(false); } + return pin; +} + +static void assert_adapter_reset(struct npu2_dev *dev) +{ + uint8_t pin, data; + int rc; + pin = get_reset_pin(dev); /* * set the i2c reset pin in output mode * * On the 9554 device, register 3 is the configuration * register and a pin is in output mode if its value is 0 */ - data = ~pin; + lock(&dev->npu->i2c_lock); + dev->npu->i2c_pin_mode &= ~pin; + data = dev->npu->i2c_pin_mode; + rc = i2c_request_send(dev->npu->i2c_port_id_ocapi, platform.ocapi->i2c_reset_addr, SMBUS_WRITE, 0x3, 1, @@ -885,16 +895,20 @@ static void assert_adapter_reset(struct npu2_dev *dev) goto err; /* register 1 controls the signal, reset is active low */ - data = ~pin; + dev->npu->i2c_pin_wr_state &= ~pin; + data = dev->npu->i2c_pin_wr_state; + rc = i2c_request_send(dev->npu->i2c_port_id_ocapi, platform.ocapi->i2c_reset_addr, SMBUS_WRITE, 0x1, 1, &data, sizeof(data), 120); if (rc) goto err; + unlock(&dev->npu->i2c_lock); return; err: + unlock(&dev->npu->i2c_lock); /** * @fwts-label OCAPIDeviceResetFailed * @fwts-advice There was an error attempting to send @@ -905,14 +919,20 @@ err: static void deassert_adapter_reset(struct npu2_dev *dev) { - uint8_t data; + uint8_t pin, data; int rc; - data = 0xFF; + pin = get_reset_pin(dev); + + lock(&dev->npu->i2c_lock); + dev->npu->i2c_pin_wr_state |= pin; + data = dev->npu->i2c_pin_wr_state; + rc = i2c_request_send(dev->npu->i2c_port_id_ocapi, platform.ocapi->i2c_reset_addr, SMBUS_WRITE, 0x1, 1, &data, sizeof(data), 120); + unlock(&dev->npu->i2c_lock); if (rc) { /** * @fwts-label OCAPIDeviceResetFailed diff --git a/include/npu2.h b/include/npu2.h index cfa3b1f8..b62d1748 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -173,7 +173,11 @@ struct npu2 { struct phb phb_nvlink; uint32_t phb_index; + /* OCAPI */ uint64_t i2c_port_id_ocapi; + struct lock i2c_lock; + uint8_t i2c_pin_mode; + uint8_t i2c_pin_wr_state; }; static inline struct npu2 *phb_to_npu2_nvlink(struct phb *phb)