From patchwork Tue Mar 12 08:31:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1055135 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44JSrg6ryXz9s47 for ; Tue, 12 Mar 2019 19:32:19 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7EF34C21EBD; Tue, 12 Mar 2019 08:31:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BE8A9C21F34; Tue, 12 Mar 2019 08:31:33 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 07AA9C21E52; Tue, 12 Mar 2019 08:31:29 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id 8A92BC21F01 for ; Tue, 12 Mar 2019 08:31:24 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Mar 2019 01:31:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,470,1544515200"; d="scan'208";a="130895411" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.82]) by fmsmga008.fm.intel.com with SMTP; 12 Mar 2019 01:31:19 -0700 Received: by ubuntu (sSMTP sendmail emulation); Tue, 12 Mar 2019 16:31:18 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Tue, 12 Mar 2019 16:31:05 +0800 Message-Id: <1552379474-12867-2-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> Cc: Chin Liang See , Ley Foon Tan , Dalon Westergreen Subject: [U-Boot] [PATCH 01/10] ddr: altera: stratix10: Move SDRAM size check to SDRAM driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move SDRAM size check to SDRAM driver. sdram_calculate_size() is called in SDRAM initialization already, avoid calling twice in size check function. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/spl_s10.c | 11 ----------- drivers/ddr/altera/sdram_s10.c | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index a3db20a819..a141ffe82a 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -181,17 +181,6 @@ void board_init_f(ulong dummy) hang(); } - gd->ram_size = sdram_calculate_size(); - printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20)); - - /* Sanity check ensure correct SDRAM size specified */ - debug("DDR: Running SDRAM size sanity check\n"); - if (get_ram_size(0, gd->ram_size) != gd->ram_size) { - puts("DDR: SDRAM size check failed!\n"); - hang(); - } - debug("DDR: SDRAM size check passed!\n"); - mbox_init(); #ifdef CONFIG_CADENCE_QSPI diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index a48567c109..8895813440 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -134,6 +134,17 @@ static int poll_hmc_clock_status(void) SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); } +static void sdram_size_check(void) +{ + /* Sanity check ensure correct SDRAM size specified */ + debug("DDR: Running SDRAM size sanity check\n"); + if (get_ram_size(0, gd->ram_size) != gd->ram_size) { + puts("DDR: SDRAM size check failed!\n"); + hang(); + } + debug("DDR: SDRAM size check passed!\n"); +} + /** * sdram_mmr_init_full() - Function to initialize SDRAM MMR * @@ -339,6 +350,8 @@ int sdram_mmr_init_full(unsigned int unused) else gd->ram_size = size; + printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20)); + /* Enable or disable the SDRAM ECC */ if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) { setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, @@ -361,6 +374,8 @@ int sdram_mmr_init_full(unsigned int unused) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); } + sdram_size_check(); + debug("DDR: HMC init success\n"); return 0; } From patchwork Tue Mar 12 08:31:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1055137 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44JSsr1vq6z9s47 for ; Tue, 12 Mar 2019 19:33:20 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E0736C21F29; Tue, 12 Mar 2019 08:31:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5DA2CC21F0C; Tue, 12 Mar 2019 08:31:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E9CADC21F0B; Tue, 12 Mar 2019 08:31:32 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lists.denx.de (Postfix) with ESMTPS id 867C4C21F1D for ; Tue, 12 Mar 2019 08:31:27 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Mar 2019 01:31:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,470,1544515200"; d="scan'208";a="327786445" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.82]) by fmsmga005.fm.intel.com with SMTP; 12 Mar 2019 01:31:23 -0700 Received: by ubuntu (sSMTP sendmail emulation); Tue, 12 Mar 2019 16:31:22 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Tue, 12 Mar 2019 16:31:06 +0800 Message-Id: <1552379474-12867-3-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> Cc: Chin Liang See , Ley Foon Tan , Dalon Westergreen Subject: [U-Boot] [PATCH 02/10] arm: socfpga: Add sdram_s10.h to sdram.h X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Includes Stratix10 SDRAM header file. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/sdram.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index 79cb9e6064..2c1f55a87a 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -11,6 +11,8 @@ #include #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#include #endif #endif From patchwork Tue Mar 12 08:31:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1055136 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44JSsn105bz9s47 for ; Tue, 12 Mar 2019 19:33:17 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BF026C21F13; Tue, 12 Mar 2019 08:32:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D4338C21F22; Tue, 12 Mar 2019 08:31:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7DBAAC21ED6; Tue, 12 Mar 2019 08:31:34 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id 2A501C21F27 for ; Tue, 12 Mar 2019 08:31:29 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Mar 2019 01:31:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,470,1544515200"; d="scan'208";a="207953683" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.82]) by orsmga001.jf.intel.com with SMTP; 12 Mar 2019 01:31:26 -0700 Received: by ubuntu (sSMTP sendmail emulation); Tue, 12 Mar 2019 16:31:25 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Tue, 12 Mar 2019 16:31:07 +0800 Message-Id: <1552379474-12867-4-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> Cc: Chin Liang See , Ley Foon Tan , Dalon Westergreen Subject: [U-Boot] [PATCH 03/10] ddr: altera: s10: Add multiple memory banks support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Setup bank start address and size based on total SDRAM memory size calculated from hardware. Update sdram_size_check() to support multiple banks. Stratix10 supports up to 2 memory banks. Bank 0: Address 0, size 2GB Bank 1: Address 0x100000000, size 124GB Signed-off-by: Dalon Westergreen Signed-off-by: Ley Foon Tan --- .../arm/mach-socfpga/include/mach/sdram_s10.h | 1 + drivers/ddr/altera/sdram_s10.c | 93 ++++++++++++++++++- 2 files changed, 91 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h index ca68594445..89e355010d 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h @@ -10,6 +10,7 @@ phys_size_t sdram_calculate_size(void); int sdram_mmr_init_full(unsigned int sdr_phy_reg); int sdram_calibration_full(void); +void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t bank_size[]); #define DDR_TWR 15 #define DDR_READ_LATENCY_DELAY 40 diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 8895813440..ae4e5ea2fd 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -13,6 +13,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -134,17 +135,100 @@ static int poll_hmc_clock_status(void) SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); } -static void sdram_size_check(void) +static void sdram_size_check(phys_addr_t bank_start[], phys_size_t bank_size[]) { + phys_size_t total_ram_check = 0; + phys_size_t ram_check = 0; + int bank; + /* Sanity check ensure correct SDRAM size specified */ debug("DDR: Running SDRAM size sanity check\n"); - if (get_ram_size(0, gd->ram_size) != gd->ram_size) { + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + while (ram_check < bank_size[bank]) { + ram_check += get_ram_size((void *)(bank_start[bank] + + ram_check), + (phys_size_t)SZ_1G); + } + total_ram_check += ram_check; + ram_check = 0; + } + + if (total_ram_check != gd->ram_size) { puts("DDR: SDRAM size check failed!\n"); hang(); } + debug("DDR: SDRAM size check passed!\n"); } +void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t bank_size[]) +{ + phys_size_t ram_alias; + + bank_addr[0] = CONFIG_SYS_SDRAM_BASE; + bank_size[0] = min((phys_size_t)SZ_2G, (phys_size_t)gd->ram_size); + + if (CONFIG_NR_DRAM_BANKS > 1) { + if (gd->ram_size > ((phys_size_t)SZ_2G * (phys_size_t)32)) { + /* With memories > 64GB it is not possible to + * access the entire memory. You cannot avoid + * the 2GB IO hole from 2GB to 4GB in the HPS + * memory space. The dram banks must be configured + * as : + * dram[0].start = 0x0 + * dram[0].size = SZ_2GB + * dram[1].start = SZ_2GB << 1 (or 4GB) + * dram[1].size = gd->ram_size - SZ_2G + */ + bank_addr[1] = (phys_addr_t)SZ_2G + + (phys_addr_t)SZ_2G; + bank_size[1] = gd->ram_size - SZ_2G; + + /* reduce ram size as useable space is smaller. + * We cannot avoid the IO hole. + */ + gd->ram_size -= SZ_2G; + + } else if (gd->ram_size > SZ_2G) { + /* We can use that the DRAM address space + * is repeatedly aliased in the overall + * 128GB of address space as the SDRAM NOC + * ignores unused upper address bits. + * + * This means, a 4GB DDR is replicated every + * 4GB in the address, and a 16GB DDR every + * 16GB. + * + * So, we can access the entire memory, for + * the 4GB case: + * dram[0].start = 0x0 + * dram[0].size = SZ_2GB + * dram[1].start = SZ_2GB << 1 + SZ_2GB (or 6GB) + * dram[1].size = gd->ram_size - SZ_2G + * + * more interestingly, the 3GB case would be the same. + */ + + /* Now we need to find the appropriate alias + * location. + */ + ram_alias = SZ_2G; + while (ram_alias < gd->ram_size) + ram_alias = ram_alias << 1; + + bank_addr[1] = ram_alias + SZ_2G; + bank_size[1] = gd->ram_size - SZ_2G; + } else { + /* Here the map is simple as all memory fits in the + * lower 2GB window. + */ + bank_addr[1] = 0; + bank_size[1] = 0; + } + } +} + /** * sdram_mmr_init_full() - Function to initialize SDRAM MMR * @@ -155,6 +239,8 @@ int sdram_mmr_init_full(unsigned int unused) u32 update_value, io48_value, ddrioctl; u32 i; int ret; + phys_addr_t bank_start[CONFIG_NR_DRAM_BANKS]; + phys_size_t bank_size[CONFIG_NR_DRAM_BANKS]; /* Enable access to DDR from CPU master */ clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG), @@ -351,6 +437,7 @@ int sdram_mmr_init_full(unsigned int unused) gd->ram_size = size; printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20)); + setup_memory_banks(bank_start, bank_size); /* Enable or disable the SDRAM ECC */ if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) { @@ -374,7 +461,7 @@ int sdram_mmr_init_full(unsigned int unused) DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); } - sdram_size_check(); + sdram_size_check(bank_start, bank_size); debug("DDR: HMC init success\n"); return 0; From patchwork Tue Mar 12 08:31:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1055138 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44JSv52QMtz9s47 for ; Tue, 12 Mar 2019 19:34:25 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 04CB7C21F2B; Tue, 12 Mar 2019 08:32:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 66A1FC21F18; Tue, 12 Mar 2019 08:31:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 81D86C21F1C; Tue, 12 Mar 2019 08:31:39 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lists.denx.de (Postfix) with ESMTPS id EC89BC21F32 for ; Tue, 12 Mar 2019 08:31:34 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Mar 2019 01:31:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,470,1544515200"; d="scan'208";a="327786469" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.82]) by fmsmga005.fm.intel.com with SMTP; 12 Mar 2019 01:31:30 -0700 Received: by ubuntu (sSMTP sendmail emulation); Tue, 12 Mar 2019 16:31:29 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Tue, 12 Mar 2019 16:31:08 +0800 Message-Id: <1552379474-12867-5-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> Cc: Chin Liang See , Ley Foon Tan , Dalon Westergreen Subject: [U-Boot] [PATCH 04/10] arm: socfpga: Update dram_init_banksize() for Stratix10 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Setup bi_dram struct based on returned from setup_memory_banks(). Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/board.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 7c8c05cc31..a0e9917e47 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -48,8 +49,21 @@ int board_init(void) int dram_init_banksize(void) { - fdtdec_setup_memory_banksize(); +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) && defined(CONFIG_ALTERA_SDRAM) + phys_addr_t bank_start[CONFIG_NR_DRAM_BANKS]; + phys_size_t bank_size[CONFIG_NR_DRAM_BANKS]; + int bank; + + gd->ram_size = sdram_calculate_size(); + setup_memory_banks(bank_start, bank_size); + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + gd->bd->bi_dram[bank].start = bank_start[bank]; + gd->bd->bi_dram[bank].size = bank_size[bank]; + } +#else + fdtdec_setup_memory_banksize(); +#endif return 0; } From patchwork Tue Mar 12 08:31:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1055139 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44JSvR3sqGz9s47 for ; Tue, 12 Mar 2019 19:34:43 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E4010C21F37; Tue, 12 Mar 2019 08:32:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0E1D1C21F0C; Tue, 12 Mar 2019 08:32:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 95A7CC21EFF; Tue, 12 Mar 2019 08:31:43 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lists.denx.de (Postfix) with ESMTPS id 78BCEC21F2F for ; Tue, 12 Mar 2019 08:31:39 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Mar 2019 01:31:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,470,1544515200"; d="scan'208";a="133342823" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.82]) by orsmga003.jf.intel.com with SMTP; 12 Mar 2019 01:31:34 -0700 Received: by ubuntu (sSMTP sendmail emulation); Tue, 12 Mar 2019 16:31:33 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Tue, 12 Mar 2019 16:31:09 +0800 Message-Id: <1552379474-12867-6-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> Cc: Chin Liang See , Ley Foon Tan , Dalon Westergreen Subject: [U-Boot] [PATCH 05/10] board: altera: Stratix10: Add board_get_usable_ram_top() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add board_get_usable_ram_top() function. Limit maximum usable ram top to 2GB. Signed-off-by: Dalon Westergreen Signed-off-by: Ley Foon Tan --- board/altera/stratix10-socdk/socfpga.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/altera/stratix10-socdk/socfpga.c b/board/altera/stratix10-socdk/socfpga.c index 043fc543f1..99c10d313c 100644 --- a/board/altera/stratix10-socdk/socfpga.c +++ b/board/altera/stratix10-socdk/socfpga.c @@ -5,3 +5,15 @@ */ #include +#include +#include + +#ifdef CONFIG_ALTERA_SDRAM +ulong board_get_usable_ram_top(ulong total_size) +{ + if (sdram_calculate_size() > SZ_2G) + return SZ_2G; + else + return sdram_calculate_size(); +} +#endif From patchwork Tue Mar 12 08:31:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1055141 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44JSw02xNLz9s47 for ; Tue, 12 Mar 2019 19:35:12 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0498BC21EF2; Tue, 12 Mar 2019 08:32:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 87F10C21F0F; Tue, 12 Mar 2019 08:32:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D3CBCC21F1F; Tue, 12 Mar 2019 08:31:47 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lists.denx.de (Postfix) with ESMTPS id 0B132C21F17 for ; Tue, 12 Mar 2019 08:31:42 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Mar 2019 01:31:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,470,1544515200"; d="scan'208";a="126201064" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.82]) by orsmga006.jf.intel.com with SMTP; 12 Mar 2019 01:31:38 -0700 Received: by ubuntu (sSMTP sendmail emulation); Tue, 12 Mar 2019 16:31:37 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Tue, 12 Mar 2019 16:31:10 +0800 Message-Id: <1552379474-12867-7-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> Cc: Chin Liang See , Ley Foon Tan , Dalon Westergreen Subject: [U-Boot] [PATCH 06/10] board: altera: Stratix10: Add ft_board_setup() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add ft_board_setup() function to setup memory banks before boot to Linux. Signed-off-by: Ley Foon Tan --- board/altera/stratix10-socdk/socfpga.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/board/altera/stratix10-socdk/socfpga.c b/board/altera/stratix10-socdk/socfpga.c index 99c10d313c..ca6e0e9085 100644 --- a/board/altera/stratix10-socdk/socfpga.c +++ b/board/altera/stratix10-socdk/socfpga.c @@ -5,6 +5,7 @@ */ #include +#include #include #include @@ -17,3 +18,27 @@ ulong board_get_usable_ram_top(ulong total_size) return sdram_calculate_size(); } #endif + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + int ret = 0; +#ifdef CONFIG_OF_LIBFDT + int bank; + int actual_bank = 0; + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (bd->bi_dram[bank].size) { + start[actual_bank] = bd->bi_dram[bank].start; + size[actual_bank++] = bd->bi_dram[bank].size; + } + } + + ret = fdt_fixup_memory_banks(blob, start, size, actual_bank); +#endif /* CONFIG_OF_LIBFDT */ + + return ret; +} +#endif From patchwork Tue Mar 12 08:31:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1055140 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44JSvm5BnWz9s47 for ; Tue, 12 Mar 2019 19:35:00 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 72852C21EEB; Tue, 12 Mar 2019 08:33:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 44C3FC21F0F; Tue, 12 Mar 2019 08:33:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2D4E6C21EBD; Tue, 12 Mar 2019 08:31:51 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lists.denx.de (Postfix) with ESMTPS id 81D93C21EA6 for ; Tue, 12 Mar 2019 08:31:46 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Mar 2019 01:31:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,470,1544515200"; d="scan'208";a="124721158" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.82]) by orsmga008.jf.intel.com with SMTP; 12 Mar 2019 01:31:42 -0700 Received: by ubuntu (sSMTP sendmail emulation); Tue, 12 Mar 2019 16:31:41 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Tue, 12 Mar 2019 16:31:11 +0800 Message-Id: <1552379474-12867-8-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> Cc: Chin Liang See , Ley Foon Tan , Dalon Westergreen Subject: [U-Boot] [PATCH 07/10] arm: socfpga: Enable OF_BOARD_SETUP for Stratix 10 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable OF_BOARD_SETUP for Stratix 10. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5e87371f8c..990e46fe06 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -36,6 +36,7 @@ config TARGET_SOCFPGA_STRATIX10 select ARMV8_SET_SMPEN select ARMV8_SPIN_TABLE select FPGA_STRATIX10 + select OF_BOARD_SETUP choice prompt "Altera SOCFPGA board select" From patchwork Tue Mar 12 08:31:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1055146 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44JSwx3SJLz9s47 for ; Tue, 12 Mar 2019 19:36:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2C2B2C21F18; Tue, 12 Mar 2019 08:34:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A4DAEC21EF2; Tue, 12 Mar 2019 08:33:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 17264C21F2A; Tue, 12 Mar 2019 08:31:54 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lists.denx.de (Postfix) with ESMTPS id B03D5C21F24 for ; Tue, 12 Mar 2019 08:31:50 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Mar 2019 01:31:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,470,1544515200"; d="scan'208";a="281889439" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.82]) by orsmga004.jf.intel.com with SMTP; 12 Mar 2019 01:31:46 -0700 Received: by ubuntu (sSMTP sendmail emulation); Tue, 12 Mar 2019 16:31:44 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Tue, 12 Mar 2019 16:31:12 +0800 Message-Id: <1552379474-12867-9-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> Cc: Chin Liang See , Ley Foon Tan , Dalon Westergreen Subject: [U-Boot] [PATCH 08/10] configs: stratix10: Change CONFIG_NR_DRAM_BANKS to 2 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Stratix 10 SoC support 2 DRAM banks. Signed-off-by: Ley Foon Tan --- configs/socfpga_stratix10_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 9e6d582ee3..4a14ea039e 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -6,7 +6,7 @@ CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y CONFIG_SPL=y CONFIG_IDENT_STRING="socfpga_stratix10" CONFIG_SPL_FS_FAT=y -CONFIG_NR_DRAM_BANKS=1 +CONFIG_NR_DRAM_BANKS=2 CONFIG_BOOTDELAY=5 CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y From patchwork Tue Mar 12 08:31:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1055142 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44JSwC41hqz9s47 for ; Tue, 12 Mar 2019 19:35:23 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1C5A7C21F1C; Tue, 12 Mar 2019 08:33:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E504DC21EF2; Tue, 12 Mar 2019 08:33:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C75CDC21F0C; Tue, 12 Mar 2019 08:31:58 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lists.denx.de (Postfix) with ESMTPS id C153BC21F02 for ; Tue, 12 Mar 2019 08:31:54 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Mar 2019 01:31:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,470,1544515200"; d="scan'208";a="130895551" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.82]) by fmsmga008.fm.intel.com with SMTP; 12 Mar 2019 01:31:49 -0700 Received: by ubuntu (sSMTP sendmail emulation); Tue, 12 Mar 2019 16:31:48 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Tue, 12 Mar 2019 16:31:13 +0800 Message-Id: <1552379474-12867-10-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> Cc: Chin Liang See , Ley Foon Tan , Dalon Westergreen Subject: [U-Boot] [PATCH 09/10] arm: socfpga: stratix10: Add cpu_has_been_warmreset() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add helper function cpu_has_been_warmreset() to check if CPU is from warm reset boot. Signed-off-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | 3 +++ arch/arm/mach-socfpga/reset_manager_s10.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h index 31b73edabe..e186296791 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h @@ -9,6 +9,7 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +int cpu_has_been_warmreset(void); void socfpga_bridges_reset(int enable); @@ -47,6 +48,8 @@ struct socfpga_reset_manager { #define RSTMGR_MPUMODRST_CORE0 0 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 #define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 +/* Watchdogs and MPU warm reset mask */ +#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 /* * Define a reset identifier, from which a permodrst bank ID diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index f176c38495..f8dd787cc6 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -103,3 +103,12 @@ void reset_deassert_peripherals_handoff(void) writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst); writel(0, &reset_manager_base->per0modrst); } + +/* + * Return non-zero if the CPU has been warm reset + */ +int cpu_has_been_warmreset(void) +{ + return readl(&reset_manager_base->status) & + RSTMGR_L4WD_MPU_WARMRESET_MASK; +} From patchwork Tue Mar 12 08:31:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 1055147 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44JSxT1bP5z9s47 for ; Tue, 12 Mar 2019 19:36:29 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E527AC21DD9; Tue, 12 Mar 2019 08:33:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 20FF6C21F0C; Tue, 12 Mar 2019 08:32:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2358FC21DE8; Tue, 12 Mar 2019 08:32:02 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lists.denx.de (Postfix) with ESMTPS id A220EC21F1B for ; Tue, 12 Mar 2019 08:31:57 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Mar 2019 01:31:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,470,1544515200"; d="scan'208";a="133568439" Received: from lftan-mobl.gar.corp.intel.com (HELO ubuntu) ([10.226.248.82]) by fmsmga007.fm.intel.com with SMTP; 12 Mar 2019 01:31:53 -0700 Received: by ubuntu (sSMTP sendmail emulation); Tue, 12 Mar 2019 16:31:52 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Tue, 12 Mar 2019 16:31:14 +0800 Message-Id: <1552379474-12867-11-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> References: <1552379474-12867-1-git-send-email-ley.foon.tan@intel.com> Cc: Chin Liang See , Ley Foon Tan , Dalon Westergreen Subject: [U-Boot] [PATCH 10/10] ddr: altera: Stratix10: Add ECC memory scrubbing X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Scrub memory content if ECC is enabled and it is not from warm reset boot. Enable icache and dcache before scrub memory and use "DC ZVA" instruction to clear memory to zeros. This instruction writes a cache line at a time and it can prevent false ECC error trigger if write cache line partially. Signed-off-by: Ley Foon Tan --- .../arm/mach-socfpga/include/mach/sdram_s10.h | 9 +++ drivers/ddr/altera/sdram_s10.c | 76 +++++++++++++++++++ 2 files changed, 85 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h index 89e355010d..354f80bfce 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h @@ -23,6 +23,7 @@ void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t bank_size[]); #define ECCCTRL1 0x100 #define ECCCTRL2 0x104 #define ERRINTEN 0x110 +#define ERRINTENS 0x114 #define INTMODE 0x11c #define INTSTAT 0x120 #define AUTOWB_CORRADDR 0x138 @@ -53,6 +54,10 @@ void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t bank_size[]); #define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) #define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f +#define DDR_HMC_ERRINTEN_INTMASK \ + (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ + DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK) + /* NOC DDR scheduler */ #define DDR_SCH_ID_COREID 0 #define DDR_SCH_ID_REVID 0x4 @@ -181,4 +186,8 @@ void setup_memory_banks(phys_addr_t bank_addr[], phys_size_t bank_size[]); #define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ (((x) >> 0) & 0xFF) +/* Firewall DDR scheduler MPFE */ +#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 +#define FW_HMC_ADAPTOR_MPU_MASK BIT(0) + #endif /* _SDRAM_S10_H_ */ diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index ae4e5ea2fd..2c691d3bee 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -22,6 +22,8 @@ static const struct socfpga_system_manager *sysmgr_regs = #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) +#define PGTABLE_OFF 0x4000 + /* The followring are the supported configurations */ u32 ddr_config[] = { /* DDR_CONFIG(Address order,Bank,Column,Row) */ @@ -135,6 +137,71 @@ static int poll_hmc_clock_status(void) SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); } +static void sdram_clear_mem(phys_addr_t addr, phys_size_t size) +{ + phys_size_t i; + + if (addr % CONFIG_SYS_CACHELINE_SIZE) { + printf("DDR: address 0x%lx not cacheline size aligned.\n", + (ulong)addr); + hang(); + } + + if (size % CONFIG_SYS_CACHELINE_SIZE) { + printf("DDR: size 0x%lx not multiple of cacheline size\n", + (ulong)size); + hang(); + } + + /* Use DC ZVA instruction to clear memory to zeros by a cache line */ + for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) { + asm("dc zva, %0" + : + : "r"(addr)); + addr += CONFIG_SYS_CACHELINE_SIZE; + } +} + +static void sdram_init_ecc_bits(phys_addr_t *bank_start, phys_size_t *bank_size) +{ + phys_size_t size, size_init; + phys_addr_t start_addr; + int bank; + unsigned int start = get_timer(0); + + icache_enable(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start_addr = bank_start[bank]; + size = bank_size[bank]; + + if (bank == 0) { + /* Initialize small block for page table */ + memset((void *)start_addr, 0, + PGTABLE_SIZE + PGTABLE_OFF); + gd->arch.tlb_addr = start_addr + PGTABLE_OFF; + gd->arch.tlb_size = PGTABLE_SIZE; + start_addr += PGTABLE_SIZE + PGTABLE_OFF; + size -= (PGTABLE_OFF + PGTABLE_SIZE); + dcache_enable(); + } + + while (size) { + size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size); + sdram_clear_mem(start_addr, size_init); + size -= size_init; + start_addr += size_init; + WATCHDOG_RESET(); + } + } + + dcache_disable(); + icache_disable(); + + printf("SDRAM-ECC: Initialized success with %d ms\n", + (unsigned int)get_timer(start)); +} + static void sdram_size_check(phys_addr_t bank_start[], phys_size_t bank_size[]) { phys_size_t total_ram_check = 0; @@ -451,6 +518,15 @@ int sdram_mmr_init_full(unsigned int unused) setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + writel(DDR_HMC_ERRINTEN_INTMASK, + SOCFPGA_SDR_ADDRESS + ERRINTENS); + + /* Enable non-secure writes to HMC Adapter for SDRAM ECC */ + writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); + + /* Initialize memory content if not from warm reset */ + if (!cpu_has_been_warmreset()) + sdram_init_ecc_bits(bank_start, bank_size); } else { clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |