From patchwork Tue Mar 12 01:49:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1055019 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44JHwB0vtYz9s4V for ; Tue, 12 Mar 2019 12:49:46 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OuSO4Quk"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44JHw96cnSzDqDr for ; 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Mon, 11 Mar 2019 18:49:33 -0700 (PDT) Received: from bobo.ibm.com ([1.132.158.219]) by smtp.gmail.com with ESMTPSA id m9sm10592891pfi.31.2019.03.11.18.49.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Mar 2019 18:49:32 -0700 (PDT) From: Nicholas Piggin To: pdbg@lists.ozlabs.org Date: Tue, 12 Mar 2019 11:49:14 +1000 Message-Id: <20190312014920.25368-2-npiggin@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190312014920.25368-1-npiggin@gmail.com> References: <20190312014920.25368-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 1/7] libpdbg: Fix CHECK_ERR macro to evaluate once in error case X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Nicholas Piggin --- libpdbg/operations.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/libpdbg/operations.h b/libpdbg/operations.h index dc5042a..85fc117 100644 --- a/libpdbg/operations.h +++ b/libpdbg/operations.h @@ -22,9 +22,10 @@ #define PRINT_ERR PR_DEBUG("failed\n"); #define CHECK_ERR(x) do { \ - if (x) { \ + typeof(x) __x = (x); \ + if (__x) { \ PRINT_ERR; \ - return x; \ + return __x; \ } \ } while(0) From patchwork Tue Mar 12 01:49:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1055020 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44JHwG3vxJz9s4V for ; Tue, 12 Mar 2019 12:49:50 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gC2kaWcX"; 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Mon, 11 Mar 2019 18:49:36 -0700 (PDT) Received: from bobo.ibm.com ([1.132.158.219]) by smtp.gmail.com with ESMTPSA id m9sm10592891pfi.31.2019.03.11.18.49.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Mar 2019 18:49:35 -0700 (PDT) From: Nicholas Piggin To: pdbg@lists.ozlabs.org Date: Tue, 12 Mar 2019 11:49:15 +1000 Message-Id: <20190312014920.25368-3-npiggin@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190312014920.25368-1-npiggin@gmail.com> References: <20190312014920.25368-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 2/7] libpdbg/p8chip.c: read status from correct target X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" --- libpdbg/p8chip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libpdbg/p8chip.c b/libpdbg/p8chip.c index 914c335..61b1e25 100644 --- a/libpdbg/p8chip.c +++ b/libpdbg/p8chip.c @@ -291,7 +291,7 @@ static int p8_thread_stop(struct thread *thread) CHECK_ERR(pib_write(&thread->target, DIRECT_CONTROLS_REG, DIRECT_CONTROL_SP_STOP)); /* Wait for thread to quiese */ - CHECK_ERR(pib_read(&chip->target, RAS_STATUS_REG, &val)); + CHECK_ERR(pib_read(&thread->target, RAS_STATUS_REG, &val)); if (i++ > RAS_STATUS_TIMEOUT) { PR_ERROR("Unable to quiesce thread %d (0x%016" PRIx64 ").\n", thread->id, val); From patchwork Tue Mar 12 01:49:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1055021 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44JHwK2rM5z9s7h for ; Tue, 12 Mar 2019 12:49:53 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; 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Mon, 11 Mar 2019 18:49:38 -0700 (PDT) Received: from bobo.ibm.com ([1.132.158.219]) by smtp.gmail.com with ESMTPSA id m9sm10592891pfi.31.2019.03.11.18.49.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Mar 2019 18:49:37 -0700 (PDT) From: Nicholas Piggin To: pdbg@lists.ozlabs.org Date: Tue, 12 Mar 2019 11:49:16 +1000 Message-Id: <20190312014920.25368-4-npiggin@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190312014920.25368-1-npiggin@gmail.com> References: <20190312014920.25368-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 3/7] libpdbg/p8chip.c: Only write the SP_STOP bit once X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" The workbook recipe is to write SP_STOP once, then poll for status. Also add a small delay between polling to give a reasonable timeout and avoid hitting the scom bus hard for no good reason. Signed-off-by: Nicholas Piggin --- libpdbg/p8chip.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/libpdbg/p8chip.c b/libpdbg/p8chip.c index 61b1e25..b93e953 100644 --- a/libpdbg/p8chip.c +++ b/libpdbg/p8chip.c @@ -286,9 +286,11 @@ static int p8_thread_stop(struct thread *thread) struct core *chip = target_to_core( pdbg_target_require_parent("core", &thread->target)); + /* Quiese active thread */ + CHECK_ERR(pib_write(&thread->target, DIRECT_CONTROLS_REG, DIRECT_CONTROL_SP_STOP)); + do { - /* Quiese active thread */ - CHECK_ERR(pib_write(&thread->target, DIRECT_CONTROLS_REG, DIRECT_CONTROL_SP_STOP)); + usleep(1); /* Wait for thread to quiese */ CHECK_ERR(pib_read(&thread->target, RAS_STATUS_REG, &val)); From patchwork Tue Mar 12 01:49:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1055022 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44JHwQ2Cl2z9s4V for ; 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Mon, 11 Mar 2019 18:49:41 -0700 (PDT) Received: from bobo.ibm.com ([1.132.158.219]) by smtp.gmail.com with ESMTPSA id m9sm10592891pfi.31.2019.03.11.18.49.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Mar 2019 18:49:40 -0700 (PDT) From: Nicholas Piggin To: pdbg@lists.ozlabs.org Date: Tue, 12 Mar 2019 11:49:17 +1000 Message-Id: <20190312014920.25368-5-npiggin@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190312014920.25368-1-npiggin@gmail.com> References: <20190312014920.25368-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 4/7] libpdbg/p8chip.c: release special wakeups for P8 X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" This copies the special wakeup release logic from p9chip.c Signed-off-by: Nicholas Piggin --- libpdbg/p8chip.c | 67 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 58 insertions(+), 9 deletions(-) diff --git a/libpdbg/p8chip.c b/libpdbg/p8chip.c index b93e953..71e6569 100644 --- a/libpdbg/p8chip.c +++ b/libpdbg/p8chip.c @@ -163,16 +163,11 @@ static int assert_special_wakeup(struct core *chip) return 0; } -#if 0 -/* TODO: Work out when to do this. */ -static int deassert_special_wakeup(struct core *chip) +static void deassert_special_wakeup(struct core *chip) { /* Assert special wakeup to prevent low power states */ - CHECK_ERR(pib_write(&chip->target, PMSPCWKUPFSP_REG, 0)); - - return 0; + pib_write(&chip->target, PMSPCWKUPFSP_REG, 0); } -#endif static struct thread_state get_thread_status(struct thread *thread) { @@ -318,6 +313,8 @@ static int p8_thread_stop(struct thread *thread) val |= PPC_BIT(8) >> thread->id; CHECK_ERR(pib_write(&chip->target, THREAD_ACTIVE_REG, val)); + thread->status = get_thread_status(thread); + return 0; } @@ -336,6 +333,8 @@ static int p8_thread_start(struct thread *thread) val |= PPC_BIT(thread->id); CHECK_ERR(pib_write(&chip->target, THREAD_ACTIVE_REG, val)); + thread->status = get_thread_status(thread); + return 0; } @@ -366,7 +365,7 @@ static int p8_ram_setup(struct thread *thread) return 1; tmp = target_to_thread(target); - if (!(get_thread_status(tmp).quiesced)) + if (!tmp->status.quiesced) return 1; } @@ -487,6 +486,16 @@ static int p8_thread_probe(struct pdbg_target *target) return 0; } +static void p8_thread_release(struct pdbg_target *target) +{ + struct core *core = target_to_core(pdbg_target_require_parent("core", target)); + struct thread *thread = target_to_thread(target); + + if (thread->status.quiesced) + /* this thread is still quiesced so don't release spwkup */ + core->release_spwkup = false; +} + static int p8_get_hid0(struct pdbg_target *chip, uint64_t *value) { CHECK_ERR(pib_read(chip, HID0_REG, value)); @@ -534,6 +543,7 @@ static struct thread p8_thread = { .compatible = "ibm,power8-thread", .class = "thread", .probe = p8_thread_probe, + .release = p8_thread_release, }, .step = p8_thread_step, .start = p8_thread_start, @@ -562,16 +572,55 @@ static int p8_core_probe(struct pdbg_target *target) if (!GETFIELD(PPC_BIT(0), value)) return -1; - assert_special_wakeup(core); + if (assert_special_wakeup(core)) + return -1; + + /* Child threads will set this to false if they are released while quiesced */ + core->release_spwkup = true; + return 0; } +static void p8_core_release(struct pdbg_target *target) +{ + struct pdbg_target *child; + struct core *core = target_to_core(target); + enum pdbg_target_status status; + + usleep(1); /* enforce small delay before and after it is cleared */ + + /* Probe and release all threads to ensure release_spwkup is up to + * date */ + pdbg_for_each_target("thread", target, child) { + status = pdbg_target_status(child); + + /* This thread has already been release so should have set + * release_spwkup to false if it was quiesced, */ + if (status == PDBG_TARGET_RELEASED) + continue; + + status = pdbg_target_probe(child); + if (status != PDBG_TARGET_ENABLED) + continue; + + /* Release the thread to ensure release_spwkup is updated. */ + pdbg_target_release(child); + } + + if (!core->release_spwkup) + return; + + deassert_special_wakeup(core); + usleep(10000); +} + static struct core p8_core = { .target = { .name = "POWER8 Core", .compatible = "ibm,power8-core", .class = "core", .probe = p8_core_probe, + .release = p8_core_release, }, }; DECLARE_HW_UNIT(p8_core); From patchwork Tue Mar 12 01:49:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1055023 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44JHwT27Mwz9s4V for ; Tue, 12 Mar 2019 12:50:01 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LXp1WTnK"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44JHwT0C3rzDqFG for ; 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Mon, 11 Mar 2019 18:49:44 -0700 (PDT) Received: from bobo.ibm.com ([1.132.158.219]) by smtp.gmail.com with ESMTPSA id m9sm10592891pfi.31.2019.03.11.18.49.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Mar 2019 18:49:43 -0700 (PDT) From: Nicholas Piggin To: pdbg@lists.ozlabs.org Date: Tue, 12 Mar 2019 11:49:18 +1000 Message-Id: <20190312014920.25368-6-npiggin@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190312014920.25368-1-npiggin@gmail.com> References: <20190312014920.25368-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 5/7] libpdbg: use MTMSRD opcode rather than MTMSR X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" XXX: have to ensure this still does the right thing on P9 --- libpdbg/operations.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libpdbg/operations.h b/libpdbg/operations.h index 85fc117..867f997 100644 --- a/libpdbg/operations.h +++ b/libpdbg/operations.h @@ -59,7 +59,7 @@ #define MTNIA_OPCODE 0x00000002UL #define MFNIA_OPCODE 0x00000004UL #define MFMSR_OPCODE 0x7c0000a6UL -#define MTMSR_OPCODE 0x7c000124UL +#define MTMSR_OPCODE 0x7c000164UL #define MFSPR_OPCODE 0x7c0002a6UL #define MTSPR_OPCODE 0x7c0003a6UL #define MFOCRF_OPCODE 0x7c100026UL From patchwork Tue Mar 12 01:49:19 2019 Content-Type: text/plain; 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Mon, 11 Mar 2019 18:49:46 -0700 (PDT) Received: from bobo.ibm.com ([1.132.158.219]) by smtp.gmail.com with ESMTPSA id m9sm10592891pfi.31.2019.03.11.18.49.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Mar 2019 18:49:46 -0700 (PDT) From: Nicholas Piggin To: pdbg@lists.ozlabs.org Date: Tue, 12 Mar 2019 11:49:19 +1000 Message-Id: <20190312014920.25368-7-npiggin@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190312014920.25368-1-npiggin@gmail.com> References: <20190312014920.25368-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 6/7] libpdbg/p8chip.c: ram state setup sequence match workbook X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" This makes a few changes to stop and ram procedure. First of all, the existing thread_stop procedure is also setting up some of the ram state. Change that to just do the stop sequence from the workbook, and move the ram stuff into ram setup and destroy. The workbook calls for inactive threads being rammed to set a thread active state before ram mode is exited, in order for GPRs modified by ramming to avoid getting lost. Currently the code does that in the stop sequence before ram mode is activated. The code also currently deasserts the thread active bit after exiting ram mode, which is not part of the workbook, so this is no longer done. Signed-off-by: Nicholas Piggin --- libpdbg/p8chip.c | 41 +++++++++++++---------------------------- 1 file changed, 13 insertions(+), 28 deletions(-) diff --git a/libpdbg/p8chip.c b/libpdbg/p8chip.c index 71e6569..cd4a50b 100644 --- a/libpdbg/p8chip.c +++ b/libpdbg/p8chip.c @@ -278,8 +278,6 @@ static int p8_thread_stop(struct thread *thread) { int i = 0; uint64_t val; - struct core *chip = target_to_core( - pdbg_target_require_parent("core", &thread->target)); /* Quiese active thread */ CHECK_ERR(pib_write(&thread->target, DIRECT_CONTROLS_REG, DIRECT_CONTROL_SP_STOP)); @@ -298,20 +296,8 @@ static int p8_thread_stop(struct thread *thread) } break; } - - /* We can continue ramming if either the - * thread is not active or the SRQ/LSU/TS bits - * are set. */ - } while ((val & RAS_STATUS_THREAD_ACTIVE) && - !((val & RAS_STATUS_SRQ_EMPTY) - && (val & RAS_STATUS_LSU_QUIESCED) - && (val & RAS_STATUS_TS_QUIESCE))); - - - /* Make the threads RAM thread active */ - CHECK_ERR(pib_read(&chip->target, THREAD_ACTIVE_REG, &val)); - val |= PPC_BIT(8) >> thread->id; - CHECK_ERR(pib_write(&chip->target, THREAD_ACTIVE_REG, val)); + } while (!(val & RAS_STATUS_INST_COMPLETE) && + !(val & RAS_STATUS_TS_QUIESCE)); thread->status = get_thread_status(thread); @@ -320,19 +306,9 @@ static int p8_thread_stop(struct thread *thread) static int p8_thread_start(struct thread *thread) { - uint64_t val; - struct core *chip = target_to_core( - pdbg_target_require_parent("core", &thread->target)); - /* Activate thread */ CHECK_ERR(pib_write(&thread->target, DIRECT_CONTROLS_REG, DIRECT_CONTROL_SP_START)); - /* Restore thread active */ - CHECK_ERR(pib_read(&chip->target, THREAD_ACTIVE_REG, &val)); - val &= ~(PPC_BIT(8) >> thread->id); - val |= PPC_BIT(thread->id); - CHECK_ERR(pib_write(&chip->target, THREAD_ACTIVE_REG, val)); - thread->status = get_thread_status(thread); return 0; @@ -369,8 +345,10 @@ static int p8_ram_setup(struct thread *thread) return 1; } - if (!(thread->status.active)) + if (!(thread->status.active)) { + PR_WARNING("Thread is in power save state, can not RAM\n"); return 2; + } /* Activate RAM mode */ CHECK_ERR(pib_read(&chip->target, RAM_MODE_REG, &ram_mode)); @@ -429,7 +407,14 @@ static int p8_ram_destroy(struct thread *thread) { struct core *chip = target_to_core( pdbg_target_require_parent("core", &thread->target)); - uint64_t ram_mode; + uint64_t val, ram_mode; + + if (!(get_thread_status(thread).active)) { + /* Mark the RAM thread active so GPRs stick */ + CHECK_ERR(pib_read(&chip->target, THREAD_ACTIVE_REG, &val)); + val |= PPC_BIT(8) >> thread->id; + CHECK_ERR(pib_write(&chip->target, THREAD_ACTIVE_REG, val)); + } /* Disable RAM mode */ CHECK_ERR(pib_read(&chip->target, RAM_MODE_REG, &ram_mode)); From patchwork Tue Mar 12 01:49:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1055025 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44JHwZ3F2sz9s9T for ; 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Mon, 11 Mar 2019 18:49:49 -0700 (PDT) Received: from bobo.ibm.com ([1.132.158.219]) by smtp.gmail.com with ESMTPSA id m9sm10592891pfi.31.2019.03.11.18.49.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Mar 2019 18:49:48 -0700 (PDT) From: Nicholas Piggin To: pdbg@lists.ozlabs.org Date: Tue, 12 Mar 2019 11:49:20 +1000 Message-Id: <20190312014920.25368-8-npiggin@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190312014920.25368-1-npiggin@gmail.com> References: <20190312014920.25368-1-npiggin@gmail.com> MIME-Version: 1.0 Subject: [Pdbg] [PATCH v2 7/7] libpdbg/p8chip.c: Emulate sreset using ramming for active threads X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicholas Piggin Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Based on patch from Alistair, some fixes and changes: - account HILE bit, set/clear MSR_LE - clear MSR_PR - don't use raw ramming (clearer this way, not perf critical) At the moment, must manually stop all threads in the core, and manually restart them. Can change behaviour depending on what exactly we want (e.g., sreset all threads may be good for debugging). Tested-by: Stewart Smith --- libpdbg/p8chip.c | 131 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 128 insertions(+), 3 deletions(-) diff --git a/libpdbg/p8chip.c b/libpdbg/p8chip.c index cd4a50b..ff21d6b 100644 --- a/libpdbg/p8chip.c +++ b/libpdbg/p8chip.c @@ -29,6 +29,7 @@ #define RAS_STATUS_TIMEOUT 100 #define DIRECT_CONTROLS_REG 0x0 +#define DIRECT_CONTROL_SP_SRESET PPC_BIT(60) #define DIRECT_CONTROL_SP_STEP PPC_BIT(61) #define DIRECT_CONTROL_SP_START PPC_BIT(62) #define DIRECT_CONTROL_SP_STOP PPC_BIT(63) @@ -314,10 +315,60 @@ static int p8_thread_start(struct thread *thread) return 0; } -static int p8_thread_sreset(struct thread *thread) +static void p8_ram_unquiesce_siblings(struct thread *thread) +{ + struct pdbg_target *target; + struct core *chip = target_to_core( + pdbg_target_require_parent("core", &thread->target)); + + pdbg_for_each_compatible(&chip->target, target, "ibm,power8-thread") { + struct thread *tmp; + + if (pdbg_target_probe(target) != PDBG_TARGET_ENABLED) + continue; + + tmp = target_to_thread(target); + if (!tmp->status.quiesced) + continue; + + if (!tmp->ram_did_quiesce) + continue; + + p8_thread_start(tmp); + + tmp->ram_did_quiesce = false; + } +} + +static int p8_ram_quiesce_siblings(struct thread *thread) { - /* Broken on p8 */ - return 1; + struct pdbg_target *target; + struct core *chip = target_to_core( + pdbg_target_require_parent("core", &thread->target)); + int rc = 0; + + pdbg_for_each_compatible(&chip->target, target, "ibm,power8-thread") { + struct thread *tmp; + + if (pdbg_target_probe(target) != PDBG_TARGET_ENABLED) + continue; + + tmp = target_to_thread(target); + if (tmp->status.quiesced) + continue; + + rc = p8_thread_stop(tmp); + if (rc) + break; + tmp->ram_did_quiesce = true; + } + + if (!rc) + return 0; + + p8_ram_unquiesce_siblings(thread); + + return rc; } static int p8_ram_setup(struct thread *thread) @@ -458,6 +509,80 @@ static int p8_ram_putxer(struct pdbg_target *thread, uint64_t value) return 0; } +#define SPR_SRR0 0x01a +#define SPR_SRR1 0x01b + +#define HID0_HILE PPC_BIT(19) + +#define MSR_HV PPC_BIT(3) /* Hypervisor mode */ +#define MSR_EE PPC_BIT(48) /* External Int. Enable */ +#define MSR_PR PPC_BIT(49) /* Problem State */ +#define MSR_FE0 PPC_BIT(52) /* FP Exception 0 */ +#define MSR_FE1 PPC_BIT(55) /* FP Exception 1 */ +#define MSR_IR PPC_BIT(58) /* Instructions reloc */ +#define MSR_DR PPC_BIT(59) /* Data reloc */ +#define MSR_RI PPC_BIT(62) /* Recoverable Interrupt */ +#define MSR_LE PPC_BIT(63) /* Little Endian */ + +static int p8_get_hid0(struct pdbg_target *chip, uint64_t *value); +static int emulate_sreset(struct thread *thread) +{ + struct pdbg_target *chip = pdbg_target_parent("core", &thread->target); + uint64_t hid0; + uint64_t old_nia, old_msr; + uint64_t new_nia, new_msr; + + printf("emulate sreset begin\n"); + CHECK_ERR(p8_get_hid0(chip, &hid0)); + printf("emulate sreset HILE=%d\n", !!(hid0 & HID0_HILE)); + CHECK_ERR(ram_getnia(&thread->target, &old_nia)); + CHECK_ERR(ram_getmsr(&thread->target, &old_msr)); + new_nia = 0x100; + new_msr = (old_msr & ~(MSR_PR | MSR_IR | MSR_DR | MSR_FE0 | MSR_FE1 | MSR_EE | MSR_RI)) | MSR_HV; + if (hid0 & HID0_HILE) + new_msr |= MSR_LE; + else + new_msr &= ~MSR_LE; + printf("emulate sreset old NIA:%llx MSR:%llx\n", old_nia, old_msr); + printf("emulate sreset new NIA:%llx MSR:%llx\n", new_nia, new_msr); + CHECK_ERR(ram_putspr(&thread->target, SPR_SRR0, old_nia)); + CHECK_ERR(ram_putspr(&thread->target, SPR_SRR1, old_msr)); + CHECK_ERR(ram_putnia(&thread->target, new_nia)); + CHECK_ERR(ram_putmsr(&thread->target, new_msr)); + printf("emulate sreset done\n"); + + return 0; +} + +static int p8_thread_sreset(struct thread *thread) +{ + int rc; + + if (!(thread->status.active)) { + CHECK_ERR(pib_write(&thread->target, DIRECT_CONTROLS_REG, DIRECT_CONTROL_SP_SRESET)); + thread->status = get_thread_status(thread); + + return 0; + } + + rc = p8_ram_quiesce_siblings(thread); + if (rc) + return rc; + + /* Thread was active, emulate the sreset */ + rc = p8_ram_setup(thread); + if (rc) { + p8_ram_unquiesce_siblings(thread); + return rc; + } + rc = emulate_sreset(thread); + p8_ram_destroy(thread); + p8_ram_unquiesce_siblings(thread); + if (rc) + return rc; + return p8_thread_start(thread); +} + /* * Initialise all viable threads for ramming on the given core. */