From patchwork Mon Oct 23 11:26:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 829261 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yLDct4mpxz9t7q for ; Mon, 23 Oct 2017 22:26:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751409AbdJWL0g (ORCPT ); Mon, 23 Oct 2017 07:26:36 -0400 Received: from mail.kernel.org ([198.145.29.99]:47744 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751396AbdJWL0f (ORCPT ); Mon, 23 Oct 2017 07:26:35 -0400 Received: from localhost.localdomain (li408-84.members.linode.com [106.187.88.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 76A4E2190B; Mon, 23 Oct 2017 11:26:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 76A4E2190B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=shawnguo@kernel.org From: Shawn Guo To: Kishon Vijay Abraham I Cc: Rob Herring , Pengcheng Li , Jianguo Sun , Jiancheng Xue , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo Subject: [PATCH v2 1/2] dt-bindings: add bindings doc for hi3798cv200 combphy Date: Mon, 23 Oct 2017 19:26:07 +0800 Message-Id: <1508757968-22729-2-git-send-email-shawnguo@kernel.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1508757968-22729-1-git-send-email-shawnguo@kernel.org> References: <1508757968-22729-1-git-send-email-shawnguo@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jianguo Sun It adds the device tree bindings for PCIE/SATA/USB3 combo PHY found on HiSilicon STB SoCs. Signed-off-by: Jianguo Sun Signed-off-by: Shawn Guo --- .../bindings/phy/phy-hi3798cv200-combphy.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt diff --git a/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt new file mode 100644 index 000000000000..5fd548f078f5 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt @@ -0,0 +1,19 @@ +HiSilicon STB PCIE/SATA/USB3 PHY + +Properties: +- compatible: Should be "hisilicon,hi3798cv200-combphy" +- #phy-cells: Should be 1. The cell number is used to select the phy mode + as defined in . +- clocks: The phandle to clock provider and clock specifier pair. +- resets: The phandle to reset controller and reset specifier pair. +- hisilicon,peripheral-syscon: The phandle to the peripheral controller. + +Example: + +combphy1: phy { + compatible = "hisilicon,hi3798cv200-combphy"; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY1_CLK>; + resets = <&crg 0x188 12>; + hisilicon,peripheral-syscon = <&peri_ctrl>; +};