From patchwork Mon Oct 23 11:12:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 829233 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yLDLZ37fLz9t3Z for ; Mon, 23 Oct 2017 22:14:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751595AbdJWLON (ORCPT ); Mon, 23 Oct 2017 07:14:13 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5070 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751589AbdJWLOM (ORCPT ); Mon, 23 Oct 2017 07:14:12 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 23 Oct 2017 04:13:49 -0700 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 23 Oct 2017 04:14:01 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 23 Oct 2017 04:14:01 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 23 Oct 2017 11:13:00 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 23 Oct 2017 11:13:00 +0000 Received: from moonraker.nvidia.com (Not Verified[10.21.132.144]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 23 Oct 2017 04:13:00 -0700 From: Jon Hunter To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding CC: Dmitry Osipenko , , , Jon Hunter Subject: [PATCH] clk: tegra: Mark APB clock as critical Date: Mon, 23 Oct 2017 12:12:52 +0100 Message-ID: <1508757172-13030-1-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Commit a140614373ae ("clk: tegra: Correct parent of the APBDMA clock") fixed the parent clock for APBDMA, but the consequence of this that after probing the APBDMA device, the APB Clock (or PCLK) is now disabled. Disabling the APB clock causes accesses to any other device on the APB to hang and prevent Tegra from booting. Currently, the APB clock is registered with the flag "CLK_IGNORE_UNUSED" to prevent the clock being disabled if unused on boot. However, even if it is used, it still needs to be always kept enabled and so update the flag for the APB clock to be "CLK_IS_CRITICAL". Fixes: a140614373ae ("clk: tegra: Correct parent of the APBDMA clock") Suggested-by: Peter De Schrijver Signed-off-by: Jon Hunter Acked-By: Peter De Schrijver --- drivers/clk/tegra/clk-tegra-super-gen4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c index 4f6fd307cb70..10047107c1dc 100644 --- a/drivers/clk/tegra/clk-tegra-super-gen4.c +++ b/drivers/clk/tegra/clk-tegra-super-gen4.c @@ -166,7 +166,7 @@ static void __init tegra_sclk_init(void __iomem *clk_base, clk_base + SYSTEM_CLK_RATE, 0, 2, 0, &sysrate_lock); clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | - CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, + CLK_IS_CRITICAL, clk_base + SYSTEM_CLK_RATE, 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); *dt_clk = clk; }