From patchwork Thu Mar 7 18:05:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1053214 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44FfxQ51rYz9s9N for ; Fri, 8 Mar 2019 05:56:42 +1100 (AEDT) Received: from localhost ([127.0.0.1]:57454 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1yC8-0000dO-6E for incoming@patchwork.ozlabs.org; Thu, 07 Mar 2019 13:56:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48439) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1xOm-0007FI-D5 for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1xOl-0006Of-Dm for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:40 -0500 Received: from [2001:41c9:1:41f::167] (port=51930 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h1xOj-00068n-6b; Thu, 07 Mar 2019 13:05:39 -0500 Received: from host86-177-156-179.range86-177.btcentralplus.com ([86.177.156.179] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h1xOW-0000Tl-If; Thu, 07 Mar 2019 18:05:24 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Thu, 7 Mar 2019 18:05:14 +0000 Message-Id: <20190307180520.13868-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> References: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.177.156.179 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH v2 1/7] target/ppc: introduce single fpr_offset() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Instead of having multiple copies of the offset calculation logic, move it to a single fpr_offset() function. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 7 ++++++- target/ppc/translate.c | 4 ++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 26604ddf98..4bb4e42670 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2563,9 +2563,14 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx) } /* Accessors for FP, VMX and VSX registers */ +static inline int fpr_offset(int i) +{ + return offsetof(CPUPPCState, vsr[i].u64[0]); +} + static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) { - return &env->vsr[i].u64[0]; + return (uint64_t *)((uintptr_t)env + fpr_offset(i)); } static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 819221f246..3b1992faf1 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6677,12 +6677,12 @@ GEN_TM_PRIV_NOOP(trechkpt); static inline void get_fpr(TCGv_i64 dst, int regno) { - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); + tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); } static inline void set_fpr(int regno, TCGv_i64 src) { - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0])); + tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); } static inline void get_avr64(TCGv_i64 dst, int regno, bool high) From patchwork Thu Mar 7 18:05:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1053211 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Ffqx00djz9s7T for ; Fri, 8 Mar 2019 05:51:56 +1100 (AEDT) Received: from localhost ([127.0.0.1]:57352 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1y7W-00047S-T6 for incoming@patchwork.ozlabs.org; Thu, 07 Mar 2019 13:51:54 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48320) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1xOh-0007CP-ID for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1xOf-0006F8-8l for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:35 -0500 Received: from [2001:41c9:1:41f::167] (port=51942 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h1xOb-00069P-Hz; Thu, 07 Mar 2019 13:05:31 -0500 Received: from host86-177-156-179.range86-177.btcentralplus.com ([86.177.156.179] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h1xOX-0000Tl-0r; Thu, 07 Mar 2019 18:05:25 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Thu, 7 Mar 2019 18:05:15 +0000 Message-Id: <20190307180520.13868-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> References: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.177.156.179 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH v2 2/7] target/ppc: introduce single vsrl_offset() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Instead of having multiple copies of the offset calculation logic, move it to a single vsrl_offset() function. This commit also renames the existing get_vsr()/set_vsr() functions to get_vsrl()/set_vsrl() which better describes their purpose. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 7 ++++++- target/ppc/translate/vsx-impl.inc.c | 12 ++++++------ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 4bb4e42670..4a7df13c2d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2573,9 +2573,14 @@ static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) return (uint64_t *)((uintptr_t)env + fpr_offset(i)); } +static inline int vsrl_offset(int i) +{ + return offsetof(CPUPPCState, vsr[i].u64[1]); +} + static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) { - return &env->vsr[i].u64[1]; + return (uint64_t *)((uintptr_t)env + vsrl_offset(i)); } static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index e73197e717..381ae0f2e9 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1,13 +1,13 @@ /*** VSX extension ***/ -static inline void get_vsr(TCGv_i64 dst, int n) +static inline void get_vsrl(TCGv_i64 dst, int n) { - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1])); + tcg_gen_ld_i64(dst, cpu_env, vsrl_offset(n)); } -static inline void set_vsr(int n, TCGv_i64 src) +static inline void set_vsrl(int n, TCGv_i64 src) { - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[n].u64[1])); + tcg_gen_st_i64(src, cpu_env, vsrl_offset(n)); } static inline int vsr_full_offset(int n) @@ -27,7 +27,7 @@ static inline void get_cpu_vsrh(TCGv_i64 dst, int n) static inline void get_cpu_vsrl(TCGv_i64 dst, int n) { if (n < 32) { - get_vsr(dst, n); + get_vsrl(dst, n); } else { get_avr64(dst, n - 32, false); } @@ -45,7 +45,7 @@ static inline void set_cpu_vsrh(int n, TCGv_i64 src) static inline void set_cpu_vsrl(int n, TCGv_i64 src) { if (n < 32) { - set_vsr(n, src); + set_vsrl(n, src); } else { set_avr64(n - 32, src, false); } From patchwork Thu Mar 7 18:05:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1053207 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44FfhZ1vH9z9s7T for ; Fri, 8 Mar 2019 05:45:34 +1100 (AEDT) Received: from localhost ([127.0.0.1]:57227 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1y1M-00077w-4W for incoming@patchwork.ozlabs.org; Thu, 07 Mar 2019 13:45:32 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48321) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1xOh-0007CQ-IY for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1xOe-0006Dv-24 for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:35 -0500 Received: from [2001:41c9:1:41f::167] (port=51938 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h1xOb-00069O-Fq; Thu, 07 Mar 2019 13:05:29 -0500 Received: from host86-177-156-179.range86-177.btcentralplus.com ([86.177.156.179] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h1xOX-0000Tl-Fx; Thu, 07 Mar 2019 18:05:25 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Thu, 7 Mar 2019 18:05:16 +0000 Message-Id: <20190307180520.13868-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> References: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.177.156.179 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH v2 3/7] target/ppc: move Vsr* macros from internal.h to cpu.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" It isn't possible to include internal.h from cpu.h so move the Vsr* macros into cpu.h alongside the other VMX/VSX register access functions. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 20 ++++++++++++++++++++ target/ppc/internal.h | 19 ------------------- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 4a7df13c2d..d0580c6b6d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2563,6 +2563,26 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx) } /* Accessors for FP, VMX and VSX registers */ +#if defined(HOST_WORDS_BIGENDIAN) +#define VsrB(i) u8[i] +#define VsrSB(i) s8[i] +#define VsrH(i) u16[i] +#define VsrSH(i) s16[i] +#define VsrW(i) u32[i] +#define VsrSW(i) s32[i] +#define VsrD(i) u64[i] +#define VsrSD(i) s64[i] +#else +#define VsrB(i) u8[15 - (i)] +#define VsrSB(i) s8[15 - (i)] +#define VsrH(i) u16[7 - (i)] +#define VsrSH(i) s16[7 - (i)] +#define VsrW(i) u32[3 - (i)] +#define VsrSW(i) s32[3 - (i)] +#define VsrD(i) u64[1 - (i)] +#define VsrSD(i) s64[1 - (i)] +#endif + static inline int fpr_offset(int i) { return offsetof(CPUPPCState, vsr[i].u64[0]); diff --git a/target/ppc/internal.h b/target/ppc/internal.h index f26a71ffcf..3ebbdf4da4 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -204,25 +204,6 @@ EXTRACT_HELPER(IMM8, 11, 8); EXTRACT_HELPER(DCMX, 16, 7); EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6); -#if defined(HOST_WORDS_BIGENDIAN) -#define VsrB(i) u8[i] -#define VsrSB(i) s8[i] -#define VsrH(i) u16[i] -#define VsrSH(i) s16[i] -#define VsrW(i) u32[i] -#define VsrSW(i) s32[i] -#define VsrD(i) u64[i] -#define VsrSD(i) s64[i] -#else -#define VsrB(i) u8[15 - (i)] -#define VsrSB(i) s8[15 - (i)] -#define VsrH(i) u16[7 - (i)] -#define VsrSH(i) s16[7 - (i)] -#define VsrW(i) u32[3 - (i)] -#define VsrSW(i) s32[3 - (i)] -#define VsrD(i) u64[1 - (i)] -#define VsrSD(i) s64[1 - (i)] -#endif static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { vsr->VsrD(0) = env->vsr[n].u64[0]; From patchwork Thu Mar 7 18:05:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1053210 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Ffqs6hVkz9s9h for ; Fri, 8 Mar 2019 05:51:53 +1100 (AEDT) Received: from localhost ([127.0.0.1]:57348 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1y7Q-0003yx-3A for incoming@patchwork.ozlabs.org; Thu, 07 Mar 2019 13:51:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48458) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1xOm-0007FP-P3 for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1xOl-0006Ow-IK for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:40 -0500 Received: from [2001:41c9:1:41f::167] (port=51958 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h1xOl-0006AC-6H; Thu, 07 Mar 2019 13:05:39 -0500 Received: from host86-177-156-179.range86-177.btcentralplus.com ([86.177.156.179] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h1xOX-0000Tl-SF; Thu, 07 Mar 2019 18:05:26 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Thu, 7 Mar 2019 18:05:17 +0000 Message-Id: <20190307180520.13868-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> References: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.177.156.179 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH v2 4/7] target/ppc: introduce avr_full_offset() function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" All TCG vector operations require pointers to the base address of the vector rather than separate access to the top and bottom 64-bits. Convert the VMX TCG instructions to use a new avr_full_offset() function instead of avr64_offset() which can then itself be written as a simple wrapper onto vsr_full_offset(). This same function can also reused in cpu_avr_ptr() to avoid having more than one copy of the offset calculation logic. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 12 +++++++++++- target/ppc/translate/vmx-impl.inc.c | 22 +++++++++++----------- target/ppc/translate/vsx-impl.inc.c | 5 ----- 3 files changed, 22 insertions(+), 17 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d0580c6b6d..2a2792306f 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2598,14 +2598,24 @@ static inline int vsrl_offset(int i) return offsetof(CPUPPCState, vsr[i].u64[1]); } +static inline int vsr_full_offset(int i) +{ + return offsetof(CPUPPCState, vsr[i].u64[0]); +} + static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) { return (uint64_t *)((uintptr_t)env + vsrl_offset(i)); } +static inline int avr_full_offset(int i) +{ + return vsr_full_offset(i + 32); +} + static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i) { - return &env->vsr[32 + i]; + return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i)); } void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c index f1b15ae2cb..4e5d0bc0e0 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -10,7 +10,7 @@ static inline TCGv_ptr gen_avr_ptr(int reg) { TCGv_ptr r = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[32 + reg].u64[0])); + tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg)); return r; } @@ -205,7 +205,7 @@ static void gen_mtvscr(DisasContext *ctx) } val = tcg_temp_new_i32(); - bofs = avr64_offset(rB(ctx->opcode), true); + bofs = avr_full_offset(rB(ctx->opcode)); #ifdef HOST_WORDS_BIGENDIAN bofs += 3 * 4; #endif @@ -284,9 +284,9 @@ static void glue(gen_, name)(DisasContext *ctx) \ } \ \ tcg_op(vece, \ - avr64_offset(rD(ctx->opcode), true), \ - avr64_offset(rA(ctx->opcode), true), \ - avr64_offset(rB(ctx->opcode), true), \ + avr_full_offset(rD(ctx->opcode)), \ + avr_full_offset(rA(ctx->opcode)), \ + avr_full_offset(rB(ctx->opcode)), \ 16, 16); \ } @@ -578,10 +578,10 @@ static void glue(gen_, NAME)(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_VPU); \ return; \ } \ - tcg_gen_gvec_4(avr64_offset(rD(ctx->opcode), true), \ + tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \ offsetof(CPUPPCState, vscr_sat), \ - avr64_offset(rA(ctx->opcode), true), \ - avr64_offset(rB(ctx->opcode), true), \ + avr_full_offset(rA(ctx->opcode)), \ + avr_full_offset(rB(ctx->opcode)), \ 16, 16, &g); \ } @@ -755,7 +755,7 @@ static void glue(gen_, name)(DisasContext *ctx) \ return; \ } \ simm = SIMM5(ctx->opcode); \ - tcg_op(avr64_offset(rD(ctx->opcode), true), 16, 16, simm); \ + tcg_op(avr_full_offset(rD(ctx->opcode)), 16, 16, simm); \ } GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12); @@ -850,8 +850,8 @@ static void gen_vsplt(DisasContext *ctx, int vece) } uimm = UIMM5(ctx->opcode); - bofs = avr64_offset(rB(ctx->opcode), true); - dofs = avr64_offset(rD(ctx->opcode), true); + bofs = avr_full_offset(rB(ctx->opcode)); + dofs = avr_full_offset(rD(ctx->opcode)); /* Experimental testing shows that hardware masks the immediate. */ bofs += (uimm << vece) & 15; diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 381ae0f2e9..7d02a235e7 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -10,11 +10,6 @@ static inline void set_vsrl(int n, TCGv_i64 src) tcg_gen_st_i64(src, cpu_env, vsrl_offset(n)); } -static inline int vsr_full_offset(int n) -{ - return offsetof(CPUPPCState, vsr[n].u64[0]); -} - static inline void get_cpu_vsrh(TCGv_i64 dst, int n) { if (n < 32) { From patchwork Thu Mar 7 18:05:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1053213 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44Ffv86tsZz9s7T for ; Fri, 8 Mar 2019 05:54:44 +1100 (AEDT) Received: from localhost ([127.0.0.1]:57401 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1yAE-0006oq-RN for incoming@patchwork.ozlabs.org; Thu, 07 Mar 2019 13:54:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48318) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1xOh-0007CN-Hp for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1xOf-0006FV-E6 for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:35 -0500 Received: from [2001:41c9:1:41f::167] (port=51952 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h1xOd-0006A5-DJ; Thu, 07 Mar 2019 13:05:32 -0500 Received: from host86-177-156-179.range86-177.btcentralplus.com ([86.177.156.179] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h1xOY-0000Tl-A9; Thu, 07 Mar 2019 18:05:26 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Thu, 7 Mar 2019 18:05:18 +0000 Message-Id: <20190307180520.13868-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> References: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.177.156.179 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH v2 5/7] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" By using the VsrD macro in avr64_offset() the same offset calculation can be used regardless of the host endian. This allows get_avr64() and set_avr64() to be simplified accordingly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 5 +++++ target/ppc/translate.c | 16 ++-------------- target/ppc/translate/vmx-impl.inc.c | 5 ----- 3 files changed, 7 insertions(+), 19 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2a2792306f..aebb6c01ee 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2608,6 +2608,11 @@ static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) return (uint64_t *)((uintptr_t)env + vsrl_offset(i)); } +static inline long avr64_offset(int i, bool high) +{ + return offsetof(CPUPPCState, vsr[32 + i].VsrD(high ? 0 : 1)); +} + static inline int avr_full_offset(int i) { return vsr_full_offset(i + 32); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3b1992faf1..a6cff20daf 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6687,24 +6687,12 @@ static inline void set_fpr(int regno, TCGv_i64 src) static inline void get_avr64(TCGv_i64 dst, int regno, bool high) { -#ifdef HOST_WORDS_BIGENDIAN - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, - vsr[32 + regno].u64[(high ? 0 : 1)])); -#else - tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, - vsr[32 + regno].u64[(high ? 1 : 0)])); -#endif + tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); } static inline void set_avr64(int regno, TCGv_i64 src, bool high) { -#ifdef HOST_WORDS_BIGENDIAN - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, - vsr[32 + regno].u64[(high ? 0 : 1)])); -#else - tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, - vsr[32 + regno].u64[(high ? 1 : 0)])); -#endif + tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); } #include "translate/fp-impl.inc.c" diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c index 4e5d0bc0e0..eb10c533ca 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -14,11 +14,6 @@ static inline TCGv_ptr gen_avr_ptr(int reg) return r; } -static inline long avr64_offset(int reg, bool high) -{ - return offsetof(CPUPPCState, vsr[32 + reg].u64[(high ? 0 : 1)]); -} - #define GEN_VR_LDX(name, opc2, opc3) \ static void glue(gen_, name)(DisasContext *ctx) \ { \ From patchwork Thu Mar 7 18:05:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1053202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44FfXy3H5Jz9s70 for ; Fri, 8 Mar 2019 05:38:57 +1100 (AEDT) Received: from localhost ([127.0.0.1]:57119 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1xux-000130-9F for incoming@patchwork.ozlabs.org; Thu, 07 Mar 2019 13:38:55 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48402) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h1xOl-0007FG-Bt for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h1xOj-0006M7-7b for qemu-devel@nongnu.org; Thu, 07 Mar 2019 13:05:39 -0500 Received: from [2001:41c9:1:41f::167] (port=51964 helo=mail.default.ilande.uk0.bigv.io) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1h1xOh-0006As-8Y; Thu, 07 Mar 2019 13:05:35 -0500 Received: from host86-177-156-179.range86-177.btcentralplus.com ([86.177.156.179] helo=kentang.home) by mail.default.ilande.uk0.bigv.io with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1h1xOY-0000Tl-Pi; Thu, 07 Mar 2019 18:05:27 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Thu, 7 Mar 2019 18:05:19 +0000 Message-Id: <20190307180520.13868-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> References: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.177.156.179 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH v2 6/7] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" When VSX support was initially added, the fpr registers were added at offset 0 of the VSR register and the vsrl registers were added at offset 1. This is in contrast to the VMX registers (the last 32 VSX registers) which are stored in host-endian order. Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also stored in host endian order to match the VMX registers. This ensures that TCG vector operations involving mixed VMX and VSX registers will function correctly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 4 ++-- target/ppc/internal.h | 8 ++++---- target/ppc/machine.c | 8 ++++---- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index aebb6c01ee..704e595014 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2585,7 +2585,7 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx) static inline int fpr_offset(int i) { - return offsetof(CPUPPCState, vsr[i].u64[0]); + return offsetof(CPUPPCState, vsr[i].VsrD(0)); } static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) @@ -2595,7 +2595,7 @@ static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) static inline int vsrl_offset(int i) { - return offsetof(CPUPPCState, vsr[i].u64[1]); + return offsetof(CPUPPCState, vsr[i].VsrD(1)); } static inline int vsr_full_offset(int i) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 3ebbdf4da4..fb6f64ed1e 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -206,14 +206,14 @@ EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6); static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - vsr->VsrD(0) = env->vsr[n].u64[0]; - vsr->VsrD(1) = env->vsr[n].u64[1]; + vsr->VsrD(0) = env->vsr[n].VsrD(0); + vsr->VsrD(1) = env->vsr[n].VsrD(1); } static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { - env->vsr[n].u64[0] = vsr->VsrD(0); - env->vsr[n].u64[1] = vsr->VsrD(1); + env->vsr[n].VsrD(0) = vsr->VsrD(0); + env->vsr[n].VsrD(1) = vsr->VsrD(1); } void helper_compute_fprf_float16(CPUPPCState *env, float16 arg); diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 756b6d2971..a92d0ad3a3 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -150,7 +150,7 @@ static int get_fpr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v = pv; - v->u64[0] = qemu_get_be64(f); + v->VsrD(0) = qemu_get_be64(f); return 0; } @@ -160,7 +160,7 @@ static int put_fpr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v = pv; - qemu_put_be64(f, v->u64[0]); + qemu_put_be64(f, v->VsrD(0)); return 0; } @@ -181,7 +181,7 @@ static int get_vsr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v = pv; - v->u64[1] = qemu_get_be64(f); + v->VsrD(1) = qemu_get_be64(f); return 0; } @@ -191,7 +191,7 @@ static int put_vsr(QEMUFile *f, void *pv, size_t size, { ppc_vsr_t *v = pv; - qemu_put_be64(f, v->u64[1]); + qemu_put_be64(f, v->VsrD(1)); return 0; } From patchwork Thu Mar 7 18:05:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 1053209 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ilande.co.uk Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44FfmL3WVXz9s9N for ; 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Thu, 07 Mar 2019 18:05:27 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, richard.henderson@linaro.org Date: Thu, 7 Mar 2019 18:05:20 +0000 Message-Id: <20190307180520.13868-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> References: <20190307180520.13868-1-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 86.177.156.179 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Tue, 02 Aug 2016 21:08:31 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.uk0.bigv.io) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:41c9:1:41f::167 Subject: [Qemu-devel] [PATCH v2 7/7] target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Now that all VSX registers are stored in host endian order, there is no need to go via different accessors depending upon the register number. Instead we introduce vsr64_offset() and use it directly from within get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}(). This also allows us to rewrite avr64_offset() and fpr_offset() in terms of the new vsr64_offset() function to more clearly express the relationship between the VSX, FPR and VMX registers, and also remove vsrl_offset() which is no longer required. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 20 ++++++++++---------- target/ppc/translate/vsx-impl.inc.c | 34 ++++------------------------------ 2 files changed, 14 insertions(+), 40 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 704e595014..5754281cfe 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2583,34 +2583,34 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx) #define VsrSD(i) s64[1 - (i)] #endif -static inline int fpr_offset(int i) +static inline int vsr64_offset(int i, bool high) { - return offsetof(CPUPPCState, vsr[i].VsrD(0)); + return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1)); } -static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) +static inline int vsr_full_offset(int i) { - return (uint64_t *)((uintptr_t)env + fpr_offset(i)); + return offsetof(CPUPPCState, vsr[i].u64[0]); } -static inline int vsrl_offset(int i) +static inline int fpr_offset(int i) { - return offsetof(CPUPPCState, vsr[i].VsrD(1)); + return vsr64_offset(i, true); } -static inline int vsr_full_offset(int i) +static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) { - return offsetof(CPUPPCState, vsr[i].u64[0]); + return (uint64_t *)((uintptr_t)env + fpr_offset(i)); } static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) { - return (uint64_t *)((uintptr_t)env + vsrl_offset(i)); + return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false)); } static inline long avr64_offset(int i, bool high) { - return offsetof(CPUPPCState, vsr[32 + i].VsrD(high ? 0 : 1)); + return vsr64_offset(i + 32, high); } static inline int avr_full_offset(int i) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 7d02a235e7..95a269fff0 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1,49 +1,23 @@ /*** VSX extension ***/ -static inline void get_vsrl(TCGv_i64 dst, int n) -{ - tcg_gen_ld_i64(dst, cpu_env, vsrl_offset(n)); -} - -static inline void set_vsrl(int n, TCGv_i64 src) -{ - tcg_gen_st_i64(src, cpu_env, vsrl_offset(n)); -} - static inline void get_cpu_vsrh(TCGv_i64 dst, int n) { - if (n < 32) { - get_fpr(dst, n); - } else { - get_avr64(dst, n - 32, true); - } + tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, true)); } static inline void get_cpu_vsrl(TCGv_i64 dst, int n) { - if (n < 32) { - get_vsrl(dst, n); - } else { - get_avr64(dst, n - 32, false); - } + tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, false)); } static inline void set_cpu_vsrh(int n, TCGv_i64 src) { - if (n < 32) { - set_fpr(n, src); - } else { - set_avr64(n - 32, src, true); - } + tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, true)); } static inline void set_cpu_vsrl(int n, TCGv_i64 src) { - if (n < 32) { - set_vsrl(n, src); - } else { - set_avr64(n - 32, src, false); - } + tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, false)); } #define VSX_LOAD_SCALAR(name, operation) \