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SFS:(10009020)(136003)(366004)(376002)(39860400002)(346002)(396003)(189003)(199004)(25786009)(8936002)(486006)(3846002)(53936002)(6306002)(2501003)(6512007)(4326008)(50226002)(5660300002)(2906002)(102836004)(107886003)(52116002)(97736004)(305945005)(99286004)(7736002)(71200400001)(54906003)(71190400001)(26005)(110136005)(186003)(6486002)(386003)(106356001)(6506007)(72206003)(14454004)(966005)(316002)(68736007)(66066001)(478600001)(86362001)(105586002)(256004)(81156014)(81166006)(2201001)(8676002)(36756003)(476003)(6116002)(6436002)(2616005)(14444005); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR11MB0028; H:DM5PR11MB1242.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: mHoWwUhBs5zaKL9oJBdBRu5+a0lHv5DkM/noE8xWbed8k8Jx7RT5aL4cjljS9eMVIMjl04lHAdWOQvJOm7sRqIpY7ILXGwdDErClxU1UXUQX+JnwcgVV43x+6wGtz/jaRBUk81QEK6cSyI34kzDTI3jYwWVlNTWq1/wkASkxR8HOSJRT51rWxFj0Ry0EO7n9DPhI5CqGyrj9O6lNuZ/3JlYCKMEq23oMT6XNhcNK4GPUStKkYMpwkkefcAAvBpjLDcf8M5mRd3XFBqFiFAsZ9MwpZ74CkYWqcykcYo33nnycub/U1VJOC7qj3dlLMFZOCn2WSS1p1zuim9CU4BrEysyFoWnl4CVFZ86tW37TuYEra96BC5y+YJRxa2bOJBu/QNLEXJ8DOtT+b/VrhDCV+oP/jsi9bSpxWR+7E4PhgmQ= Content-ID: <5F48573B33CB414D827C8D5FF4FAA52E@namprd11.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: ef52e8af-d222-4cc3-0c2a-08d6a0afde93 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Mar 2019 14:44:13.7557 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB0028 X-OriginatorOrg: microchip.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190304_064418_933650_C4C932A3 X-CRM114-Status: GOOD ( 12.49 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [216.71.154.253 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 DKIMWL_WL_MED DKIMwl.org - Whitelisted Medium sender X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eugen.Hristev@microchip.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Eugen Hristev During frame reception while the MCAN is in Error Passive state and the Receive Error Counter has thevalue MCAN_ECR.REC = 127, it may happen that MCAN_IR.MRAF is set although there was no Message RAM access failure. If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated. Work around: The Message RAM Access Failure interrupt routine needs to check whether MCAN_ECR.RP = '1' and MCAN_ECR.REC = '127'. In this case, reset MCAN_IR.MRAF. No further action is required. This affects versions older than 3.2.0 Errata explained on Sama5d2 SoC which includes this hardware block: http://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Family-Silicon-Errata-and-Data-Sheet-Clarification-DS80000803B.pdf chapter 6.2 Reproducibility: If 2 devices with m_can are connected back to back, configuring different bitrate on them will lead to interrupt storm on the receiving side, with error "Message RAM access failure occurred". Another way is to have a bad hardware connection. Bad wire connection can lead to this issue as well. This patch fixes the issue according to provided workaround. Signed-off-by: Eugen Hristev --- drivers/net/can/m_can/m_can.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 9b44940..deb274a 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -822,6 +822,27 @@ static int m_can_poll(struct napi_struct *napi, int quota) if (!irqstatus) goto end; + /* Errata workaround for issue "Needless activation of MRAF irq" + * During frame reception while the MCAN is in Error Passive state + * and the Receive Error Counter has the value MCAN_ECR.REC = 127, + * it may happen that MCAN_IR.MRAF is set although there was no + * Message RAM access failure. + * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated + * The Message RAM Access Failure interrupt routine needs to check + * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127. + * In this case, reset MCAN_IR.MRAF. No further action is required. + */ + if ((priv->version <= 31) && (irqstatus & IR_MRAF) && + (m_can_read(priv, M_CAN_ECR) & ECR_RP)) { + struct can_berr_counter bec; + + __m_can_get_berr_counter(dev, &bec); + if (bec.rxerr == 127) { + m_can_write(priv, M_CAN_IR, IR_MRAF); + irqstatus &= ~IR_MRAF; + } + } + psr = m_can_read(priv, M_CAN_PSR); if (irqstatus & IR_ERR_STATE) work_done += m_can_handle_state_errors(dev, psr);