From patchwork Sat Mar 2 03:47:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 1050547 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="BlvqWSQJ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44BC1W0KXcz9s1B for ; Sat, 2 Mar 2019 14:48:12 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 56E52C21C93; Sat, 2 Mar 2019 03:48:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1377AC21C38; Sat, 2 Mar 2019 03:48:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F14B4C21C38; Sat, 2 Mar 2019 03:48:02 +0000 (UTC) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by lists.denx.de (Postfix) with ESMTPS id 8C4C7C21BE5 for ; Sat, 2 Mar 2019 03:48:02 +0000 (UTC) Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4EAD720857; Sat, 2 Mar 2019 03:48:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1551498480; bh=SsvUyFln9a8ZvQftVFT9XktZrbh9PDA36WiL/gadGoc=; h=From:To:Cc:Subject:Date:From; b=BlvqWSQJdRrKfQb4exQGUjEPSk50sdKw18XEkrCnG/GFAsNNmERKRBwgsdHo6Lhwb dVuipxKeT3glqjeDoxZ3S9o12EljUSCTbko399ahNu8u/oONAgrBNgvfawbi5tTiG5 NrLkIzhYytlFkYg7J6inHzNviH96WzUHEGFe6W94= From: Dinh Nguyen To: marex@denx.de Date: Fri, 1 Mar 2019 21:47:47 -0600 Message-Id: <20190302034747.19819-1-dinguyen@kernel.org> X-Mailer: git-send-email 2.20.0 MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH] ARM: socfpga: configure pl310 from dts X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Read the cache properties of the L2 cache controller from the device tree and configure it. Signed-off-by: Dinh Nguyen --- arch/arm/include/asm/pl310.h | 4 ++++ arch/arm/mach-socfpga/misc.c | 45 +++++++++++++++++++++++++++++------- 2 files changed, 41 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index b83978b1cc..346dbe476d 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -19,6 +19,10 @@ #define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) #define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) +#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0) +#define L310_LATENCY_CTRL_RD(n) ((n) << 4) +#define L310_LATENCY_CTRL_WR(n) ((n) << 8) + #define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_L310 (3 << 6) #define L2X0_CACHE_ID_RTL_MASK 0x3f diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index fcf211d62b..b53f22e621 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -57,19 +57,48 @@ void enable_caches(void) } #ifdef CONFIG_SYS_L2_PL310 +static void setup_cache_latency(void) +{ + const void *blob = gd->fdt_blob; + int node; + u32 latency; + u32 data[3]; + + /* find the l2-cache node */ + node = fdt_node_offset_by_compatible(blob, -1, "arm,pl310-cache"); + + fdtdec_get_int_array(blob, node, "arm,tag-latency", data, 3); + latency = L310_LATENCY_CTRL_RD(data[0] - 1) | + L310_LATENCY_CTRL_WR(data[1] - 1) | + L310_LATENCY_CTRL_SETUP(data[2] - 1); + + writel(latency, &pl310->pl310_tag_latency_ctrl); + + fdtdec_get_int_array(blob, node, "arm,data-latency", data, 3); + latency = L310_LATENCY_CTRL_RD(data[0] - 1) | + L310_LATENCY_CTRL_WR(data[1] - 1) | + L310_LATENCY_CTRL_SETUP(data[2] - 1); + writel(latency, &pl310->pl310_data_latency_ctrl); + + if (fdtdec_get_bool(blob, node, "arm,shared-override")) + setbits_le32(&pl310->pl310_aux_ctrl, + L310_SHARED_ATT_OVERRIDE_ENABLE); + + if (fdtdec_get_config_int(blob, "prefetch-data", 1)) + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK); + + if (fdtdec_get_config_int(blob, "prefetch-instr", 1)) + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_INST_PREFETCH_MASK); +} + void v7_outer_cache_enable(void) { /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - writel(0x111, &pl310->pl310_tag_latency_ctrl); - writel(0x121, &pl310->pl310_data_latency_ctrl); - - /* enable BRESP, instruction and data prefetch, full line of zeroes */ - setbits_le32(&pl310->pl310_aux_ctrl, - L310_AUX_CTRL_DATA_PREFETCH_MASK | - L310_AUX_CTRL_INST_PREFETCH_MASK | - L310_SHARED_ATT_OVERRIDE_ENABLE); + setup_cache_latency(); /* Enable the L2 cache */ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);