From patchwork Sat Oct 21 21:54:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 828982 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HDdYjcYQ"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yKMBp4Wpwz9sBW for ; Sun, 22 Oct 2017 12:19:30 +1100 (AEDT) Received: from localhost ([::1]:59716 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e64vI-0007sg-NX for incoming@patchwork.ozlabs.org; Sat, 21 Oct 2017 21:19:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47532) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e61ix-0000Nw-Tr for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e61it-00024j-Or for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:31 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:51664) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e61it-0001wV-Gy for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:27 -0400 Received: by mail-lf0-x243.google.com with SMTP id r129so16443436lff.8 for ; Sat, 21 Oct 2017 14:54:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eLxtz3Pm0pnfqs7Y2sSFhB2l8YHQQDyonacSM6zGzic=; b=HDdYjcYQHohFBuMusWUQCReaWGNR0pSQmOd3kyuNi/HOTyv98MzB1dhMyXCTc7P//K aHDK/L7bwjIt3Oam6B7WBa02VawjF7ivToQM8g9y5xqPq+sBUc8/qpRcf08Qy50NCGEI u8bIjdr64yfxerOFY6UItAPwoPuWQTMu2DNA69vK3+qlTcNJVTwV+UTY+NrucGkytbo+ I0CQg50chfpwE7yN/IARKGunjPXGDEBmXPFumzakTU9yOC1ngQWIkbEp3ELHPLV/jD31 ZvcBbZO0bNAQ8uc6aUZ4o5wk4B4WuhrtZJeSRYXgPglKAvedq8XgNRIw/gbXRxVt2kdV 5L3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eLxtz3Pm0pnfqs7Y2sSFhB2l8YHQQDyonacSM6zGzic=; b=O4HVsm0Uq58VO7WLugPNAjrWJgN30OHKk39b/coZc6nGBkEV22s7N4WtUtDWOZz9hC 7Rje4DAGU/Yv5b5klFy7PZgDr3dzRCKqcRJZb6jyw1dgUMldZxDtY86dvRo0Ahs1Va+K 3a5CJX0vYaiSmBQaZyGqM3a5s8E45edwBBh9aMedEqabq0XyTHoYiZiBZd71KaQtJb/+ 4GqCPP6S8k28vb6bxzAi1zZ6uinHGk5GKjkleQriwFWKOl+a+zmJN3yY4CdkZxbajV9E jtj76BbBF4goBDoqJuTEs6otQTSO79nd05piMiAU6abRp9BI1D1dUSFdTbkpNRIvAikv 4HMg== X-Gm-Message-State: AMCzsaVGPjdPRik8ix0B7XmoxYAY4LvyTtbMvVo6JvOuGvYjHvocUa7r mgo7/a50RgFMcaY4mVNEMaQI9WzP X-Google-Smtp-Source: ABhQp+SF4b22zRS2U9T2X5AV+V0JNaEvrh8Qitte0NmIhx3Z9bdpunaNKt6EYeSfTnM3ydC7ftHuXg== X-Received: by 10.46.0.23 with SMTP id 23mr4375885lja.187.1508622864701; Sat, 21 Oct 2017 14:54:24 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id q87sm731173lfg.35.2017.10.21.14.54.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Oct 2017 14:54:23 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sat, 21 Oct 2017 23:54:09 +0200 Message-Id: <20171021215420.19787-2-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171021215420.19787-1-frasse.iglesias@gmail.com> References: <20171021215420.19787-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 X-Mailman-Approved-At: Sat, 21 Oct 2017 21:15:24 -0400 Subject: [Qemu-devel] [PATCH v2 01/12] m25p80: Add support for continuous read out of RDSR and READ_FSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for continuous read out of the RDSR and READ_FSR status registers until the chip select is deasserted. Signed-off-by: Francisco Iglesias --- hw/block/m25p80.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index a2438b9..2971519 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -423,6 +423,7 @@ typedef struct Flash { uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; uint32_t len; uint32_t pos; + bool data_read_loop; uint8_t needed_bytes; uint8_t cmd_in_progress; uint32_t cur_addr; @@ -983,6 +984,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) } s->pos = 0; s->len = 1; + s->data_read_loop = true; s->state = STATE_READING_DATA; break; @@ -993,6 +995,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) } s->pos = 0; s->len = 1; + s->data_read_loop = true; s->state = STATE_READING_DATA; break; @@ -1133,6 +1136,7 @@ static int m25p80_cs(SSISlave *ss, bool select) s->pos = 0; s->state = STATE_IDLE; flash_sync_dirty(s, -1); + s->data_read_loop = false; } DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); @@ -1198,7 +1202,9 @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) s->pos++; if (s->pos == s->len) { s->pos = 0; - s->state = STATE_IDLE; + if (!s->data_read_loop) { + s->state = STATE_IDLE; + } } break; From patchwork Sat Oct 21 21:54:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 828980 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="D89o8uIf"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yKM9M6ZkQz9t2M for ; Sun, 22 Oct 2017 12:18:15 +1100 (AEDT) Received: from localhost ([::1]:59713 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e64u5-0006vB-PI for incoming@patchwork.ozlabs.org; Sat, 21 Oct 2017 21:18:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47534) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e61ix-0000Ny-U4 for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e61it-000259-QN for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:31 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:54759) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e61it-00021E-Ja for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:27 -0400 Received: by mail-lf0-x241.google.com with SMTP id d10so16435437lfg.11 for ; Sat, 21 Oct 2017 14:54:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9aSzQLHm5JK8PQyX1bBIhU+r7LHtN87YLNqY/RmOfII=; b=D89o8uIfMbQO/yB5IEESPNAIKPoLnPbFtf4DSww5uGg/7idNK/7F63w2r5Th7UsN6K mC0/EkYYGSoo3yeBE5WxVRKXFAyB6dE6WKEZgxJPpYuVxchZeoV3AwG6s8Vqg6ufZxi4 giWcJo2giN/p0qjBzc1x3aZeMryYtVeGDlaM1LIuG/IfIj5oCp7n8chykI+iC1qb28Hv UODI+/GStQxwiKf5+GnmfRFD6OBaJUIoE7oslI5g25xHy5mDzSYBxcK5ysIa5EbqIDHH 3Ih+6edaJMA+4o0wthMP5SLruHnO0228jljoOftrGIltAA4zsuF3ebLtXoweaurB8qsR eL3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9aSzQLHm5JK8PQyX1bBIhU+r7LHtN87YLNqY/RmOfII=; b=dW4uOyZhxlnzG/ywtzz+qHS5UqtBlQklpifmIixO/e3g3CFCgd4PXzbA/SWng53FTe nKrs+mVW4c+z03AoF2kU6WDI2IA0rHztKdtnKqcutkZbnLBkU94ksfHJrsA5V5BuMp8o sKY5gLkiDZqOVjmbflRF29SI+fgqPebnpdEomBhFpxXBHSeG73NAz+tnE8Bq+RXTk8o/ IyV5IlDJ9Ki+saOxfjnlVRHARbKJ2hnI7lFmtJ+juS6MjV9caAUNgpSnPilOlqRC1pQi x0TQ5VGcgf9KBnNs2arEOILFqDVrLiGdzBZ6zEklojR1Z3YmbqnybeDjdE9QFZX1JVsR Lw3Q== X-Gm-Message-State: AMCzsaWKudW216LRRarZx0Td1ELAXBSfvQ2qvSSch89Szp7KS6++Vzi4 xyDrhG7vhwrWhx/0HzY4aaX9RSj7 X-Google-Smtp-Source: ABhQp+Sd2/qsED7zTAf3XX/m5N5FPfA0W2lpOa5P4BcCaWQk6tpoJfykiGwrPYqtKZOjrojRoZLc+Q== X-Received: by 10.46.65.216 with SMTP id d85mr3966123ljf.156.1508622865975; Sat, 21 Oct 2017 14:54:25 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id q87sm731173lfg.35.2017.10.21.14.54.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Oct 2017 14:54:25 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sat, 21 Oct 2017 23:54:10 +0200 Message-Id: <20171021215420.19787-3-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171021215420.19787-1-frasse.iglesias@gmail.com> References: <20171021215420.19787-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 X-Mailman-Approved-At: Sat, 21 Oct 2017 21:15:24 -0400 Subject: [Qemu-devel] [PATCH v2 02/12] m25p80: Add support for SST READ ID 0x90/0xAB commands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for SST READ ID 0x90/0xAB commands for reading out the flash manufacuter ID and device ID. Signed-off-by: Francisco Iglesias --- hw/block/m25p80.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 2971519..c85e8fa 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -355,6 +355,8 @@ typedef enum { DPP = 0xa2, QPP = 0x32, QPP_4 = 0x34, + RDID_90 = 0x90, + RDID_AB = 0xab, ERASE_4K = 0x20, ERASE4_4K = 0x21, @@ -405,6 +407,7 @@ typedef enum { MAN_MACRONIX, MAN_NUMONYX, MAN_WINBOND, + MAN_SST, MAN_GENERIC, } Manufacturer; @@ -476,6 +479,8 @@ static inline Manufacturer get_man(Flash *s) return MAN_SPANSION; case 0xC2: return MAN_MACRONIX; + case 0xBF: + return MAN_SST; default: return MAN_GENERIC; } @@ -1018,6 +1023,21 @@ static void decode_new_cmd(Flash *s, uint32_t value) s->state = STATE_READING_DATA; break; + case RDID_90: + case RDID_AB: + DB_PRINT_L(0, "populated manf/dev ID\n"); + if (get_man(s) == MAN_SST) { + s->data[0] = s->pi->id[0]; + s->data[1] = s->pi->id[2]; + s->pos = 0; + s->len = 2; + s->data_read_loop = true; + s->state = STATE_READING_DATA; + } else { + qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); + } + break; + case BULK_ERASE: if (s->write_enable) { DB_PRINT_L(0, "chip erase\n"); From patchwork Sat Oct 21 21:54:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 828979 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="TWW/gR6H"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yKM7h3b6dz9t2M for ; Sun, 22 Oct 2017 12:16:48 +1100 (AEDT) Received: from localhost ([::1]:59706 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e64sg-0005fo-Gi for incoming@patchwork.ozlabs.org; Sat, 21 Oct 2017 21:16:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47533) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e61ix-0000Nx-Tv for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e61iv-0002AA-C6 for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:31 -0400 Received: from mail-lf0-x242.google.com ([2a00:1450:4010:c07::242]:53845) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e61iv-000268-4W for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:29 -0400 Received: by mail-lf0-x242.google.com with SMTP id l23so16439029lfk.10 for ; Sat, 21 Oct 2017 14:54:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tSl7eQso+q094Y+cEKkGThU70ADeRNAjYQi//rxRY1E=; b=TWW/gR6HlLPAr1Alzw1G/+B4nPTjqwXBlEmP5jegQ+dkBp/qAGR8b3cJEnay0nQVuj 3ZYt4molX1VBU3Rr6oPkzDi1McwdCdaZIrZG7NDzgB2RcU0Qhj0gKI92i5J2cOjmLTq2 Ov0JpqI2d4AacpgP6GEaxS8h4hUdtFrI+Np6vuu1NLv4cPTFOIeyDDZngBlt/dML9Fz4 sT4/1m5tb/OZdwZ/G46PVUwsDe0RuM+sNBR/JrobfOjlQOT4IcGVGqb+c87nrw7/a9X+ zU45wJp2kpCQ00YeeH3XUv1zsiTsQTFPCfVakWeCdGNa6o6wSDNS8RjXcunI4t0x+AZ2 yO2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tSl7eQso+q094Y+cEKkGThU70ADeRNAjYQi//rxRY1E=; b=nrSNR/yIHhB9UmKZybo1iLKhxa4AWs3JSgDMsAPTvUEa1bxBrFpcLKe9ov3JUPiosz Br9xq5RevWAZJ9xQy2MDqiqk3cq5HHfnf19hCiX38+jv+VrKlzc00zwJdn9fQMUo+RAq hKIsD7wOGt3R0cSpaqDDZ4KEnJAIzrFTZq6ibvcFo7ww7MShAOoAWVchQchOAr2AB16I GfKPc9tIsCOfoJPqGGE9l+0r+5TV6tooh8rrvN8VOEoucnVjnPCqOMxzisLeot6FDyWx Mvg+8VguGrmV9nGTdGObUUqcxtnSrxsJRnoIj2tqTgFV1Fe0ueqLzqO9KqYNtFaiRn95 MQpg== X-Gm-Message-State: AMCzsaW3Fn6GV6QtaK6I1NIoCbRJvAqpXF5CV3Vh4SJlhLZ/kFsMurSN jtB6JJaiS8J4CQ1fLaw63b/4GWgT X-Google-Smtp-Source: ABhQp+S48GuwR9dy6cu+Kej+Cqpfjw4pegvEptnR/a2KAVATvePMlhwSg58j8bhHXXXk8o3zlzizYA== X-Received: by 10.46.88.73 with SMTP id x9mr3729431ljd.80.1508622867519; Sat, 21 Oct 2017 14:54:27 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id q87sm731173lfg.35.2017.10.21.14.54.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Oct 2017 14:54:26 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sat, 21 Oct 2017 23:54:11 +0200 Message-Id: <20171021215420.19787-4-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171021215420.19787-1-frasse.iglesias@gmail.com> References: <20171021215420.19787-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 X-Mailman-Approved-At: Sat, 21 Oct 2017 21:15:25 -0400 Subject: [Qemu-devel] [PATCH v2 03/12] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for the bank address register access commands (BRRD/BRWR) and the BULK_ERASE (0x60) command. Signed-off-by: Francisco Iglesias --- hw/block/m25p80.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index c85e8fa..3d2975c 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -331,6 +331,8 @@ typedef enum { WRDI = 0x4, RDSR = 0x5, WREN = 0x6, + BRRD = 0x16, + BRWR = 0x17, JEDEC_READ = 0x9f, BULK_ERASE = 0xc7, READ_FSR = 0x70, @@ -368,6 +370,8 @@ typedef enum { EN_4BYTE_ADDR = 0xB7, EX_4BYTE_ADDR = 0xE9, + BULK_ERASE_60 = 0x60, + EXTEND_ADDR_READ = 0xC8, EXTEND_ADDR_WRITE = 0xC5, @@ -975,6 +979,15 @@ static void decode_new_cmd(Flash *s, uint32_t value) } break; + case BRWR: + if (s->write_enable) { + s->needed_bytes = 1; + s->pos = 0; + s->len = 0; + s->state = STATE_COLLECTING_DATA; + } + break; + case WRDI: s->write_enable = false; break; @@ -1004,6 +1017,12 @@ static void decode_new_cmd(Flash *s, uint32_t value) s->state = STATE_READING_DATA; break; + case BRRD: + s->pos = 0; + s->len = 1; + s->state = STATE_READING_DATA; + break; + case JEDEC_READ: DB_PRINT_L(0, "populated jedec code\n"); for (i = 0; i < s->pi->id_len; i++) { @@ -1038,6 +1057,7 @@ static void decode_new_cmd(Flash *s, uint32_t value) } break; + case BULK_ERASE_60: case BULK_ERASE: if (s->write_enable) { DB_PRINT_L(0, "chip erase\n"); From patchwork Sat Oct 21 21:54:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 828983 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="W2FJdfH6"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yKMCb3f8wz9sBW for ; Sun, 22 Oct 2017 12:20:11 +1100 (AEDT) Received: from localhost ([::1]:59719 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e64vx-0008Sm-Hc for incoming@patchwork.ozlabs.org; Sat, 21 Oct 2017 21:20:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47535) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e61ix-0000Nz-UQ for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e61ix-0002GZ-3l for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:32 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:48750) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e61iw-0002Ci-SH for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:31 -0400 Received: by mail-lf0-x243.google.com with SMTP id a69so16454032lfe.5 for ; Sat, 21 Oct 2017 14:54:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FdiE8tyGJHZgwvotlTJPUBZEI/Ued2X7KcFJfF1QTwY=; b=W2FJdfH6H9HNIw3WOpxu/GLrpWQTqga+wjQc5p40Rs3SBF+/p9HEHXZppC0nY3Hh+S 7L5jVyRAasjRI47B+RRyf7sS0JKQFaYqk/J34vvKKhe8+XkQrZcPKmLJhINBKULD4dQ5 Xp7ui8tVRoMtxtRpiyRRTrpkcp9/Q7PxPT83uBNRw+B5KkpFKaS4YcNS7F/x4anSOcYj NlID4v2vnrgYvGZnR+bZyvG/jeEo0uWwF80De+xHg8dSdkUajqV6UGwTAaqaXkbWGwUw BtLDnxvF0dGFZI0stb5LGNt7dwIrBUx6sTYmtfwE4xiGHv7JFyigRNhFkS2Zx/ERb242 VB2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FdiE8tyGJHZgwvotlTJPUBZEI/Ued2X7KcFJfF1QTwY=; b=hWcFruqZPsfeOenAf0k4d6VNrkuk+0Le9aZuGjikoy/fIvgRIJ9b1kFbUGZerm5cN+ SGD+RJRESf96L96DovmSGwatajms4mvIxmfcDTR3DXwQgnhhOopY+7SEkTFkSWGTA35u jTIAHZ8irwnUBpPCrzDm3YMjQlXGrGdaXG+FfrVnzupqv/gVPYky/G2/V3VVqWXOm9KO Y23kLLnkAwNT0HnB99lEWs3PQcx4QvFQMUxcRhyaUZw+hiT1VxqAhwi+LoYbQwQEkHh9 cPa9o1hPqvrOUTEG6kfpv6prj0iWntyCWgTqbGMbYniVfdqfgKDuA80v66pQ/SjI8P+v 9Wtg== X-Gm-Message-State: AMCzsaUZlodw/+0wz8kK9kOKE8Yu5cIBA6ovFwd/Gtno/dsuHJOsSaut rtrjLANp22gCyXf4VcZZq8O91QDg X-Google-Smtp-Source: ABhQp+S+2NqKp5cxKSGqsRhB3mrFV9uGwwXpXu79lZpKfzJsKCfCZjSAkDQh/2TGgg2ZqG9OE+Hw4g== X-Received: by 10.46.80.16 with SMTP id e16mr3735842ljb.165.1508622868876; Sat, 21 Oct 2017 14:54:28 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id q87sm731173lfg.35.2017.10.21.14.54.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Oct 2017 14:54:28 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sat, 21 Oct 2017 23:54:12 +0200 Message-Id: <20171021215420.19787-5-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171021215420.19787-1-frasse.iglesias@gmail.com> References: <20171021215420.19787-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 X-Mailman-Approved-At: Sat, 21 Oct 2017 21:15:25 -0400 Subject: [Qemu-devel] [PATCH v2 04/12] m25p80: Add support for n25q512a11 and n25q512a13 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for Micron (Numonyx) n25q512a11 and n25q512a13 flashes. Signed-off-by: Francisco Iglesias --- hw/block/m25p80.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 3d2975c..7f3fcc4 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -240,6 +240,8 @@ static const FlashPartInfo known_devices[] = { { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, + { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, + { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, From patchwork Sat Oct 21 21:54:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 828984 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="AlNuB3Tv"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yKMDW5mzYz9sBW for ; Sun, 22 Oct 2017 12:20:59 +1100 (AEDT) Received: from localhost ([::1]:59727 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e64wj-0000xK-QM for incoming@patchwork.ozlabs.org; Sat, 21 Oct 2017 21:20:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47569) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e61j0-0000OM-3a for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e61iy-0002MI-Mf for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:34 -0400 Received: from mail-lf0-x244.google.com ([2a00:1450:4010:c07::244]:51664) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e61iy-0002I2-F8 for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:32 -0400 Received: by mail-lf0-x244.google.com with SMTP id r129so16443549lff.8 for ; Sat, 21 Oct 2017 14:54:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eTuc2E1/iSb4OMamGe+sju0ul3InQlHCb5VgukXOOeM=; b=AlNuB3Tvsp6lPgreKAU3QSESfZKBzM1w7PvQbi3seGK6ri6vDXzWEhe6/E6dxYxn48 MN9tOUa0rU90L4QK0FZL0SV3PPVANEZTzKN/vVqdYNfEQI1UMUUHJaw5Igq+st/1Nf08 934r/ISyvNvwRyfAgtwIURe5SBBcjS3R9X9HFDKdFfCf33KyHbeup2Sf45JgFQs6qF3w ou7mkNUhD/KI0jynFUWc4WCQvOHzvWWwl2hDlwL0xaY5OUPc94Mkis7H/NXU+IDb7ji5 +a5Af+F6BJ690LOJRVsdvFt89r6rJ/ESmZYPPPOrp9MSj4tNuxF/LHYKScD1QKrCxxMx JzyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eTuc2E1/iSb4OMamGe+sju0ul3InQlHCb5VgukXOOeM=; b=OabgmxR2yBBSETKnrlhsUV9AqM4bVccSZ0mb8n+qJoliIcREHY1P4MqNT0+cOK1HuC F0J++jLDudzWCcWmWkBBN07gJsR866WKmVjnbAokHe6lV6wQpWWVtmhlQNHkuPLM8WIu dhaBXpqwOUfpZaDmJ7qyYSYx9Jd72cp6mrJ7a1anyTePSOmxTaa90WNqy9SPKAjTF9di z9RWwNLul3Sfd6fp/+lI0x3h5/INtiYG0nsVHOb9IZSLaDsKIg1649aFEtnJTulDZ21Q 6zXXl/bIEyNsYkJdmrRtJ+DbMxViEFpNKwm/HpBa0gN3a3+c127WQnNYTstfRwULywSF PWQQ== X-Gm-Message-State: AMCzsaVdArMm586bhzkuLsQy1CwGcQ2zzYkI6RLGmbvSOUbl6T9hXLE6 rWJyKIYGciafLuqdLQNqcm8De4bu X-Google-Smtp-Source: ABhQp+TN61lUW7lLsIdOllakMnSsfV73wsmTLmAc7u1Lt9aV8Ps0N2HfuzJYgEu+xwRgOYoqmd56Mg== X-Received: by 10.46.69.6 with SMTP id s6mr3817123lja.76.1508622870617; Sat, 21 Oct 2017 14:54:30 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id q87sm731173lfg.35.2017.10.21.14.54.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Oct 2017 14:54:29 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sat, 21 Oct 2017 23:54:13 +0200 Message-Id: <20171021215420.19787-6-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171021215420.19787-1-frasse.iglesias@gmail.com> References: <20171021215420.19787-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::244 X-Mailman-Approved-At: Sat, 21 Oct 2017 21:15:25 -0400 Subject: [Qemu-devel] [PATCH v2 05/12] xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the header for consistency. Also move out a define and remove two dubbel included headers (while touching the code). Finally, add 4 byte address commands to the FlashCMD enum. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 34 ---------------------------------- include/hw/ssi/xilinx_spips.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 34 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index ef56d35..93b9e43 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -27,8 +27,6 @@ #include "sysemu/sysemu.h" #include "hw/ptimer.h" #include "qemu/log.h" -#include "qemu/fifo8.h" -#include "hw/ssi/ssi.h" #include "qemu/bitops.h" #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" @@ -116,43 +114,11 @@ /* 16MB per linear region */ #define LQSPI_ADDRESS_BITS 24 -/* Bite off 4k chunks at a time */ -#define LQSPI_CACHE_SIZE 1024 #define SNOOP_CHECKING 0xFF #define SNOOP_NONE 0xFE #define SNOOP_STRIPING 0 -typedef enum { - READ = 0x3, - FAST_READ = 0xb, - DOR = 0x3b, - QOR = 0x6b, - DIOR = 0xbb, - QIOR = 0xeb, - - PP = 0x2, - DPP = 0xa2, - QPP = 0x32, -} FlashCMD; - -typedef struct { - XilinxSPIPS parent_obj; - - uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; - hwaddr lqspi_cached_addr; - Error *migration_blocker; - bool mmio_execution_enabled; -} XilinxQSPIPS; - -typedef struct XilinxSPIPSClass { - SysBusDeviceClass parent_class; - - const MemoryRegionOps *reg_ops; - - uint32_t rx_fifo_size; - uint32_t tx_fifo_size; -} XilinxSPIPSClass; static inline int num_effective_busses(XilinxSPIPS *s) { diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index 06aa096..7f9e2fc 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -32,6 +32,22 @@ typedef struct XilinxSPIPS XilinxSPIPS; #define XLNX_SPIPS_R_MAX (0x100 / 4) +/* Bite off 4k chunks at a time */ +#define LQSPI_CACHE_SIZE 1024 + +typedef enum { + READ = 0x3, READ_4 = 0x13, + FAST_READ = 0xb, FAST_READ_4 = 0x0c, + DOR = 0x3b, DOR_4 = 0x3c, + QOR = 0x6b, QOR_4 = 0x6c, + DIOR = 0xbb, DIOR_4 = 0xbc, + QIOR = 0xeb, QIOR_4 = 0xec, + + PP = 0x2, PP_4 = 0x12, + DPP = 0xa2, + QPP = 0x32, QPP_4 = 0x34, +} FlashCMD; + struct XilinxSPIPS { SysBusDevice parent_obj; @@ -56,6 +72,24 @@ struct XilinxSPIPS { uint32_t regs[XLNX_SPIPS_R_MAX]; }; +typedef struct { + XilinxSPIPS parent_obj; + + uint8_t lqspi_buf[LQSPI_CACHE_SIZE]; + hwaddr lqspi_cached_addr; + Error *migration_blocker; + bool mmio_execution_enabled; +} XilinxQSPIPS; + +typedef struct XilinxSPIPSClass { + SysBusDeviceClass parent_class; + + const MemoryRegionOps *reg_ops; + + uint32_t rx_fifo_size; + uint32_t tx_fifo_size; +} XilinxSPIPSClass; + #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" From patchwork Sat Oct 21 21:54:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 828981 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; 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[83.254.152.225]) by smtp.gmail.com with ESMTPSA id q87sm731173lfg.35.2017.10.21.14.54.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Oct 2017 14:54:31 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sat, 21 Oct 2017 23:54:14 +0200 Message-Id: <20171021215420.19787-7-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171021215420.19787-1-frasse.iglesias@gmail.com> References: <20171021215420.19787-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 X-Mailman-Approved-At: Sat, 21 Oct 2017 21:15:25 -0400 Subject: [Qemu-devel] [PATCH v2 06/12] xilinx_spips: Update striping to be big-endian bit order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Update striping functionality to be big-endian bit order and output even bits into lower memory and odd bits into upper. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 93b9e43..d052fc6 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -209,14 +209,14 @@ static void xilinx_spips_reset(DeviceState *d) xilinx_spips_update_cs_lines(s); } -/* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB) +/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: * Each digit in the below array is a single bit (num == 3): * - * {{ 76543210, } ----- stripe (dir == false) -----> {{ FCheb630, } - * { hgfedcba, } { GDAfc741, } - * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { HEBgda52, }} + * {{ 76543210, } ----- stripe (dir == false) -----> {{ 741gdaFC, } + * { hgfedcba, } { 630fcHEB, } + * { HGFEDCBA, }} <---- upstripe (dir == true) ----- { 52hebGDA, }} */ static inline void stripe8(uint8_t *x, int num, bool dir) @@ -224,15 +224,15 @@ static inline void stripe8(uint8_t *x, int num, bool dir) uint8_t r[num]; memset(r, 0, sizeof(uint8_t) * num); int idx[2] = {0, 0}; - int bit[2] = {0, 0}; + int bit[2] = {0, 7}; int d = dir; for (idx[0] = 0; idx[0] < num; ++idx[0]) { - for (bit[0] = 0; bit[0] < 8; ++bit[0]) { - r[idx[d]] |= x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0; + for (bit[0] = 7; bit[0] != -1; bit[0] += -1) { + r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; idx[1] = (idx[1] + 1) % num; if (!idx[1]) { - bit[1]++; + bit[1] += -1; } } } @@ -267,8 +267,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } for (i = 0; i < num_effective_busses(s); ++i) { + int bus = num_effective_busses(s) - 1 - i; DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]); - tx_rx[i] = ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]); + tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]); DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]); } From patchwork Sat Oct 21 21:54:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 828986 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="jImdW+S4"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yKMGD6v0pz9sxR for ; Sun, 22 Oct 2017 12:22:28 +1100 (AEDT) Received: from localhost ([::1]:59733 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e64yA-0002G3-W3 for incoming@patchwork.ozlabs.org; Sat, 21 Oct 2017 21:22:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47619) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e61j3-0000Pg-UN for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e61j2-0002ao-Ma for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:37 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:48031) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e61j2-0002WJ-As for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:36 -0400 Received: by mail-lf0-x241.google.com with SMTP id k40so16444230lfi.4 for ; Sat, 21 Oct 2017 14:54:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1+aGvSo3KjhfS29Klr8ma/kIS45w4BzZZ4zxSIUUfNk=; b=jImdW+S45WcE2s9nWb7TuzfcCvZAK/Gv2eXArbgBoS/eHRy+d6wMLYpEuTqBdmbsfs w63qasVf+0nT3HEq52dStskYAcIUYkyBcufhtUdZQ53Dgm2keZ6+XFZepTJ3LFo4fkkr WkHduBMssh7G3Jrl6kD/afzsf6Z2uD+3Kxl6jcZdnQBWv98xzJZcW4JmMqwW5IvIf2L8 UGkNBy71Pd6SvNkneWIDc4ea3pSikiU1fidUSLkLslfHY6TUWPsMMICoeDl160MKQhTJ hFG5lYk7GNhmNDWRr1aMNljWtSaqih5DNnJtDrPnSOwWQltzpI7DWSw+lo9y6mUQOAPz sxbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1+aGvSo3KjhfS29Klr8ma/kIS45w4BzZZ4zxSIUUfNk=; b=HOFdCyYf1tY1ANwRxND+ivZW6GIy+DxLB6utWQvyj+JREmBQIBZMhI01VzMhMqGfp+ +XNKJXyrc2FeSlAXJryWND2/oMMVcKfbX5L3q/wneUgBF5WkrAwrqEDaeE2x1Jgh5DwF HGu+OhpBTfiIJxXXVRHAhEbMs218ryWFaz83I3eiNzd9Du+gOtS9UwrJrPRgaG9Ct/i8 fXtJ6wPUIoY3JO7eyhpDyKwr0wiu20ckehMhZF1+r9p8vsYdx2f5pThD5Und/ac3PgHB 0Ld682KKyVMgGYowmbW/e+28mYj+1lwosCa4pvWyvOaCXdlKJxGUw8GhNaaLKzKiD2sL pMfQ== X-Gm-Message-State: AMCzsaUuXqWJyzrKxhVIiHFxnwBM0LU2glIqCCpSDfKoJcE37zso+bnj PJfJp9uebMeUxmuPoAChkse2sQWF X-Google-Smtp-Source: ABhQp+TV5WqdaOPquUquFaGbo/OCL2fMYpbxuzOBzl5SxhqM7YFxctZr8BHe7SyZPWuedbF/R8h4Pg== X-Received: by 10.46.42.194 with SMTP id q185mr3443960ljq.191.1508622874659; Sat, 21 Oct 2017 14:54:34 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id q87sm731173lfg.35.2017.10.21.14.54.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Oct 2017 14:54:33 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sat, 21 Oct 2017 23:54:16 +0200 Message-Id: <20171021215420.19787-9-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171021215420.19787-1-frasse.iglesias@gmail.com> References: <20171021215420.19787-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 X-Mailman-Approved-At: Sat, 21 Oct 2017 21:15:25 -0400 Subject: [Qemu-devel] [PATCH v2 08/12] xilinx_spips: Support configured endiannes of TX/RX registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Input into the transmition fifo (and output from the recieve fifo) according the configured endianess in the configuration register. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 68 ++++++++++++++++++++++++++++++--------------------- 1 file changed, 40 insertions(+), 28 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 946df13..578ff8a 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -47,7 +47,7 @@ /* config register */ #define R_CONFIG (0x00 / 4) #define IFMODE (1U << 31) -#define ENDIAN (1 << 26) +#define R_CONFIG_ENDIAN (1 << 26) #define MODEFAIL_GEN_EN (1 << 17) #define MAN_START_COM (1 << 16) #define MAN_START_EN (1 << 15) @@ -447,13 +447,29 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } } -static inline void rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) +static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be) +{ + int i; + for (i = 0; i < num && !fifo8_is_full(fifo); ++i) { + if (be) { + fifo8_push(fifo, (uint8_t)(value >> 24)); + value <<= 8; + } else { + fifo8_push(fifo, (uint8_t)value); + value >>= 8; + } + } +} + +static inline int rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) { int i; for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) { value[i] = fifo8_pop(&s->rx_fifo); } + + return max - i; } static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, @@ -463,6 +479,9 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, uint32_t mask = ~0; uint32_t ret; uint8_t rx_buf[4]; + int shortfall; + + memset(rx_buf, 0, sizeof(rx_buf)); addr >>= 2; switch (addr) { @@ -473,6 +492,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, ret = s->regs[addr] & IXR_ALL; s->regs[addr] = 0; DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + xilinx_spips_update_ixr(s); return ret; case R_INTR_MASK: mask = IXR_ALL; @@ -493,9 +513,13 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, break; case R_RX_DATA: memset(rx_buf, 0, sizeof(rx_buf)); - rx_data_bytes(s, rx_buf, s->num_txrx_bytes); - ret = s->regs[R_CONFIG] & ENDIAN ? cpu_to_be32(*(uint32_t *)rx_buf) - : cpu_to_le32(*(uint32_t *)rx_buf); + shortfall = rx_data_bytes(s, rx_buf, s->num_txrx_bytes); + ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { + ret <<= 8 * shortfall; + } DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); xilinx_spips_update_ixr(s); return ret; @@ -506,25 +530,12 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, } -static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num) -{ - int i; - for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) { - if (s->regs[R_CONFIG] & ENDIAN) { - fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24)); - value <<= 8; - } else { - fifo8_push(&s->tx_fifo, (uint8_t)value); - value >>= 8; - } - } -} - static void xilinx_spips_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { int mask = ~0; int man_start_com = 0; + int tx_btt = 0; XilinxSPIPS *s = opaque; DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); @@ -560,16 +571,17 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, mask = 0; break; case R_TX_DATA: - tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes); - goto no_reg_update; - case R_TXD1: - tx_data_bytes(s, (uint32_t)value, 1); - goto no_reg_update; - case R_TXD2: - tx_data_bytes(s, (uint32_t)value, 2); + tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; case R_TXD3: - tx_data_bytes(s, (uint32_t)value, 3); + tx_btt++; + case R_TXD2: + tx_btt++; + case R_TXD1: + tx_btt++; + tx_data_bytes(&s->tx_fifo, (uint32_t)value, tx_btt, + s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; } s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); @@ -679,7 +691,7 @@ static void lqspi_load_cache(void *opaque, hwaddr addr) while (cache_entry < LQSPI_CACHE_SIZE) { for (i = 0; i < 64; ++i) { - tx_data_bytes(s, 0, 1); + tx_data_bytes(&s->tx_fifo, 0, 1, false); } xilinx_spips_flush_txfifo(s); for (i = 0; i < 64; ++i) { From patchwork Sat Oct 21 21:54:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 828987 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[83.254.152.225]) by smtp.gmail.com with ESMTPSA id q87sm731173lfg.35.2017.10.21.14.54.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Oct 2017 14:54:36 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sat, 21 Oct 2017 23:54:18 +0200 Message-Id: <20171021215420.19787-11-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171021215420.19787-1-frasse.iglesias@gmail.com> References: <20171021215420.19787-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 X-Mailman-Approved-At: Sat, 21 Oct 2017 21:15:25 -0400 Subject: [Qemu-devel] [PATCH v2 10/12] xilinx_spips: Add support for 4 byte addresses in the LQSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index c858a6c..c360af7 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -92,8 +92,9 @@ #define R_LQSPI_CFG_RESET 0x03A002EB #define LQSPI_CFG_LQ_MODE (1U << 31) #define LQSPI_CFG_TWO_MEM (1 << 30) -#define LQSPI_CFG_SEP_BUS (1 << 30) +#define LQSPI_CFG_SEP_BUS (1 << 29) #define LQSPI_CFG_U_PAGE (1 << 28) +#define LQSPI_CFG_ADDR4 (1 << 27) #define LQSPI_CFG_MODE_EN (1 << 25) #define LQSPI_CFG_MODE_WIDTH 8 #define LQSPI_CFG_MODE_SHIFT 16 @@ -705,6 +706,9 @@ static void lqspi_load_cache(void *opaque, hwaddr addr) fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE); /* read address */ DB_PRINT_L(0, "pushing read address %06x\n", flash_addr); + if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) { + fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24)); + } fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16)); fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8)); fifo8_push(&s->tx_fifo, (uint8_t)flash_addr); From patchwork Sat Oct 21 21:54:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 828985 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="oR3dgdrP"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yKMFf0t3Xz9sBW for ; Sun, 22 Oct 2017 12:21:58 +1100 (AEDT) Received: from localhost ([::1]:59731 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e64xg-0001qa-5Y for incoming@patchwork.ozlabs.org; Sat, 21 Oct 2017 21:21:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47762) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e61jA-0000R9-Mk for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e61j7-0002sk-3K for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:44 -0400 Received: from mail-lf0-x243.google.com ([2a00:1450:4010:c07::243]:54760) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e61j6-0002o0-KQ for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:41 -0400 Received: by mail-lf0-x243.google.com with SMTP id d10so16435636lfg.11 for ; Sat, 21 Oct 2017 14:54:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C22UntMYHIeA5NRXvJha9qI10won+o14BqjveKY/jS4=; b=oR3dgdrPok/iy0ksGg3Uef+vuj8vGMQ7cRrvQOqjKO17eTInoOyvdJsopfcvNu8wD6 h2FObBw3KmvXh6iTRyb6LBtAvscEzZeRISdlu/Hi+SIAmyJWiOMe/cP/iSY/SHOU935K Q6oPzQc9eFq4YY7qF2KLMfX4sVepmNPwF7pYBHjgbqpjjngOcSfr6F0uFA3s/reHCOIz a4zqbm1+RyW1/SwytHy6mPoI9iCgIRVe2N86xmLCMhLDw1xoDu5iq5ADTMe36lmJqJgB kt0BM5NWqe5oOjDqEaV8VFbcVdOILQRwsXvwwwk1IVFlWNSoN/LRBWLo/hUCzMHeQ2Dr I+sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C22UntMYHIeA5NRXvJha9qI10won+o14BqjveKY/jS4=; b=f33RWCP8FO/SjJf/aqClXLrFeQSAn77FAjPeg7d9TUoIBLGWl1ofgffh3r9rvAbSJB 4fdlnTuRLXoyeU3sIhV+lwbX75bK8SpAz0Gqs3wH/ny+T7ZIcN/wtVyvwZnS2zC64ZKt pfwzadKZ3TnSMsGRjPTqz7Lm7NSnx3O33XWG3AKHpqJiRLz8ldZOHzsm0jeaBDv7yTgv rZKEHUmvvmBgrO6g3+EADAkUryfhC46Hm4Tk9rsRncIHsE7W32W0Im13UJTtNEffdHI4 Tx910vWDTc+VXWIMqMiUj4JRW/aZtrAo815jH1wqnBqT4W4h1meqO1osHCiZieKZ0uqa 9S5A== X-Gm-Message-State: AMCzsaUfMa6pXf1pMM+n8iPz9ovSqpdxcFZBy8ZvCKA8udXVGlA83Fce knhKwq9GZ5hlqNfw65Tot2DOUU07 X-Google-Smtp-Source: ABhQp+Qb4aOcjmExv4LIIaoo/K/pPh4h8x8hGb3m1WQzdbwwUD52nAxTLE4R60Ps0hhyYDwy9J38vQ== X-Received: by 10.46.64.135 with SMTP id r7mr3908056lje.111.1508622878694; Sat, 21 Oct 2017 14:54:38 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id q87sm731173lfg.35.2017.10.21.14.54.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Oct 2017 14:54:37 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sat, 21 Oct 2017 23:54:19 +0200 Message-Id: <20171021215420.19787-12-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171021215420.19787-1-frasse.iglesias@gmail.com> References: <20171021215420.19787-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::243 X-Mailman-Approved-At: Sat, 21 Oct 2017 21:15:25 -0400 Subject: [Qemu-devel] [PATCH v2 11/12] xilinx_spips: Add support for the ZynqMP Generic QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for the Zynq Ultrascale MPSoc Generic QSPI. Signed-off-by: Francisco Iglesias --- default-configs/arm-softmmu.mak | 1 + hw/ssi/xilinx_spips.c | 510 ++++++++++++++++++++++++++++++++++++---- include/hw/ssi/xilinx_spips.h | 31 ++- 3 files changed, 494 insertions(+), 48 deletions(-) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 5059d13..d09fd34 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -130,3 +130,4 @@ CONFIG_SMBIOS=y CONFIG_ASPEED_SOC=y CONFIG_GPIO_KEY=y CONFIG_MSF2=y +CONFIG_XILINX_AXI=y diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index c360af7..0aaa5c8 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -31,6 +31,7 @@ #include "hw/ssi/xilinx_spips.h" #include "qapi/error.h" #include "hw/register.h" +#include "sysemu/dma.h" #include "migration/blocker.h" #ifndef XILINX_SPIPS_ERR_DEBUG @@ -69,13 +70,31 @@ #define R_INTR_DIS (0x0C / 4) #define R_INTR_MASK (0x10 / 4) #define IXR_TX_FIFO_UNDERFLOW (1 << 6) +/* Poll timeout not implemented */ +#define IXR_RX_FIFO_EMPTY (1 << 11) +#define IXR_GENERIC_FIFO_FULL (1 << 10) +#define IXR_GENERIC_FIFO_NOT_FULL (1 << 9) +#define IXR_TX_FIFO_EMPTY (1 << 8) +#define IXR_GENERIC_FIFO_EMPTY (1 << 7) #define IXR_RX_FIFO_FULL (1 << 5) #define IXR_RX_FIFO_NOT_EMPTY (1 << 4) #define IXR_TX_FIFO_FULL (1 << 3) #define IXR_TX_FIFO_NOT_FULL (1 << 2) #define IXR_TX_FIFO_MODE_FAIL (1 << 1) #define IXR_RX_FIFO_OVERFLOW (1 << 0) -#define IXR_ALL ((IXR_TX_FIFO_UNDERFLOW<<1)-1) +#define IXR_ALL ((1 << 13) - 1) +#define GQSPI_IXR_MASK 0xFBE + +#define IXR_SELF_CLEAR \ +(IXR_GENERIC_FIFO_EMPTY \ +| IXR_GENERIC_FIFO_FULL \ +| IXR_GENERIC_FIFO_NOT_FULL \ +| IXR_TX_FIFO_EMPTY \ +| IXR_TX_FIFO_FULL \ +| IXR_TX_FIFO_NOT_FULL \ +| IXR_RX_FIFO_EMPTY \ +| IXR_RX_FIFO_FULL \ +| IXR_RX_FIFO_NOT_EMPTY) #define R_EN (0x14 / 4) #define R_DELAY (0x18 / 4) @@ -118,9 +137,63 @@ #define R_MOD_ID (0xFC / 4) +#define R_GQSPI_SELECT (0x144 / 4) + FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1) +#define R_GQSPI_ISR (0x104 / 4) +#define R_GQSPI_IER (0x108 / 4) +#define R_GQSPI_IDR (0x10c / 4) +#define R_GQSPI_IMR (0x110 / 4) +#define R_GQSPI_TX_THRESH (0x128 / 4) +#define R_GQSPI_RX_THRESH (0x12c / 4) + +#define R_GQSPI_CNFG (0x100 / 4) + FIELD(GQSPI_CNFG, MODE_EN, 30, 2) + FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1) + FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1) + FIELD(GQSPI_CNFG, ENDIAN, 26, 1) + /* Poll timeout not implemented */ + FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) + /* QEMU doesnt care about any of these last three */ + FIELD(GQSPI_CNFG, BR, 3, 3) + FIELD(GQSPI_CNFG, CPH, 2, 1) + FIELD(GQSPI_CNFG, CPL, 1, 1) + +#define R_GQSPI_GEN_FIFO (0x140 / 4) + +#define R_GQSPI_TXD (0x11c / 4) +#define R_GQSPI_RXD (0x120 / 4) + +#define R_GQSPI_FIFO_CTRL (0x14c / 4) + FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1) + FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1) + FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) + +#define R_GQSPI_GFIFO_THRESH (0x150 / 4) + +#define R_GQSPI_DATA_STS (0x15c / 4) + +/* We use the snapshot register to hold the core state for the currently + * or most recently executed command. So the generic fifo format is defined + * for the snapshot register + */ +#define R_GQSPI_GF_SNAPSHOT (0x160 / 4) + FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1) + FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1) + FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1) + FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2) + FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2) + FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2) + FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1) + FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1) + FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8) + +#define R_GQSPI_MOD_ID (0x168 / 4) +#define R_GQSPI_MOD_ID_VALUE 0x010A0000 + /* size of TXRX FIFOs */ -#define RXFF_A 32 -#define TXFF_A 32 +#define RXFF_A (128) +#define TXFF_A (128) #define RXFF_A_Q (64 * 4) #define TXFF_A_Q (64 * 4) @@ -133,6 +206,7 @@ #define SNOOP_NONE 0xEE #define SNOOP_STRIPING 0 +#define ZYNQMP_ONLY(a) ((zynqmp) ? (a) : (0)) static inline int num_effective_busses(XilinxSPIPS *s) { @@ -140,37 +214,61 @@ static inline int num_effective_busses(XilinxSPIPS *s) s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; } -static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field) -{ - return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS - || !fifo8_is_empty(&s->tx_fifo)); +static void xilinx_spips_update_cs_lines_legacy_mangle(XilinxSPIPS *s, + int *field) { + *field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT); + /* In dual parallel, mirror low CS to both */ + if (num_effective_busses(s) == 2) { + /* Single bit chip-select for qspi */ + *field &= 0x1; + *field |= *field << 1; + /* Dual stack U-Page */ + } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM && + s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) { + /* Single bit chip-select for qspi */ + *field &= 0x1; + /* change from CS0 to CS1 */ + *field <<= 1; + } + /* Auto CS */ + if (!(s->regs[R_CONFIG] & MANUAL_CS) && + fifo8_is_empty(&s->tx_fifo)) { + *field = 0; + } +} + +static void xilinx_spips_update_cs_lines_generic_mangle(XilinxSPIPS *s, + int *field) { + *field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT); } static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) { - int i, j; - bool found = false; - int field = s->regs[R_CONFIG] >> CS_SHIFT; + int i; + int field = 0; - for (i = 0; i < s->num_cs; i++) { - for (j = 0; j < num_effective_busses(s); j++) { - int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE); - int cs_to_set = (j * s->num_cs + i + upage) % - (s->num_cs * s->num_busses); - - if (xilinx_spips_cs_is_set(s, i, field) && !found) { - DB_PRINT_L(0, "selecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 0); - } else { - DB_PRINT_L(0, "deselecting slave %d\n", i); - qemu_set_irq(s->cs_lines[cs_to_set], 1); - } + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + xilinx_spips_update_cs_lines_legacy_mangle(s, &field); + } else { + if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { + return; } - if (xilinx_spips_cs_is_set(s, i, field)) { - found = true; + xilinx_spips_update_cs_lines_generic_mangle(s, &field); + } + + for (i = 0; i < s->num_cs; i++) { + bool old_state = s->cs_lines_state[i]; + bool new_state = field & (1 << i); + + if (old_state != new_state) { + s->cs_lines_state[i] = new_state; + s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); + DB_PRINT_L(0, "%sselecting slave %d\n", new_state ? "" : "de", i); } + qemu_set_irq(s->cs_lines[i], !new_state); } - if (!found) { + + if (!(field & ((1 << s->num_cs) - 1))) { s->snoop_state = SNOOP_CHECKING; s->cmd_dummies = 0; s->link_state = 1; @@ -182,22 +280,53 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s) static void xilinx_spips_update_ixr(XilinxSPIPS *s) { - if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) { - return; + int new_irqline; + uint32_t qspi_int, gqspi_int; + bool zynqmp = false; + + if (object_dynamic_cast(OBJECT(s), TYPE_XLNX_ZYNQMP_QSPIPS)) { + zynqmp = true; } - /* These are set/cleared as they occur */ - s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW | - IXR_TX_FIFO_MODE_FAIL); + /* these are pure functions of fifo state, set them here */ - s->regs[R_INTR_STATUS] |= - (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | - (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) | - (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | - (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); + s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR; + s->regs[R_GQSPI_ISR] |= + (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) | + (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) | + (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ? + IXR_GENERIC_FIFO_NOT_FULL : 0) | + + (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + + (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) | + (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ? + IXR_TX_FIFO_NOT_FULL : 0); + + if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { + s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR; + s->regs[R_INTR_STATUS] |= + (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) | + (s->rx_fifo.num >= s->regs[R_RX_THRES] ? + IXR_RX_FIFO_NOT_EMPTY : 0) | + ZYNQMP_ONLY(fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | + (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | + (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); + } + + /* QSPI/SPI Interrupt Trigger Status */ + qspi_int = s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS]; + /* GQSPI Interrupt Trigger Status */ + gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & + GQSPI_IXR_MASK; /* drive external interrupt pin */ - int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] & - IXR_ALL); + new_irqline = !!((qspi_int | gqspi_int) & IXR_ALL); if (new_irqline != s->irqline) { + DB_PRINT_L(0, "IRQ state is changing %" PRIx32 " -> %" PRIx32 "\n", + s->irqline, new_irqline); s->irqline = new_irqline; qemu_set_irq(s->irq, s->irqline); } @@ -214,11 +343,18 @@ static void xilinx_spips_reset(DeviceState *d) fifo8_reset(&s->rx_fifo); fifo8_reset(&s->rx_fifo); + fifo8_reset(&s->rx_fifo_g); + fifo8_reset(&s->rx_fifo_g); + fifo32_reset(&s->fifo_g); /* non zero resets */ s->regs[R_CONFIG] |= MODEFAIL_GEN_EN; s->regs[R_SLAVE_IDLE_COUNT] = 0xFF; s->regs[R_TX_THRES] = 1; s->regs[R_RX_THRES] = 1; + s->regs[R_GQSPI_TX_THRESH] = 1; + s->regs[R_GQSPI_RX_THRESH] = 1; + s->regs[R_GQSPI_GFIFO_THRESH] = 1; + s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK; /* FIXME: move magic number definition somewhere sensible */ s->regs[R_MOD_ID] = 0x01090106; s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET; @@ -228,6 +364,7 @@ static void xilinx_spips_reset(DeviceState *d) s->snoop_state = SNOOP_CHECKING; s->cmd_dummies = 0; s->man_start_com = false; + s->man_start_com_g = false; xilinx_spips_update_ixr(s); xilinx_spips_update_cs_lines(s); } @@ -262,6 +399,141 @@ static inline void stripe8(uint8_t *x, int num, bool dir) memcpy(x, r, sizeof(uint8_t) * num); } +static void xilinx_spips_flush_fifo_g(XilinxSPIPS *s) +{ + while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) { + uint8_t tx_rx[2]; + int num_stripes; + int i; + uint8_t busses; + + /* memset() get's optimised out and results in the kernel seeing bogus + * data and complaining. So until memset_s() is supported let's just do + * it like this. + */ + memset(tx_rx, 0, sizeof(tx_rx)); + i = tx_rx[0]; + i += tx_rx[1]; + + if (!s->regs[R_GQSPI_DATA_STS]) { + uint8_t imm; + + s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g); + DB_PRINT_L(0, "Popped GQSPI command %" PRIx32 "\n", + s->regs[R_GQSPI_GF_SNAPSHOT]); + if (!s->regs[R_GQSPI_GF_SNAPSHOT]) { + DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing"); + continue; + } + xilinx_spips_update_cs_lines(s); + + imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + /* immedate transfer */ + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) || + ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { + s->regs[R_GQSPI_DATA_STS] = 1; + /* CS setup/hold - do nothing */ + } else { + s->regs[R_GQSPI_DATA_STS] = 0; + } + /* exponential transfer */ + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) { + if (imm > 31) { + qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too" + " long - 2 ^ %" PRId8 " requested\n", imm); + } + s->regs[R_GQSPI_DATA_STS] = 1ul << imm; + /* non-exponential data transfer */ + } else { + s->regs[R_GQSPI_DATA_STS] = imm; + } + } + + /* Zero length transfer? no thanks! */ + if (!s->regs[R_GQSPI_DATA_STS]) { + continue; + } + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) && + fifo8_is_full(&s->rx_fifo_g)) { + /* No space in RX fifo for transfer - try again later */ + return; + } + + num_stripes = ARRAY_FIELD_EX32(s->regs, + GQSPI_GF_SNAPSHOT, STRIPE) ? 2 : 1; + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) && + !ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { + num_stripes = 1; + } + + if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { + tx_rx[0] = ARRAY_FIELD_EX32(s->regs, + GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA); + } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) { + for (i = 0; i < num_stripes; ++i) { + if (!fifo8_is_empty(&s->tx_fifo_g)) { + tx_rx[i] = fifo8_pop(&s->tx_fifo_g); + s->tx_fifo_g_align++; + } else { + return; + } + } + } + if (num_stripes == 1) { + /* mirror */ + for (i = 1; i < 2; ++i) { + tx_rx[i] = tx_rx[0]; + } + } + + busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT); + for (i = 0; i < 2; ++i) { + if (busses & (1 << i)) { + DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]); + } + tx_rx[i] = ssi_transfer(s->spi[i], tx_rx[i]); + if (busses & (1 << i)) { + DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]); + } + } + + switch (busses) { + case 0x3: + if (num_stripes == 2) { + s->regs[R_GQSPI_DATA_STS]--; + } + /* fallthrough */ + default: + if (s->regs[R_GQSPI_DATA_STS] != 0) { + /* Don't let this wrap around */ + s->regs[R_GQSPI_DATA_STS]--; + } + } + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) { + for (i = 0; i < 2; ++i) { + if (busses & (1 << i)) { + DB_PRINT_L(1, "bus %d push_byte = %02x\n", + i, tx_rx[i]); + fifo8_push(&s->rx_fifo_g, tx_rx[i]); + s->rx_fifo_g_align++; + } + } + } + + if (!s->regs[R_GQSPI_DATA_STS]) { + for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) { + fifo8_pop(&s->tx_fifo_g); + } + for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) { + fifo8_push(&s->rx_fifo_g, 0); + } + } + } +} + static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command) { if (!qs) { @@ -327,9 +599,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) uint8_t addr_length; if (fifo8_is_empty(&s->tx_fifo)) { - if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { - s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; - } xilinx_spips_update_ixr(s); return; } else if (s->snoop_state == SNOOP_STRIPING) { @@ -490,16 +759,31 @@ static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) static void xilinx_spips_check_flush(XilinxSPIPS *s) { - if (s->man_start_com || - (!fifo8_is_empty(&s->tx_fifo) && - !(s->regs[R_CONFIG] & MAN_START_EN))) { - xilinx_spips_check_zero_pump(s); - xilinx_spips_flush_txfifo(s); + bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] || + !fifo32_is_empty(&s->fifo_g); + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (s->man_start_com_g || + (gqspi_has_work && + !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) { + xilinx_spips_flush_fifo_g(s); + } + } else { + if (s->man_start_com || + (!fifo8_is_empty(&s->tx_fifo) && + !(s->regs[R_CONFIG] & MAN_START_EN))) { + xilinx_spips_check_zero_pump(s); + xilinx_spips_flush_txfifo(s); + } } if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) { s->man_start_com = false; } + + if (!gqspi_has_work) { + s->man_start_com_g = false; + } xilinx_spips_update_ixr(s); } @@ -514,6 +798,54 @@ static inline int rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max) return max - i; } +static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num) +{ + void *ret; + + if (max == 0 || max > fifo->num) { + abort(); + } + *num = MIN(fifo->capacity - fifo->head, max); + ret = &fifo->data[fifo->head]; + fifo->head += *num; + fifo->head %= fifo->capacity; + fifo->num -= *num; + return ret; +} + +static void xlnx_zynqmp_qspips_notify(void *opaque) +{ + XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque); + XilinxSPIPS *s = XILINX_SPIPS(rq); + Fifo8 *recv_fifo; + + if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) { + if (!(ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, MODE_EN) == 2)) { + return; + } + recv_fifo = &s->rx_fifo_g; + } else { + if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) { + return; + } + recv_fifo = &s->rx_fifo; + } + + while (recv_fifo->num >= 4 + && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq)) + { + size_t ret; + uint32_t num; + const void *rxd = pop_buf(recv_fifo, 4, &num); + + memcpy(rq->dma_buf, rxd, num); + + ret = stream_push(rq->dma, rq->dma_buf, 4); + assert(ret == 4); + xilinx_spips_check_flush(s); + } +} + static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, unsigned size) { @@ -522,6 +854,8 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, uint32_t ret; uint8_t rx_buf[4]; int shortfall; + const void *rxd; + uint32_t rx_num; memset(rx_buf, 0, sizeof(rx_buf)); @@ -563,6 +897,21 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, ret <<= 8 * shortfall; } DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + xilinx_spips_check_flush(s); + xilinx_spips_update_ixr(s); + return ret; + case R_GQSPI_RXD: + if (fifo8_is_empty(&s->rx_fifo_g)) { + qemu_log_mask(LOG_GUEST_ERROR, "Read from empty GQSPI RX FIFO\n"); + return 0; + } + rxd = pop_buf(&s->rx_fifo_g, 4, &rx_num); + assert(!(rx_num % 4)); + memcpy(rx_buf, rxd, rx_num); + ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ? + cpu_to_be32(*(uint32_t *)rx_buf) : + cpu_to_le32(*(uint32_t *)rx_buf); + xilinx_spips_check_flush(s); xilinx_spips_update_ixr(s); return ret; } @@ -624,6 +973,49 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, tx_data_bytes(&s->tx_fifo, (uint32_t)value, tx_btt, s->regs[R_CONFIG] & R_CONFIG_ENDIAN); goto no_reg_update; + case R_GQSPI_CNFG: + mask = ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK); + if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) && + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) { + s->man_start_com_g = true; + } + break; + case R_GQSPI_GEN_FIFO: + if (!fifo32_is_full(&s->fifo_g)) { + fifo32_push(&s->fifo_g, value); + } + goto no_reg_update; + case R_GQSPI_TXD: + tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4, + ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)); + goto no_reg_update; + case R_GQSPI_FIFO_CTRL: + mask = 0; + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) { + fifo32_reset(&s->fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) { + fifo8_reset(&s->tx_fifo_g); + } + if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) { + fifo8_reset(&s->rx_fifo_g); + } + break; + case R_GQSPI_IDR: + s->regs[R_GQSPI_IMR] |= value; + goto no_reg_update; + case R_GQSPI_IER: + s->regs[R_GQSPI_IMR] &= ~value; + goto no_reg_update; + case R_GQSPI_ISR: + s->regs[R_GQSPI_ISR] &= ~value; + goto no_reg_update; + case R_GQSPI_IMR: + case R_GQSPI_RXD: + case R_GQSPI_GF_SNAPSHOT: + case R_GQSPI_MOD_ID: + mask = 0; + break; } s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); no_reg_update: @@ -667,6 +1059,9 @@ static void xilinx_qspips_write(void *opaque, hwaddr addr, if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) { fifo8_reset(&s->rx_fifo); } + if (object_dynamic_cast(OBJECT(s), TYPE_XLNX_ZYNQMP_QSPIPS)) { + xlnx_zynqmp_qspips_notify(s); + } } static const MemoryRegionOps qspips_ops = { @@ -812,6 +1207,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) } s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses); + s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses); for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) { ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]); } @@ -829,6 +1225,9 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) fifo8_create(&s->rx_fifo, xsc->rx_fifo_size); fifo8_create(&s->tx_fifo, xsc->tx_fifo_size); + fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size); + fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size); + fifo32_create(&s->fifo_g, 32); } static void xilinx_qspips_realize(DeviceState *dev, Error **errp) @@ -860,6 +1259,17 @@ static void xilinx_qspips_realize(DeviceState *dev, Error **errp) } } +static void xlnx_zynqmp_qspips_init(Object *obj) +{ + XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj); + + object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE, + (Object **)&rq->dma, + object_property_allow_set_link, + OBJ_PROP_LINK_UNREF_ON_RELEASE, + NULL); +} + static int xilinx_spips_post_load(void *opaque, int version_id) { xilinx_spips_update_ixr((XilinxSPIPS *)opaque); @@ -940,10 +1350,18 @@ static const TypeInfo xilinx_qspips_info = { .class_init = xilinx_qspips_class_init, }; +static const TypeInfo xlnx_zynqmp_qspips_info = { + .name = TYPE_XLNX_ZYNQMP_QSPIPS, + .parent = TYPE_XILINX_QSPIPS, + .instance_size = sizeof(XlnxZynqMPQSPIPS), + .instance_init = xlnx_zynqmp_qspips_init, +}; + static void xilinx_spips_register_types(void) { type_register_static(&xilinx_spips_info); type_register_static(&xilinx_qspips_info); + type_register_static(&xlnx_zynqmp_qspips_info); } type_init(xilinx_spips_register_types) diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h index df6e245..ecfeb28 100644 --- a/include/hw/ssi/xilinx_spips.h +++ b/include/hw/ssi/xilinx_spips.h @@ -26,11 +26,12 @@ #define XILINX_SPIPS_H #include "hw/ssi/ssi.h" -#include "qemu/fifo8.h" +#include "qemu/fifo32.h" +#include "hw/stream.h" typedef struct XilinxSPIPS XilinxSPIPS; -#define XLNX_SPIPS_R_MAX (0x100 / 4) +#define XLNX_SPIPS_R_MAX 0x200 /* Bite off 4k chunks at a time */ #define LQSPI_CACHE_SIZE 1024 @@ -66,10 +67,24 @@ struct XilinxSPIPS { uint8_t link_state_next; uint8_t link_state_next_when; qemu_irq *cs_lines; + bool *cs_lines_state; SSIBus **spi; Fifo8 rx_fifo; Fifo8 tx_fifo; + /* GQSPI has seperate tx/rx fifos */ + Fifo8 rx_fifo_g; + Fifo8 tx_fifo_g; + /* + * at the end of each generic command, misaligned extra bytes are discard + * or padded to tx and rx respectively to round it out (and avoid need for + * individual byte access. Since we use byte fifos, keep track of the + * alignment WRT to word access. + */ + uint8_t rx_fifo_g_align; + uint8_t tx_fifo_g_align; + + Fifo32 fifo_g; uint8_t num_txrx_bytes; uint32_t rx_discard; @@ -77,6 +92,7 @@ struct XilinxSPIPS { uint32_t regs[XLNX_SPIPS_R_MAX]; bool man_start_com; + bool man_start_com_g; }; typedef struct { @@ -88,6 +104,13 @@ typedef struct { bool mmio_execution_enabled; } XilinxQSPIPS; +typedef struct { + XilinxQSPIPS parent_obj; + + StreamSlave *dma; + uint8_t dma_buf[4]; +} XlnxZynqMPQSPIPS; + typedef struct XilinxSPIPSClass { SysBusDeviceClass parent_class; @@ -99,6 +122,7 @@ typedef struct XilinxSPIPSClass { #define TYPE_XILINX_SPIPS "xlnx.ps7-spi" #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi" +#define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi" #define XILINX_SPIPS(obj) \ OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS) @@ -110,4 +134,7 @@ typedef struct XilinxSPIPSClass { #define XILINX_QSPIPS(obj) \ OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS) +#define XLNX_ZYNQMP_QSPIPS(obj) \ + OBJECT_CHECK(XlnxZynqMPQSPIPS, (obj), TYPE_XLNX_ZYNQMP_QSPIPS) + #endif /* XILINX_SPIPS_H */ From patchwork Sat Oct 21 21:54:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Francisco Iglesias X-Patchwork-Id: 828988 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="qGDAqJY0"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yKMJk6m3Nz9sxR for ; Sun, 22 Oct 2017 12:24:38 +1100 (AEDT) Received: from localhost ([::1]:59743 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e650H-0004gB-3t for incoming@patchwork.ozlabs.org; Sat, 21 Oct 2017 21:24:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47751) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e61j9-0000Qw-Fy for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e61j7-0002we-T0 for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:43 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:53846) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e61j7-0002s1-MA for qemu-devel@nongnu.org; Sat, 21 Oct 2017 17:54:41 -0400 Received: by mail-lf0-x241.google.com with SMTP id l23so16439241lfk.10 for ; Sat, 21 Oct 2017 14:54:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TTmqqUQFOQVH1O/NMrz2I/mu9U5GfUrEmp4aSR6uufM=; b=qGDAqJY0bfQkgRI9Cu5RWAv7JF+LZs0VySl/rbSBAuQ67YYV6JTQyf/RovDDfDQNNU ZsdtBW8MBq2XmpBvj+22ZYZUjEIQpd+qk37Y0DSFFdrOn0mMwP5AeCUn4HmLXsaCHh9b b5L5e0LjzPqvzabQ1YPMgXi/6Jmh6qMTlunx9Zwrqk99uB9l8Cophz1vcBk49NlKp0AQ f32iT0qCQysIOfEUoBP2W64RTippV4s0h9b0/tYz8xsaBceHOAuAdVYqvBm0f8OeTVnU bb7rb8TrG2hD08aIRGmAdJVund3vAPX2vY7YP2dat0HV4SALkFtuvHZ8gFzSNU4dn3cP 4xeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TTmqqUQFOQVH1O/NMrz2I/mu9U5GfUrEmp4aSR6uufM=; b=WQSf9z/3neH8xvGK9wlx1AOU3dO0TeHM4faBxbPRz2ULr258hNSg+SEpLq+gJgYEju +fnFHkxH6+7fR5/cvYSo27SO2sKj65xUkomLKrVeujonk0qMGYqOsVEKx+xscnhTspO2 BeZfow4SQguuD+Qjm4MV1ApftttvnF5a8vhSR/KHccGzikiogekCf6ijm0MDTiEKOTE/ dDe5aD786soum5KZUte+yyK/4lMKL12AzZvOFCC0A/YmLMVRTQVkMMVPJ6bgfbTLavNZ w7z3G7YBpMJQ6Nv2Nkvg2XtKYESVi0/K2ZFuFKXhov03bdvEJqwYA0Iih/tIhpILMNnM adDg== X-Gm-Message-State: AMCzsaUWPrF+Q8CvCvGfU9nyr5SQvCYsuT989UotT/ohBgZTCRmHywyy toUL5DBF64yLpc6ZR6A1b6o2pOhV X-Google-Smtp-Source: ABhQp+Tpwk3QAhTejA0n8e2cLbExlbiBpd5IqoV3fwQI/CqfcGLeusqP1GUChslabQZM4Ug5v2TtPg== X-Received: by 10.25.16.42 with SMTP id f42mr2975776lfi.172.1508622880079; Sat, 21 Oct 2017 14:54:40 -0700 (PDT) Received: from localhost.localdomain (c83-254-152-225.bredband.comhem.se. [83.254.152.225]) by smtp.gmail.com with ESMTPSA id q87sm731173lfg.35.2017.10.21.14.54.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Oct 2017 14:54:39 -0700 (PDT) From: Francisco Iglesias To: qemu-devel@nongnu.org Date: Sat, 21 Oct 2017 23:54:20 +0200 Message-Id: <20171021215420.19787-13-frasse.iglesias@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171021215420.19787-1-frasse.iglesias@gmail.com> References: <20171021215420.19787-1-frasse.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 X-Mailman-Approved-At: Sat, 21 Oct 2017 21:15:25 -0400 Subject: [Qemu-devel] [PATCH v2 12/12] xlnx-zcu102: Add support for the ZynqMP QSPI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add support for the ZynqMP QSPI and connect Numonyx n25q512a11 flashes to it. Signed-off-by: Francisco Iglesias --- hw/arm/xlnx-zcu102.c | 23 +++++++++++++++++++++++ hw/arm/xlnx-zynqmp.c | 24 ++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 5 +++++ 3 files changed, 52 insertions(+) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 519a16e..7d61972 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -150,6 +150,29 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line); } + for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) { + SSIBus *spi_bus; + DeviceState *flash_dev; + qemu_irq cs_line; + DriveInfo *dinfo = drive_get_next(IF_MTD); + int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS; + gchar *bus_name = g_strdup_printf("qspi%d", bus); + + spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name); + g_free(bus_name); + + flash_dev = ssi_create_slave_no_init(spi_bus, "n25q512a11"); + if (dinfo) { + qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + qdev_init_nofail(flash_dev); + + cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line); + } + /* TODO create and connect IDE devices for ide_drive_get() */ xlnx_zcu102_binfo.ram_size = ram_size; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index d4b6560..f7c8b4b 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -40,6 +40,10 @@ #define SATA_ADDR 0xFD0C0000 #define SATA_NUM_PORTS 2 +#define QSPI_ADDR 0xff0f0000 +#define LQSPI_ADDR 0xc0000000 +#define QSPI_IRQ 15 + #define DP_ADDR 0xfd4a0000 #define DP_IRQ 113 @@ -169,6 +173,9 @@ static void xlnx_zynqmp_init(Object *obj) qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); } + object_initialize(&s->qspi, sizeof(s->qspi), TYPE_XLNX_ZYNQMP_QSPIPS); + qdev_set_parent_bus(DEVICE(&s->qspi), sysbus_get_default()); + object_initialize(&s->dp, sizeof(s->dp), TYPE_XLNX_DP); qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default()); @@ -405,6 +412,23 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) g_free(bus_name); } + object_property_set_bool(OBJECT(&s->qspi), true, "realized", &err); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 0, QSPI_ADDR); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->qspi), 1, LQSPI_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi), 0, gic_spi[QSPI_IRQ]); + for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_BUS; i++) { + gchar *bus_name; + gchar *target_bus; + /* Alias controller SPI bus to the SoC itself */ + bus_name = g_strdup_printf("qspi%d", i); + target_bus = g_strdup_printf("spi%d", i); + object_property_add_alias(OBJECT(s), bus_name, + OBJECT(&s->qspi), target_bus, + &error_abort); + g_free(bus_name); + g_free(target_bus); + } + object_property_set_bool(OBJECT(&s->dp), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6eff81a..3e6fb9b 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -40,6 +40,10 @@ #define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SPIS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS 2 +#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 +#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 + #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 @@ -83,6 +87,7 @@ typedef struct XlnxZynqMPState { SysbusAHCIState sata; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; + XlnxZynqMPQSPIPS qspi; XlnxDPState dp; XlnxDPDMAState dpdma;