From patchwork Sat Feb 23 00:20:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 1047209 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496924-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="iLA/T6hR"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 445plp71jkz9s9L for ; Sat, 23 Feb 2019 11:21:09 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type; q=dns; s=default; b=AHaz5Att18g6AjUUj6DLnt2asd3Oo Psn9E/0QmAa8CZpQt7tlWA3zsld3i/jtEKFP+obk1tM31Dx663avm043vYq3ZX0y wZ0YdcdGhoF9AaHuasqg0/Irw0y2hoTDW2wH0xFIyuOYMzcIS4Vm/MoRMe804nNK 63/jrL5bRR6xPo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type; s=default; bh=//igTTJqwbUgbeIh93/UYzXKTKo=; b=iLA /T6hRfLIpAlIup3sY9RYnWqDcW6zDZvjZDy2mOIBt4uBOFI86U7WCWFXGDu78kyN AtvklKu1fik9fDOAMtg7/OhZzNbWXZAOb+1ZjvOwCt3lt0qagpbw3vQKVfiqgvZd qyDhfFbkyJLfCdt2Gc/sIwSQWu1N/LJZq+ZLc8zA= Received: (qmail 76531 invoked by alias); 23 Feb 2019 00:21:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 76424 invoked by uid 89); 23 Feb 2019 00:20:59 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, SPF_HELO_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 23 Feb 2019 00:20:57 +0000 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0261881F25; Sat, 23 Feb 2019 00:20:56 +0000 (UTC) Received: from tucnak.zalov.cz (ovpn-117-64.ams2.redhat.com [10.36.117.64]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 837505C204; Sat, 23 Feb 2019 00:20:55 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.15.2/8.15.2) with ESMTP id x1N0KrYL009498; Sat, 23 Feb 2019 01:20:53 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.15.2/8.15.2/Submit) id x1N0KpWB009497; Sat, 23 Feb 2019 01:20:51 +0100 Date: Sat, 23 Feb 2019 01:20:51 +0100 From: Jakub Jelinek To: Richard Earnshaw , Ramana Radhakrishnan , Kyrylo Tkachov , James Greenhalgh Cc: gcc-patches@gcc.gnu.org Subject: [PATCH] Improve arm and aarch64 casesi (PR target/70341) Message-ID: <20190223002051.GL7611@tucnak> Reply-To: Jakub Jelinek MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) X-IsSubscribed: yes Hi! The testcase in the PR doesn't hoist any memory loads from the large switch before the switch on aarch64 and arm (unlike e.g. x86), because the arm/aarch64 casesi patterns don't properly annotate the memory load from the jump table. It is created by gen_* and in RTL directly one can't specify the needed flags (MEM_READONLY_P and MEM_NOTRAP_P). Fixed thusly, bootstrapped/regtested on armv7hl-linux-gnueabi and aarch64-linux, ok for trunk? 2019-02-23 Jakub Jelinek PR target/70341 * config/arm/arm.md (arm_casesi_internal): New define_expand. Rename old define_insn to ... (*arm_casesi_internal): ... this. Add mode to LABEL_REFs. * config/arm/thumb2.md (thumb2_casesi_internal): New define_expand. Rename old define_insn to ... (*thumb2_casesi_internal): ... this. Add mode to LABEL_REFs. (thumb2_casesi_internal_pic): New define_expand. Rename old define_insn to ... (*thumb2_casesi_internal_pic): ... this. Add mode to LABEL_REFs. * config/aarch64/aarch64.md (casesi): Create the casesi_dispatch MEM manually here, set MEM_READONLY_P and MEM_NOTRAP_P on it. Jakub --- gcc/config/arm/arm.md.jj 2019-02-18 20:48:32.643732307 +0100 +++ gcc/config/arm/arm.md 2019-02-21 14:40:50.603452028 +0100 @@ -8914,16 +8914,35 @@ (define_expand "casesi" ;; The USE in this pattern is needed to tell flow analysis that this is ;; a CASESI insn. It has no other purpose. -(define_insn "arm_casesi_internal" +(define_expand "arm_casesi_internal" + [(parallel [(set (pc) + (if_then_else + (leu (match_operand:SI 0 "s_register_operand") + (match_operand:SI 1 "arm_rhs_operand")) + (match_dup 4) + (label_ref:SI (match_operand 3 "")))) + (clobber (reg:CC CC_REGNUM)) + (use (label_ref:SI (match_operand 2 "")))])] + "TARGET_ARM" +{ + operands[4] = gen_rtx_MULT (SImode, operands[0], GEN_INT (4)); + operands[4] = gen_rtx_PLUS (SImode, operands[4], + gen_rtx_LABEL_REF (SImode, operands[2])); + operands[4] = gen_rtx_MEM (SImode, operands[4]); + MEM_READONLY_P (operands[4]) = 1; + MEM_NOTRAP_P (operands[4]) = 1; +}) + +(define_insn "*arm_casesi_internal" [(parallel [(set (pc) (if_then_else (leu (match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "arm_rhs_operand" "rI")) (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4)) - (label_ref (match_operand 2 "" "")))) - (label_ref (match_operand 3 "" "")))) + (label_ref:SI (match_operand 2 "" "")))) + (label_ref:SI (match_operand 3 "" "")))) (clobber (reg:CC CC_REGNUM)) - (use (label_ref (match_dup 2)))])] + (use (label_ref:SI (match_dup 2)))])] "TARGET_ARM" "* if (flag_pic) --- gcc/config/arm/thumb2.md.jj 2019-01-01 12:37:28.280792453 +0100 +++ gcc/config/arm/thumb2.md 2019-02-21 15:00:26.811137210 +0100 @@ -1079,17 +1079,37 @@ (define_insn "thumb2_zero_extendqisi2_v6 (set_attr "neg_pool_range" "*,250")] ) -(define_insn "thumb2_casesi_internal" +(define_expand "thumb2_casesi_internal" + [(parallel [(set (pc) + (if_then_else + (leu (match_operand:SI 0 "s_register_operand") + (match_operand:SI 1 "arm_rhs_operand")) + (match_dup 4) + (label_ref:SI (match_operand 3 "")))) + (clobber (reg:CC CC_REGNUM)) + (clobber (match_scratch:SI 5)) + (use (label_ref:SI (match_operand 2 "")))])] + "TARGET_THUMB2 && !flag_pic" +{ + operands[4] = gen_rtx_MULT (SImode, operands[0], GEN_INT (4)); + operands[4] = gen_rtx_PLUS (SImode, operands[4], + gen_rtx_LABEL_REF (SImode, operands[2])); + operands[4] = gen_rtx_MEM (SImode, operands[4]); + MEM_READONLY_P (operands[4]) = 1; + MEM_NOTRAP_P (operands[4]) = 1; +}) + +(define_insn "*thumb2_casesi_internal" [(parallel [(set (pc) (if_then_else (leu (match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "arm_rhs_operand" "rI")) (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4)) - (label_ref (match_operand 2 "" "")))) - (label_ref (match_operand 3 "" "")))) + (label_ref:SI (match_operand 2 "" "")))) + (label_ref:SI (match_operand 3 "" "")))) (clobber (reg:CC CC_REGNUM)) (clobber (match_scratch:SI 4 "=&r")) - (use (label_ref (match_dup 2)))])] + (use (label_ref:SI (match_dup 2)))])] "TARGET_THUMB2 && !flag_pic" "* return thumb2_output_casesi(operands);" [(set_attr "conds" "clob") @@ -1097,18 +1117,39 @@ (define_insn "thumb2_casesi_internal" (set_attr "type" "multiple")] ) -(define_insn "thumb2_casesi_internal_pic" +(define_expand "thumb2_casesi_internal_pic" + [(parallel [(set (pc) + (if_then_else + (leu (match_operand:SI 0 "s_register_operand") + (match_operand:SI 1 "arm_rhs_operand")) + (match_dup 4) + (label_ref:SI (match_operand 3 "")))) + (clobber (reg:CC CC_REGNUM)) + (clobber (match_scratch:SI 5)) + (clobber (match_scratch:SI 6)) + (use (label_ref:SI (match_operand 2 "")))])] + "TARGET_THUMB2 && flag_pic" +{ + operands[4] = gen_rtx_MULT (SImode, operands[0], GEN_INT (4)); + operands[4] = gen_rtx_PLUS (SImode, operands[4], + gen_rtx_LABEL_REF (SImode, operands[2])); + operands[4] = gen_rtx_MEM (SImode, operands[4]); + MEM_READONLY_P (operands[4]) = 1; + MEM_NOTRAP_P (operands[4]) = 1; +}) + +(define_insn "*thumb2_casesi_internal_pic" [(parallel [(set (pc) (if_then_else (leu (match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "arm_rhs_operand" "rI")) (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4)) - (label_ref (match_operand 2 "" "")))) - (label_ref (match_operand 3 "" "")))) + (label_ref:SI (match_operand 2 "" "")))) + (label_ref:SI (match_operand 3 "" "")))) (clobber (reg:CC CC_REGNUM)) (clobber (match_scratch:SI 4 "=&r")) (clobber (match_scratch:SI 5 "=r")) - (use (label_ref (match_dup 2)))])] + (use (label_ref:SI (match_dup 2)))])] "TARGET_THUMB2 && flag_pic" "* return thumb2_output_casesi(operands);" [(set_attr "conds" "clob") --- gcc/config/aarch64/aarch64.md.jj 2019-01-19 09:39:18.847831222 +0100 +++ gcc/config/aarch64/aarch64.md 2019-02-21 15:25:27.874532191 +0100 @@ -622,13 +622,27 @@ (define_expand "casesi" operands[0], operands[2], operands[4])); operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[3])); - emit_jump_insn (gen_casesi_dispatch (operands[2], operands[0], - operands[3])); + operands[2] + = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, operands[2], operands[0]), + UNSPEC_CASESI); + operands[2] = gen_rtx_MEM (DImode, operands[2]); + MEM_READONLY_P (operands[2]) = 1; + MEM_NOTRAP_P (operands[2]) = 1; + emit_jump_insn (gen_casesi_dispatch (operands[2], operands[3])); DONE; } ) -(define_insn "casesi_dispatch" +(define_expand "casesi_dispatch" + [(parallel + [(set (pc) (match_operand:DI 0 "")) + (clobber (reg:CC CC_REGNUM)) + (clobber (match_scratch:DI 2)) + (clobber (match_scratch:DI 3)) + (use (label_ref:DI (match_operand 1 "")))])] + "") + +(define_insn "*casesi_dispatch" [(parallel [(set (pc) (mem:DI (unspec [(match_operand:DI 0 "register_operand" "r") @@ -637,7 +651,7 @@ (define_insn "casesi_dispatch" (clobber (reg:CC CC_REGNUM)) (clobber (match_scratch:DI 3 "=r")) (clobber (match_scratch:DI 4 "=r")) - (use (label_ref (match_operand 2 "" "")))])] + (use (label_ref:DI (match_operand 2 "" "")))])] "" "* return aarch64_output_casesi (operands);