From patchwork Thu Feb 21 07:21:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1045840 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="P2fyB9GU"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 444mBH13HXz9sBF for ; Thu, 21 Feb 2019 18:21:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726680AbfBUHV6 (ORCPT ); Thu, 21 Feb 2019 02:21:58 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:7891 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726219AbfBUHV6 (ORCPT ); Thu, 21 Feb 2019 02:21:58 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 20 Feb 2019 23:22:03 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 20 Feb 2019 23:21:57 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 20 Feb 2019 23:21:57 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:21:57 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 21 Feb 2019 07:21:57 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 20 Feb 2019 23:21:57 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , Thomas Gleixner CC: , , Joseph Lo , , , Rob Herring Subject: [PATCH V7 1/8] dt-bindings: timer: add Tegra210 timer Date: Thu, 21 Feb 2019 15:21:43 +0800 Message-ID: <20190221072150.4395-2-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221072150.4395-1-josephl@nvidia.com> References: <20190221072150.4395-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1550733724; bh=3lHJQTnyy/s1T3oQkkJrYUFvEa7JrbFiTtgfe8q74Rc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=P2fyB9GUZ+FHwJARtxWATadNBEEvjkhlOp+MyHGzoUJfT+5cZXoALqTEZr2oYhX+V cznagakCaCykOAM+dFyNj186O9ZGGDMIBXig9YA8aHgwLZQNc5FqPenciGZkdzzSNF /l5n5BM2+J+a6ThdoybZroLuGOkfLib1FUSelp305eFaYQNVBXazwi/OvCust73vvx ueo8h+/7musLxmEoMdQx2dpHI5UCHay/LTmWKAUpPzrIZE7/ArutUds5xbT0Q5yRG2 bcl9h+B3ZEejaCaQ3fUVs8Z7pnDKDNPRupszIritbSNFsVpIyQvvqeORdkcRQ9cXg8 w0mCM14XolsGw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic, or watchdog interrupts. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Reviewed-by: Rob Herring Acked-by: Jon Hunter --- v7: * no change v6: * add ack tag from Jon. v5: * no change v4: * no change v3: * no change v2: * list all the interrupts that are supported by tegra210 timers block * add RB tag from Rob. --- .../bindings/timer/nvidia,tegra210-timer.txt | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt new file mode 100644 index 000000000000..032cda96fe0d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt @@ -0,0 +1,36 @@ +NVIDIA Tegra210 timer + +The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived +from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock +(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic, +or watchdog interrupts. + +Required properties: +- compatible : "nvidia,tegra210-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : A list of 14 interrupts; one per each timer channels 0 through + 13. +- clocks : Must contain one entry, for the module clock. + See ../clocks/clock-bindings.txt for details. + +timer@60005000 { + compatible = "nvidia,tegra210-timer"; + reg = <0x0 0x60005000 0x0 0x400>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_TIMER>; + clock-names = "timer"; +}; From patchwork Thu Feb 21 07:21:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1045845 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="otJq9ScE"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 444mBS6NFyz9sD4 for ; Thu, 21 Feb 2019 18:22:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726292AbfBUHWC (ORCPT ); Thu, 21 Feb 2019 02:22:02 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:7903 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726219AbfBUHWB (ORCPT ); Thu, 21 Feb 2019 02:22:01 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 20 Feb 2019 23:22:06 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 20 Feb 2019 23:22:00 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 20 Feb 2019 23:22:00 -0800 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:21:59 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 21 Feb 2019 07:21:59 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 20 Feb 2019 23:21:59 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , Thomas Gleixner CC: , , Joseph Lo , , Thierry Reding Subject: [PATCH V7 2/8] clocksource: tegra: add Tegra210 timer support Date: Thu, 21 Feb 2019 15:21:44 +0800 Message-ID: <20190221072150.4395-3-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221072150.4395-1-josephl@nvidia.com> References: <20190221072150.4395-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1550733726; bh=f454FOdTT2RaY4g8msOQEUfNf6jm2ACuW1jcHGmERsA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=otJq9ScE2iRKkpoV13xtWIUZo0PHyYbRszcyTWh2qhFwLvHCH3rVHK3Okuatf57A2 ZLcfrorVdJPN3zID02aaJvM2Czn+1h9laqBKTNSdVsCG2Ol3X4LDA/PUTu3SW5/z9r GVZfp1AHCIxlZvjb8Lc7PjqG/Er+LTKf1GNeCKp878gmptFYuNZocJQfzq4ycmQztU 40vyg2eSG0Imyt+75/i9EInd08qyHEdNmBqNK4z2lhJxQgoza6Z16mU/99A8z3d8Zh RPwTfSJiH1onDJ0k9sBCnIOyrhPtrtUGvkSZJLUtxQUAoBhSnBbqvN2g9yaq1SW0WZ ZlDNLu3byZJew== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add support for the Tegra210 timer that runs at oscillator clock (TMR10-TMR13). We need these timers to work as clock event device and to replace the ARMv8 architected timer due to it can't survive across the power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up source when CPU suspends in power down state. Also convert the original driver to use timer-of API. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Thierry Reding Acked-by: Jon Hunter Acked-by: Daniel Lezcano --- v7: * kconfig fix for 'depends on ARM || ARM64' * move suspend/resume to clkevt * refine the usage for the macro of TIMER_OF_DECLARE v6: * refine the timer defines * add ack tag from Jon. v5: * add ack tag from Thierry v4: * merge timer-tegra210.c in previous version into timer-tegra20.c v3: * use timer-of API v2: * add error clean-up code --- drivers/clocksource/Kconfig | 3 +- drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++--------- include/linux/cpuhotplug.h | 1 + 3 files changed, 262 insertions(+), 112 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 8dfd3bc448d0..5d93e580e5dc 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -131,7 +131,8 @@ config SUN5I_HSTIMER config TEGRA_TIMER bool "Tegra timer driver" if COMPILE_TEST select CLKSRC_MMIO - depends on ARM + select TIMER_OF + depends on ARM || ARM64 help Enables support for the Tegra driver. diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 4293943f4e2b..fdb3d795a409 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -15,21 +15,24 @@ * */ -#include +#include +#include +#include +#include +#include #include -#include #include -#include -#include -#include -#include -#include #include #include +#include #include -#include +#include + +#include "timer-of.h" +#ifdef CONFIG_ARM #include +#endif #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c @@ -39,74 +42,161 @@ #define TIMERUS_USEC_CFG 0x14 #define TIMERUS_CNTR_FREEZE 0x4c -#define TIMER1_BASE 0x0 -#define TIMER2_BASE 0x8 -#define TIMER3_BASE 0x50 -#define TIMER4_BASE 0x58 - -#define TIMER_PTV 0x0 -#define TIMER_PCR 0x4 - +#define TIMER_PTV 0x0 +#define TIMER_PTV_EN BIT(31) +#define TIMER_PTV_PER BIT(30) +#define TIMER_PCR 0x4 +#define TIMER_PCR_INTR_CLR BIT(30) + +#ifdef CONFIG_ARM +#define TIMER_CPU0 0x50 /* TIMER3 */ +#else +#define TIMER_CPU0 0x90 /* TIMER10 */ +#define TIMER10_IRQ_IDX 10 +#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) +#endif +#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8) + +static u32 usec_config; static void __iomem *timer_reg_base; +#ifdef CONFIG_ARM static void __iomem *rtc_base; - static struct timespec64 persistent_ts; static u64 persistent_ms, last_persistent_ms; - static struct delay_timer tegra_delay_timer; - -#define timer_writel(value, reg) \ - writel_relaxed(value, timer_reg_base + (reg)) -#define timer_readl(reg) \ - readl_relaxed(timer_reg_base + (reg)) +#endif static int tegra_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - u32 reg; + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); + writel(TIMER_PTV_EN | + ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ + reg_base + TIMER_PTV); return 0; } -static inline void timer_shutdown(struct clock_event_device *evt) +static int tegra_timer_shutdown(struct clock_event_device *evt) { - timer_writel(0, TIMER3_BASE + TIMER_PTV); + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + + writel(0, reg_base + TIMER_PTV); + + return 0; } -static int tegra_timer_shutdown(struct clock_event_device *evt) +static int tegra_timer_set_periodic(struct clock_event_device *evt) { - timer_shutdown(evt); + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + + writel(TIMER_PTV_EN | TIMER_PTV_PER | + ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), + reg_base + TIMER_PTV); + return 0; } -static int tegra_timer_set_periodic(struct clock_event_device *evt) +static irqreturn_t tegra_timer_isr(int irq, void *dev_id) +{ + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + + writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static void tegra_timer_suspend(struct clock_event_device *evt) +{ + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + + writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); +} + +static void tegra_timer_resume(struct clock_event_device *evt) +{ + writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); +} + +#ifdef CONFIG_ARM64 +static DEFINE_PER_CPU(struct timer_of, tegra_to) = { + .flags = TIMER_OF_CLOCK | TIMER_OF_BASE, + + .clkevt = { + .name = "tegra_timer", + .rating = 460, + .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, + .set_next_event = tegra_timer_set_next_event, + .set_state_shutdown = tegra_timer_shutdown, + .set_state_periodic = tegra_timer_set_periodic, + .set_state_oneshot = tegra_timer_shutdown, + .tick_resume = tegra_timer_shutdown, + .suspend = tegra_timer_suspend, + .resume = tegra_timer_resume, + }, +}; + +static int tegra_timer_setup(unsigned int cpu) { - u32 reg = 0xC0000000 | ((1000000 / HZ) - 1); + struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + + irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); + enable_irq(to->clkevt.irq); + + clockevents_config_and_register(&to->clkevt, timer_of_rate(to), + 1, /* min */ + 0x1fffffff); /* 29 bits */ - timer_shutdown(evt); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); return 0; } -static struct clock_event_device tegra_clockevent = { - .name = "timer0", - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_DYNIRQ, - .set_next_event = tegra_timer_set_next_event, - .set_state_shutdown = tegra_timer_shutdown, - .set_state_periodic = tegra_timer_set_periodic, - .set_state_oneshot = tegra_timer_shutdown, - .tick_resume = tegra_timer_shutdown, +static int tegra_timer_stop(unsigned int cpu) +{ + struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + + to->clkevt.set_state_shutdown(&to->clkevt); + disable_irq_nosync(to->clkevt.irq); + + return 0; +} +#else /* CONFIG_ARM */ +static struct timer_of tegra_to = { + .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ, + + .clkevt = { + .name = "tegra_timer", + .rating = 300, + .features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_DYNIRQ, + .set_next_event = tegra_timer_set_next_event, + .set_state_shutdown = tegra_timer_shutdown, + .set_state_periodic = tegra_timer_set_periodic, + .set_state_oneshot = tegra_timer_shutdown, + .tick_resume = tegra_timer_shutdown, + .suspend = tegra_timer_suspend, + .resume = tegra_timer_resume, + .cpumask = cpu_possible_mask, + }, + + .of_irq = { + .index = 2, + .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, + .handler = tegra_timer_isr, + }, }; static u64 notrace tegra_read_sched_clock(void) { - return timer_readl(TIMERUS_CNTR_1US); + return readl(timer_reg_base + TIMERUS_CNTR_1US); +} + +static unsigned long tegra_delay_timer_read_counter_long(void) +{ + return readl(timer_reg_base + TIMERUS_CNTR_1US); } /* @@ -143,100 +233,155 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts) timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC); *ts = persistent_ts; } +#endif -static unsigned long tegra_delay_timer_read_counter_long(void) -{ - return readl(timer_reg_base + TIMERUS_CNTR_1US); -} - -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = (struct clock_event_device *)dev_id; - timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static struct irqaction tegra_timer_irq = { - .name = "timer0", - .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, - .handler = tegra_timer_interrupt, - .dev_id = &tegra_clockevent, -}; - -static int __init tegra20_init_timer(struct device_node *np) +static int tegra_timer_common_init(struct device_node *np, struct timer_of *to) { - struct clk *clk; - unsigned long rate; - int ret; - - timer_reg_base = of_iomap(np, 0); - if (!timer_reg_base) { - pr_err("Can't map timer registers\n"); - return -ENXIO; - } + int ret = 0; - tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); - if (tegra_timer_irq.irq <= 0) { - pr_err("Failed to map timer IRQ\n"); - return -EINVAL; - } + ret = timer_of_init(np, to); + if (ret < 0) + goto out; - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); - rate = 12000000; - } else { - clk_prepare_enable(clk); - rate = clk_get_rate(clk); - } + timer_reg_base = timer_of_base(to); - switch (rate) { + /* + * Configure microsecond timers to have 1MHz clock + * Config register is 0xqqww, where qq is "dividend", ww is "divisor" + * Uses n+1 scheme + */ + switch (timer_of_rate(to)) { case 12000000: - timer_writel(0x000b, TIMERUS_USEC_CFG); + usec_config = 0x000b; /* (11+1)/(0+1) */ + break; + case 12800000: + usec_config = 0x043f; /* (63+1)/(4+1) */ break; case 13000000: - timer_writel(0x000c, TIMERUS_USEC_CFG); + usec_config = 0x000c; /* (12+1)/(0+1) */ + break; + case 16800000: + usec_config = 0x0453; /* (83+1)/(4+1) */ break; case 19200000: - timer_writel(0x045f, TIMERUS_USEC_CFG); + usec_config = 0x045f; /* (95+1)/(4+1) */ break; case 26000000: - timer_writel(0x0019, TIMERUS_USEC_CFG); + usec_config = 0x0019; /* (25+1)/(0+1) */ + break; + case 38400000: + usec_config = 0x04bf; /* (191+1)/(4+1) */ + break; + case 48000000: + usec_config = 0x002f; /* (47+1)/(0+1) */ break; default: - WARN(1, "Unknown clock rate"); + ret = -EINVAL; + goto out; + } + + writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG); + +out: + return ret; +} + +#ifdef CONFIG_ARM64 +static int __init tegra_init_timer(struct device_node *np) +{ + int cpu, ret = 0; + struct timer_of *to; + + to = this_cpu_ptr(&tegra_to); + ret = tegra_timer_common_init(np, to); + if (ret < 0) + goto out; + + for_each_possible_cpu(cpu) { + struct timer_of *cpu_to; + + cpu_to = per_cpu_ptr(&tegra_to, cpu); + cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu); + cpu_to->of_clk.rate = timer_of_rate(to); + cpu_to->clkevt.cpumask = cpumask_of(cpu); + cpu_to->clkevt.irq = + irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); + if (!cpu_to->clkevt.irq) { + pr_err("%s: can't map IRQ for CPU%d\n", + __func__, cpu); + ret = -EINVAL; + goto out; + } + + irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); + ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, + IRQF_TIMER | IRQF_NOBALANCING, + cpu_to->clkevt.name, &cpu_to->clkevt); + if (ret) { + pr_err("%s: cannot setup irq %d for CPU%d\n", + __func__, cpu_to->clkevt.irq, cpu); + ret = -EINVAL; + goto out_irq; + } + } + + cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, + "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, + tegra_timer_stop); + + return ret; +out_irq: + for_each_possible_cpu(cpu) { + struct timer_of *cpu_to; + + cpu_to = per_cpu_ptr(&tegra_to, cpu); + if (cpu_to->clkevt.irq) { + free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt); + irq_dispose_mapping(cpu_to->clkevt.irq); + } } +out: + timer_of_cleanup(to); + return ret; +} +#else /* CONFIG_ARM */ +static int __init tegra_init_timer(struct device_node *np) +{ + int ret = 0; + + ret = tegra_timer_common_init(np, &tegra_to); + if (ret < 0) + goto out; - sched_clock_register(tegra_read_sched_clock, 32, 1000000); + tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0); + tegra_to.of_clk.rate = 1000000; /* microsecond timer */ + sched_clock_register(tegra_read_sched_clock, 32, + timer_of_rate(&tegra_to)); ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", 1000000, 300, 32, - clocksource_mmio_readl_up); + "timer_us", timer_of_rate(&tegra_to), + 300, 32, clocksource_mmio_readl_up); if (ret) { pr_err("Failed to register clocksource\n"); - return ret; + goto out; } tegra_delay_timer.read_current_timer = tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = 1000000; + tegra_delay_timer.freq = timer_of_rate(&tegra_to); register_current_timer_delay(&tegra_delay_timer); - ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); - if (ret) { - pr_err("Failed to register timer IRQ: %d\n", ret); - return ret; - } + clockevents_config_and_register(&tegra_to.clkevt, + timer_of_rate(&tegra_to), + 0x1, + 0x1fffffff); - tegra_clockevent.cpumask = cpu_possible_mask; - tegra_clockevent.irq = tegra_timer_irq.irq; - clockevents_config_and_register(&tegra_clockevent, 1000000, - 0x1, 0x1fffffff); + return ret; +out: + timer_of_cleanup(&tegra_to); - return 0; + return ret; } -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); static int __init tegra20_init_rtc(struct device_node *np) { @@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct device_node *np) return register_persistent_clock(tegra_read_persistent_clock64); } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); +#endif +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer); +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index fd586d0301e7..e78281d07b70 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -121,6 +121,7 @@ enum cpuhp_state { CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, CPUHP_AP_ARM_TWD_STARTING, CPUHP_AP_QCOM_TIMER_STARTING, + CPUHP_AP_TEGRA_TIMER_STARTING, CPUHP_AP_ARMADA_TIMER_STARTING, CPUHP_AP_MARCO_TIMER_STARTING, CPUHP_AP_MIPS_GIC_TIMER_STARTING, From patchwork Thu Feb 21 07:21:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1045842 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="H9H9T2Wq"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 444mBQ2g2Tz9sBr for ; Thu, 21 Feb 2019 18:22:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726219AbfBUHWE (ORCPT ); Thu, 21 Feb 2019 02:22:04 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:2843 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727044AbfBUHWD (ORCPT ); Thu, 21 Feb 2019 02:22:03 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 20 Feb 2019 23:22:10 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 20 Feb 2019 23:22:02 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 20 Feb 2019 23:22:02 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:22:02 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:22:02 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 21 Feb 2019 07:22:01 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 20 Feb 2019 23:22:01 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , "Thomas Gleixner" CC: , , Joseph Lo , Thierry Reding Subject: [PATCH V7 3/8] soc/tegra: default select TEGRA_TIMER for Tegra210 Date: Thu, 21 Feb 2019 15:21:45 +0800 Message-ID: <20190221072150.4395-4-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221072150.4395-1-josephl@nvidia.com> References: <20190221072150.4395-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1550733730; bh=puuvg2631Nt+Oa9pn1c8k94YNAeE1c9YhtHedKj6rHc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=H9H9T2WqGJWFiQphdou5Z4utIZ1XbQGJQGtSzRDJpFotMmjBan8xzeR0g4FJfTqBq K/jy8J0oX2aannuaLYimFZEDL1uHuEt7KQtBjVc7vZSaQPzDtWU+TQHYmeXPgq4j/j DzGwfeO2KsivlkkJyarvJKPe69XWxk0zZ7Wy7VJOjAGbpCTW4kdkZaR0VZcinEHuyX nJ053TIc5VF4k1OapXnW4mrkuXJaZUoBvDKeeltXvCc5seHC1iTb4dZZUVBWAXOK93 2xx95/T9Cz5eg6amve6DmLPvZndMmdyr081oUdutFTJjXfJn+/1g4kstA68pztnvgC Xhwind6V7MtXA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The tegra timer is necessary for Tegra210 to support CPU idle power-down state. So select it by default. Signed-off-by: Joseph Lo Acked-by: Thierry Reding Acked-by: Jon Hunter --- v7: * no change v6: * add ack tag from Jon. v5: * add ack tag from Thierry. v4: * new added in this version --- drivers/soc/tegra/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index fe4481676da6..a0b03443d8c1 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -76,6 +76,7 @@ config ARCH_TEGRA_210_SOC select PINCTRL_TEGRA210 select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC + select TEGRA_TIMER help Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53 From patchwork Thu Feb 21 07:21:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1045843 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="ltIjuM6G"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 444mBR3JlCz9sD4 for ; Thu, 21 Feb 2019 18:22:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727044AbfBUHWF (ORCPT ); Thu, 21 Feb 2019 02:22:05 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:7922 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727161AbfBUHWF (ORCPT ); Thu, 21 Feb 2019 02:22:05 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 20 Feb 2019 23:22:10 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 20 Feb 2019 23:22:04 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 20 Feb 2019 23:22:04 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:22:04 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:22:03 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 21 Feb 2019 07:22:03 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 20 Feb 2019 23:22:03 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , "Thomas Gleixner" CC: , , Joseph Lo Subject: [PATCH V7 4/8] arm64: tegra: fix timer node for Tegra210 Date: Thu, 21 Feb 2019 15:21:46 +0800 Message-ID: <20190221072150.4395-5-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221072150.4395-1-josephl@nvidia.com> References: <20190221072150.4395-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1550733730; bh=tg/Ekpwc3CEibmk4JYWVpJwucI6vp/74MfYWYNPoyL0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=ltIjuM6GvJwh5HyJcSlIFziS6ndve1xiT7G0H3QVDEyP3wWMrqiqajFq9kPhiNXDt MpMKTfqVqLfosvl5d7ocVM6r1f5Kf8mpojUcRYbU3InHrnad2ZgSaQ7fGFToUzCOWB iyYHcONTKE+eXNfSFPvHnTQ9t9elAHxagjrtGRFUGgZYeYpCZ5BpOok9cy0Jc49r9H tVPPgFsu9eTbkWwgbJ8SCLgNN/SSCBgoaaX/1IzMZNXw6F9rNvLwkIOUTRUGDWaVUj BWDyhVcnF/of27DnmmAPnch9HyqdzmQmRPIn7Ok3Q5vPkAG7KqkHYDuLki6/as6/mJ w0QivLxUfiGQg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Fix timer node to make it work with Tegra210 timer driver. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- v7: * no change v6: * add ack tag from Jon. v5: * no change v4: * no change v3: * no change v2: * list all the IRQs per each timer channels 0 through 13 * remove compatible string of "nvidia,tegra30-timer" --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 6574396d2257..abbb686bd8ba 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -384,14 +384,22 @@ }; timer@60005000 { - compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra210-timer"; reg = <0x0 0x60005000 0x0 0x400>; - interrupts = , + interrupts = , + , , , , , - ; + , + , + , + , + , + , + , + ; clocks = <&tegra_car TEGRA210_CLK_TIMER>; clock-names = "timer"; }; From patchwork Thu Feb 21 07:21:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1045844 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="ng8z7cxy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 444mBS1PKTz9sBr for ; Thu, 21 Feb 2019 18:22:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727183AbfBUHWH (ORCPT ); Thu, 21 Feb 2019 02:22:07 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:7935 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727176AbfBUHWH (ORCPT ); Thu, 21 Feb 2019 02:22:07 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 20 Feb 2019 23:22:12 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 20 Feb 2019 23:22:06 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 20 Feb 2019 23:22:06 -0800 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:22:06 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 21 Feb 2019 07:22:06 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 20 Feb 2019 23:22:06 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , Thomas Gleixner CC: , , Joseph Lo Subject: [PATCH V7 5/8] arm64: tegra: add CPU idle states properties for Tegra210 Date: Thu, 21 Feb 2019 15:21:47 +0800 Message-ID: <20190221072150.4395-6-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221072150.4395-1-josephl@nvidia.com> References: <20190221072150.4395-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1550733732; bh=Krx9tvdK8mQ7TQM92OcKajbqr0b518YrQWvANYWEcRI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=ng8z7cxyH1l6eMNTRE9LgCFwFXhZ+5elSU5uBck2vP1VXnABZqkBrl7/VpI/ci7OM NVoonpW9421HnMP1DANcvpgD9obXvLH/PR/RcaNei4Zojdm4PamBQ4X+9RJ0qXuWH+ pPFLRda38iD4znM3M7K9LpgfwoxmwG3+8w26FIFWpJoOukRSfTOmAprAhcKr9yhpcs ClTsFwocRg4AY7XmaS5ILxFB6ImWFJh6e7bJpG3x6IdfK4YX+u7e59dl6rMZOf0nNH 9dfA8ryyxedZv0AQxJkXH21mmJ7GlEmLJNfiLS3n9wqEWEb4wr7LJIOkWEwHhxqbJv lMMrmVhNv8G8w== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add idle states properties for generic ARM CPU idle driver. This includes a cpu-sleep state which is the power down state of CPU cores. Signed-off-by: Joseph Lo Acked-by: Jon Hunter Acked-by: Daniel Lezcano --- v7: * s/C7/CPU_SLEEP/ & s/c7/cpu-sleep/ * update the timing of 'entry/exit-latency-us' v6: * add ack tag from Jon. v5: * no change v4: * no change v3: * no change v2: * add entry-latency-us and exit-latency-us properties --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index abbb686bd8ba..79cedd36ffad 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1371,24 +1371,43 @@ <&dfll>; clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; + cpu-idle-states = <&CPU_SLEEP>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <1>; + cpu-idle-states = <&CPU_SLEEP>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <2>; + cpu-idle-states = <&CPU_SLEEP>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <3>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000007>; + entry-latency-us = <100>; + exit-latency-us = <30>; + min-residency-us = <1000>; + wakeup-latency-us = <130>; + idle-state-name = "cpu-sleep"; + status = "disabled"; + }; }; }; From patchwork Thu Feb 21 07:21:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1045847 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Sfrv86N+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 444mBT5sPhz9sBr for ; Thu, 21 Feb 2019 18:22:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727184AbfBUHWJ (ORCPT ); Thu, 21 Feb 2019 02:22:09 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:7315 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727176AbfBUHWI (ORCPT ); Thu, 21 Feb 2019 02:22:08 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 20 Feb 2019 23:22:07 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 20 Feb 2019 23:22:08 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 20 Feb 2019 23:22:08 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:22:08 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 21 Feb 2019 07:22:08 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 20 Feb 2019 23:22:08 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , Thomas Gleixner CC: , , Joseph Lo Subject: [PATCH V7 6/8] arm64: tegra: Enable CPU idle support for Jetson TX1 Date: Thu, 21 Feb 2019 15:21:48 +0800 Message-ID: <20190221072150.4395-7-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221072150.4395-1-josephl@nvidia.com> References: <20190221072150.4395-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1550733727; bh=wwcRKqRLhJrFyHtQ1XvXF4Ehy7yBE3l/POMWxm4Ao6c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=Sfrv86N+utJo+2QZc7/So8Zi5kpu7hKigFT7T8/fnOKxDSkpIMcANbhz5Lgr01jAT +/EokEPY/WiEJpZSEHGBIU6w85eyukwoKXWLDnnMnBiiHKUZMsntK+Qiba40gJvvj4 cAZMcYSFOtaLzTYb0Se3K+mvk/a3ddSerNIv87LqawZzoucXOlfF/WlmrKI3XPp6jo kyrWs5/OtzaY+nnjfzpqPgD9UrQsm6eKI8o0tKNDRCqor3d0tGSZJsxbt4tF2GAU2E IDcP/u3qPFpO7Nyn7cBYV1vUoDQs8AHX6rIuBYvv+s8DukuxRj1BRXy4txR47kKqT+ QkJ6EUlD+Aavg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable CPU idle support for Jetson TX1 platform. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- v7: * s/c7/cpu-sleep/ v6: * add ack tag from Jon. v5: * no change v4: * no change v3: * no change v2: * no change --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 053458a5db55..4dcd0d36189a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -305,6 +305,12 @@ cpu@3 { enable-method = "psci"; }; + + idle-states { + cpu-sleep { + status = "okay"; + }; + }; }; psci { From patchwork Thu Feb 21 07:21:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1045848 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="OceaUCzG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 444mBY09h8z9sCH for ; Thu, 21 Feb 2019 18:22:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727210AbfBUHWM (ORCPT ); Thu, 21 Feb 2019 02:22:12 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:7321 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727161AbfBUHWL (ORCPT ); Thu, 21 Feb 2019 02:22:11 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 20 Feb 2019 23:22:09 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 20 Feb 2019 23:22:10 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 20 Feb 2019 23:22:10 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:22:10 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:22:10 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 21 Feb 2019 07:22:10 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 20 Feb 2019 23:22:10 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , "Thomas Gleixner" CC: , , Joseph Lo Subject: [PATCH V7 7/8] arm64: tegra: Enable CPU idle support for Smaug Date: Thu, 21 Feb 2019 15:21:49 +0800 Message-ID: <20190221072150.4395-8-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221072150.4395-1-josephl@nvidia.com> References: <20190221072150.4395-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1550733729; bh=KRDQj9vXKb5WlKoNng8/9HfzHsIaDhd8WrkgXmcCnjI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=OceaUCzG5OThXNia803Z+ylIPMeCc2SkVbJpCZAyGcS6PWYPCFdK9kkqZo3Zny0wH 1z8Q+LesWyJVf3JCYU/OhXJJBfmBtWuuKyW+QSsYrJF6CuICDWRYr3Z2AZw35fcCux 8fNfoZ1x1Mo9FBou3WZLOPgVrjPoUtJyTh924QSmlv2G2TWPu/0af4SO/qJosIOhWq pdzPx6oTF2wmuUs3NWeOrljsWX7Pei75T4XWjm0Iddd8Pxv3lHOf3LCHd6IfgdCTgZ dqOuCRQCR/r7PGiZTcOf3FthFK1s6n36nVtvF2dwp9+Q8zaY3gBEEAMbbcPTenGRdV CiqLi0T5ODJWQ== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable CPU idle support for Smaug platform. Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- v7: * s/c7/cpu-sleep/ v6: * add ack tag from Jon. v5: * no change v4: * no change v3: * no change v2: * no change --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index a4b8f668a6d4..25fd65b5397a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1751,6 +1751,13 @@ cpu@3 { enable-method = "psci"; }; + + idle-states { + cpu-sleep { + arm,psci-suspend-param = <0x00010007>; + status = "okay"; + }; + }; }; gpio-keys { From patchwork Thu Feb 21 07:21:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1045849 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="TkEwW293"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 444mBZ0CY2z9sD4 for ; Thu, 21 Feb 2019 18:22:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727219AbfBUHWN (ORCPT ); Thu, 21 Feb 2019 02:22:13 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:2883 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727161AbfBUHWN (ORCPT ); Thu, 21 Feb 2019 02:22:13 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 20 Feb 2019 23:22:21 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 20 Feb 2019 23:22:12 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 20 Feb 2019 23:22:12 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:22:12 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 21 Feb 2019 07:22:12 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 21 Feb 2019 07:22:12 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 20 Feb 2019 23:22:12 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter , Daniel Lezcano , "Thomas Gleixner" CC: , , Joseph Lo Subject: [PATCH V7 8/8] arm64: tegra: Enable CPU idle support for Shield Date: Thu, 21 Feb 2019 15:21:50 +0800 Message-ID: <20190221072150.4395-9-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190221072150.4395-1-josephl@nvidia.com> References: <20190221072150.4395-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1550733741; bh=44biMiFScpj3JFxN9qB/6joZqFonPW8T1GzONE394E0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=TkEwW293nh5MBK9R6Z/cQ+z8MhuofVlmEA6gwe9Wy18BRG1aOr1k5xpIdG69/fHR8 a0w5jQNE/HZRgRSnIm2gRpGhIJdkdIasQW6oR3tBJdRf7Kvhf7PKcjC0mkxLbcakrY YytkFMSok+8kvQjqncz6/iyq13OK52syWAkxzMdvvtRyAvh+n9Ma0tGsESVaA35vDE Y+bgcNe5FyiK7lfiik/WxFScBwT10DnCo0+EUBPpyd/vqOyrTM7dn/nIZ1xD8rklPW lDsdNQjfmPUUE8L3Z6iYa3/SXKSkVyCly4E19j6h3g4XT8yHrVHutJPkyyw4Js2w3u ceJNOiJrdUTCA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable CPU idle support for Shield platform. Signed-off-by: Joseph Lo --- v7: * new added in v7 --- arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 3ddf173ccc18..88a4b9333d84 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1629,6 +1629,12 @@ cpu@3 { enable-method = "psci"; }; + + idle-states { + cpu-sleep { + status = "okay"; + }; + }; }; psci {