From patchwork Tue Feb 19 20:02:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Smirnov X-Patchwork-Id: 1044881 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ExGmZZHM"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 443sCJ5w8Nz9s6w for ; Wed, 20 Feb 2019 07:04:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729632AbfBSUER (ORCPT ); Tue, 19 Feb 2019 15:04:17 -0500 Received: from mail-pl1-f193.google.com ([209.85.214.193]:42093 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726451AbfBSUEP (ORCPT ); Tue, 19 Feb 2019 15:04:15 -0500 Received: by mail-pl1-f193.google.com with SMTP id s1so10933339plp.9; Tue, 19 Feb 2019 12:04:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eOrFyuS90LqtoruGZQ65onq0a4QdxsrTnhK0HpBAldc=; b=ExGmZZHMJkg3u9OTKDoU6CCkSbgS+0X12DwR4A9Kul4Uc9A4dJMK9tC41OY6d5a9Aw aglv0JYk/EC04WF1sZDFpRcUzT920K3kqaF3OTvXmaPgQakA8Lxf0n2CHy2zZFUJOH1P ZdGLnpsVsX9j9xJVJaiWHxNAL1Da9ACaADQVn+kS5txtuer1F5e5fg0ImOotxr7syKmU Zg0PkSB55QlPBaNkBjnM2LtTtjQSOm774p+m3Ru0am6yp72tcDrP8dNiUh8EVoG5Kzj+ vb9NJKu5Wj3ED3Ylgy3n7yEiUJxkSN5ebyMQ6EgsjdWnVUp3nYXagfA8Mt6ILQEvTpII RqTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eOrFyuS90LqtoruGZQ65onq0a4QdxsrTnhK0HpBAldc=; b=aSzH5AEYqb8/XW87xh5xEfvL/Th0J6I6ra5HuAXM12rWK1ewSKnvT4EWQ776QqmybC A+GA/RxBCMbmiGEKWu1JRgbwh+aMUwHE4TgnU+0EgEn/rvEcj+MLcfBUTMZeidt84kVI RiRS8J7zZNcniFY3nqh6WvaoXhVjdQ4+1GSNoC871bv5xBqproCSH7sYlOrwq4ReDNRe UCL4FiFOoVkL/5B55pHbAdI609pJRZeKkScLgObUU6eJQYn37zdMN52pZQSsl93CfYTn 3WA/m/AMGn/uyhqpvFzCI8VjSnq48tK9uNwYVX1SJR/iMXsanEgP616w45cdhbLEzUA2 t54Q== X-Gm-Message-State: AHQUAuad9eI0RglfaETcL+A530+B2vsK0epDnp0PRzIik3JTPuuAHbYh 3JUqGk1AaG6ltAZTYtK7eVk= X-Google-Smtp-Source: AHgI3Iaok4AZgi6TJpw48i3eaqZf3u11jkTAsAOrUkZ2mXkf+ku18NlCOMapd64px1h1GQ/s2/axCw== X-Received: by 2002:a17:902:9a95:: with SMTP id w21mr32430815plp.118.1550606654870; Tue, 19 Feb 2019 12:04:14 -0800 (PST) Received: from squirtle.lan (c-24-22-235-96.hsd1.wa.comcast.net. [24.22.235.96]) by smtp.gmail.com with ESMTPSA id e63sm31519622pfc.47.2019.02.19.12.04.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Feb 2019 12:04:14 -0800 (PST) From: Andrey Smirnov To: Lorenzo Pieralisi Cc: Andrey Smirnov , Gustavo Pimentel , Bjorn Helgaas , Fabio Estevam , Chris Healy , Lucas Stach , Leonard Crestez , "A.s. Dong" , Richard Zhu , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 1/5] PCI: dwc: Make use of IS_ALIGNED() Date: Tue, 19 Feb 2019 12:02:38 -0800 Message-Id: <20190219200242.17243-2-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219200242.17243-1-andrew.smirnov@gmail.com> References: <20190219200242.17243-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Make the intent a bit more clear as well as get rid of explicit arithmetic by using IS_ALIGNED() to determine if "addr" is aligned to "size". No functional change intended. Signed-off-by: Andrey Smirnov Acked-by: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org --- drivers/pci/controller/dwc/pcie-designware.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 93ef8c31fb39..67236379c61a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -22,7 +22,7 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val) { - if ((uintptr_t)addr & (size - 1)) { + if (!IS_ALIGNED((uintptr_t)addr, size)) { *val = 0; return PCIBIOS_BAD_REGISTER_NUMBER; } @@ -43,7 +43,7 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val) int dw_pcie_write(void __iomem *addr, int size, u32 val) { - if ((uintptr_t)addr & (size - 1)) + if (!IS_ALIGNED((uintptr_t)addr, size)) return PCIBIOS_BAD_REGISTER_NUMBER; if (size == 4) From patchwork Tue Feb 19 20:02:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Smirnov X-Patchwork-Id: 1044880 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Kis3oj3j"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 443sCG5WYlz9s6w for ; Wed, 20 Feb 2019 07:04:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729668AbfBSUES (ORCPT ); Tue, 19 Feb 2019 15:04:18 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:35128 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729638AbfBSUER (ORCPT ); Tue, 19 Feb 2019 15:04:17 -0500 Received: by mail-pl1-f195.google.com with SMTP id p8so10951846plo.2; Tue, 19 Feb 2019 12:04:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7zn1Jso68+ps/Kh/7DAZgNR71SoxjfHsFyh8div2Ihs=; b=Kis3oj3jXF0ANwB2G41FeWJeyQ3FdHxBIWM0FTBwP+kFYfsg5shhl/pt+bCNZtts82 JXVXQjuk/+GmIT7vIK7jy+DHL2JZ61oN6Oz8gL+iCPMvTkTTiSFi1F8wiNFMriPtSTA0 FB4XorGN65UHlmL4APKsDHFzHH22QcpGC5/GSQpWgBk5jJLPv/iSQmJnobB9Mi0izBLQ e+oaJN/yHK2bztEA4p+/bc+FCKisdGIZbFvzhMCjY50Z0qIUquXAifTamgUG0n5HfbAv 3YOl95z1V12U49m2byrz2VuBsP2QarpW6ZngGjosIJzwGXnuzLf2ZAGnh88fsc5Cj+Un 9v8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7zn1Jso68+ps/Kh/7DAZgNR71SoxjfHsFyh8div2Ihs=; b=pLD0ie/v88lXhtYEDuaGq8pXUryn9qz+WwSsmavDG8UccqBVDqx4ag2qzE7yGO/6Xk F6cfzA8M2m5fAPY5kfd7ED4oUMRKryGcb4MpgXjsTGYR9KbiqGl9sR2+PrDmzElmb35q T6z3PKRtF+qjXRSa/5CHZUWD4rccN604yUJ3H4JJpNNXDeLahBJvRtnhdClRMZttb49Z fROTuKT7VOOiDR33Iz21FfJMh0gbuOGydw6B13sUoAIaJYIuobg1/OUmhYEQPqgoxZJf TlboQq57CRAA0ka74V6pIybZHhn5mPDML1eY2AR46eDIOj1oJ8DY2C/ILvny5KPS0sFl q0fA== X-Gm-Message-State: AHQUAuZpn2EJi8sG3PL+osKr1po0nCIYyZW9gwqu8+eihmrojQviAqqm xmds14BSb0Ii2mLY1lOY4wI= X-Google-Smtp-Source: AHgI3IbRI7q9KYAp9AZ8+6shmYkfxaKhV7eDpmJIN3SeblXin+Rif0oznINJYKHkn6jfsdsfVIvo8g== X-Received: by 2002:a17:902:e409:: with SMTP id ci9mr9313567plb.221.1550606656725; Tue, 19 Feb 2019 12:04:16 -0800 (PST) Received: from squirtle.lan (c-24-22-235-96.hsd1.wa.comcast.net. [24.22.235.96]) by smtp.gmail.com with ESMTPSA id e63sm31519622pfc.47.2019.02.19.12.04.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Feb 2019 12:04:15 -0800 (PST) From: Andrey Smirnov To: Lorenzo Pieralisi Cc: Andrey Smirnov , Gustavo Pimentel , Bjorn Helgaas , Fabio Estevam , Chris Healy , Lucas Stach , Leonard Crestez , "A.s. Dong" , Richard Zhu , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 2/5] PCI: dwc: Share code for dw_pcie_rd/wr_other_conf() Date: Tue, 19 Feb 2019 12:02:39 -0800 Message-Id: <20190219200242.17243-3-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219200242.17243-1-andrew.smirnov@gmail.com> References: <20190219200242.17243-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Default implementation of pcie_rd_other_conf() and dw_pcie_wd_other_conf() share more than 80% of their code. Move shared code into a dedicated subroutine and convert pcie_rd_other_conf() and dw_pcie_wd_other_conf() to use it. No functional change intended. Signed-off-by: Andrey Smirnov Acked-by: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org --- .../pci/controller/dwc/pcie-designware-host.c | 61 +++++++------------ 1 file changed, 23 insertions(+), 38 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 45ff5e4f8af6..0c18ab63811f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -512,8 +512,9 @@ int dw_pcie_host_init(struct pcie_port *pp) return ret; } -static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val) +static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val, + bool write) { int ret, type; u32 busdev, cfg_size; @@ -521,9 +522,6 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, void __iomem *va_cfg_base; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - if (pp->ops->rd_other_conf) - return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); - busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | PCIE_ATU_FUNC(PCI_FUNC(devfn)); @@ -542,7 +540,11 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, type, cpu_addr, busdev, cfg_size); - ret = dw_pcie_read(va_cfg_base + where, size, val); + if (write) + ret = dw_pcie_write(va_cfg_base + where, size, *val); + else + ret = dw_pcie_read(va_cfg_base + where, size, val); + if (pci->num_viewport <= 2) dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, PCIE_ATU_TYPE_IO, pp->io_base, @@ -551,43 +553,26 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, return ret; } +static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, + u32 devfn, int where, int size, u32 *val) +{ + if (pp->ops->rd_other_conf) + return pp->ops->rd_other_conf(pp, bus, devfn, where, + size, val); + + return dw_pcie_access_other_conf(pp, bus, devfn, where, size, val, + false); +} + static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - int ret, type; - u32 busdev, cfg_size; - u64 cpu_addr; - void __iomem *va_cfg_base; - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - if (pp->ops->wr_other_conf) - return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); - - busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | - PCIE_ATU_FUNC(PCI_FUNC(devfn)); + return pp->ops->wr_other_conf(pp, bus, devfn, where, + size, val); - if (bus->parent->number == pp->root_bus_nr) { - type = PCIE_ATU_TYPE_CFG0; - cpu_addr = pp->cfg0_base; - cfg_size = pp->cfg0_size; - va_cfg_base = pp->va_cfg0_base; - } else { - type = PCIE_ATU_TYPE_CFG1; - cpu_addr = pp->cfg1_base; - cfg_size = pp->cfg1_size; - va_cfg_base = pp->va_cfg1_base; - } - - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, - type, cpu_addr, - busdev, cfg_size); - ret = dw_pcie_write(va_cfg_base + where, size, val); - if (pci->num_viewport <= 2) - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, - PCIE_ATU_TYPE_IO, pp->io_base, - pp->io_bus_addr, pp->io_size); - - return ret; + return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val, + true); } static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, From patchwork Tue Feb 19 20:02:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Smirnov X-Patchwork-Id: 1044877 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; 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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id e63sm31519622pfc.47.2019.02.19.12.04.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Feb 2019 12:04:17 -0800 (PST) From: Andrey Smirnov To: Lorenzo Pieralisi Cc: Andrey Smirnov , Gustavo Pimentel , Bjorn Helgaas , Fabio Estevam , Chris Healy , Lucas Stach , Leonard Crestez , "A.s. Dong" , Richard Zhu , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 3/5] PCI: dwc: Make use of BIT() in constant definitions Date: Tue, 19 Feb 2019 12:02:40 -0800 Message-Id: <20190219200242.17243-4-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219200242.17243-1-andrew.smirnov@gmail.com> References: <20190219200242.17243-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Avoid using explicit left shifts and convert various definitions to use BIT() instead. No functional change intended. Signed-off-by: Andrey Smirnov Acked-by: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org --- drivers/pci/controller/dwc/pcie-designware.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 14 +++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 67236379c61a..31f6331ca46f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -306,7 +306,7 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index, } dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); - dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE); + dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, (u32)~PCIE_ATU_ENABLE); } int dw_pcie_wait_for_link(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 279000255ad1..070382869685 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -41,7 +41,7 @@ #define PORT_LOGIC_LTSSM_STATE_L0 0x11 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C -#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) +#define PORT_LOGIC_SPEED_CHANGE BIT(17) #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) @@ -55,8 +55,8 @@ #define PCIE_MSI_INTR0_STATUS 0x830 #define PCIE_ATU_VIEWPORT 0x900 -#define PCIE_ATU_REGION_INBOUND (0x1 << 31) -#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INBOUND BIT(31) +#define PCIE_ATU_REGION_OUTBOUND 0 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0) #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) @@ -66,8 +66,8 @@ #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) #define PCIE_ATU_CR2 0x908 -#define PCIE_ATU_ENABLE (0x1 << 31) -#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) +#define PCIE_ATU_ENABLE BIT(31) +#define PCIE_ATU_BAR_MODE_ENABLE BIT(30) #define PCIE_ATU_LOWER_BASE 0x90C #define PCIE_ATU_UPPER_BASE 0x910 #define PCIE_ATU_LIMIT 0x914 @@ -78,7 +78,7 @@ #define PCIE_ATU_UPPER_TARGET 0x91C #define PCIE_MISC_CONTROL_1_OFF 0x8BC -#define PCIE_DBI_RO_WR_EN (0x1 << 0) +#define PCIE_DBI_RO_WR_EN BIT(0) /* * iATU Unroll-specific register definitions @@ -105,7 +105,7 @@ ((region) << 9) #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ - (((region) << 9) | (0x1 << 8)) + (((region) << 9) | BIT(8)) #define MAX_MSI_IRQS 256 #define MAX_MSI_IRQS_PER_CTRL 32 From patchwork Tue Feb 19 20:02:41 2019 Content-Type: text/plain; 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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id e63sm31519622pfc.47.2019.02.19.12.04.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Feb 2019 12:04:18 -0800 (PST) From: Andrey Smirnov To: Lorenzo Pieralisi Cc: Andrey Smirnov , Gustavo Pimentel , Bjorn Helgaas , Fabio Estevam , Chris Healy , Lucas Stach , Leonard Crestez , "A.s. Dong" , Richard Zhu , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 4/5] PCI: dwc: Make use of GENMASK/FIELD_PREP Date: Tue, 19 Feb 2019 12:02:41 -0800 Message-Id: <20190219200242.17243-5-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219200242.17243-1-andrew.smirnov@gmail.com> References: <20190219200242.17243-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Convert various multi-bit fields to be defined using GENMASK/FIELD_PREP. This way bit field boundaries are defined in a single place only, as well as defined in a way that makes it easier to verify them against reference manual. No functional change intended. Signed-off-by: Andrey Smirnov Acked-by: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org --- drivers/pci/controller/dwc/pcie-designware.h | 29 +++++++++++--------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 070382869685..8ebfb06584d9 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -11,6 +11,7 @@ #ifndef _PCIE_DESIGNWARE_H #define _PCIE_DESIGNWARE_H +#include #include #include #include @@ -30,11 +31,12 @@ /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_LINK_CONTROL 0x710 -#define PORT_LINK_MODE_MASK (0x3f << 16) -#define PORT_LINK_MODE_1_LANES (0x1 << 16) -#define PORT_LINK_MODE_2_LANES (0x3 << 16) -#define PORT_LINK_MODE_4_LANES (0x7 << 16) -#define PORT_LINK_MODE_8_LANES (0xf << 16) +#define PORT_LINK_MODE_MASK GENMASK(21, 16) +#define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n) +#define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1) +#define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) +#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) +#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) #define PCIE_PORT_DEBUG0 0x728 #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f @@ -42,11 +44,12 @@ #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C #define PORT_LOGIC_SPEED_CHANGE BIT(17) -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) -#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) -#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) -#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) -#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) +#define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8) +#define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n) +#define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) +#define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2) +#define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) +#define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8) #define PCIE_MSI_ADDR_LO 0x820 #define PCIE_MSI_ADDR_HI 0x824 @@ -72,9 +75,9 @@ #define PCIE_ATU_UPPER_BASE 0x910 #define PCIE_ATU_LIMIT 0x914 #define PCIE_ATU_LOWER_TARGET 0x918 -#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) -#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) -#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) +#define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x) +#define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x) +#define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x) #define PCIE_ATU_UPPER_TARGET 0x91C #define PCIE_MISC_CONTROL_1_OFF 0x8BC From patchwork Tue Feb 19 20:02:42 2019 Content-Type: text/plain; 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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id e63sm31519622pfc.47.2019.02.19.12.04.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Feb 2019 12:04:20 -0800 (PST) From: Andrey Smirnov To: Lorenzo Pieralisi Cc: Andrey Smirnov , Gustavo Pimentel , Bjorn Helgaas , Fabio Estevam , Chris Healy , Lucas Stach , Leonard Crestez , "A.s. Dong" , Richard Zhu , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 5/5] PCI: dwc: Remove superfluous shifting in definitions Date: Tue, 19 Feb 2019 12:02:42 -0800 Message-Id: <20190219200242.17243-6-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190219200242.17243-1-andrew.smirnov@gmail.com> References: <20190219200242.17243-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Surrounding definitions no longer use explicit shift, so "<< 0" here serve no purpose. Remove them. No functional change intended. Signed-off-by: Andrey Smirnov Acked-by: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org --- drivers/pci/controller/dwc/pcie-designware.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 8ebfb06584d9..f6fb65a40f10 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -60,14 +60,14 @@ #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND BIT(31) #define PCIE_ATU_REGION_OUTBOUND 0 -#define PCIE_ATU_REGION_INDEX2 (0x2 << 0) -#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) -#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) +#define PCIE_ATU_REGION_INDEX2 0x2 +#define PCIE_ATU_REGION_INDEX1 0x1 +#define PCIE_ATU_REGION_INDEX0 0x0 #define PCIE_ATU_CR1 0x904 -#define PCIE_ATU_TYPE_MEM (0x0 << 0) -#define PCIE_ATU_TYPE_IO (0x2 << 0) -#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) -#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) +#define PCIE_ATU_TYPE_MEM 0x0 +#define PCIE_ATU_TYPE_IO 0x2 +#define PCIE_ATU_TYPE_CFG0 0x4 +#define PCIE_ATU_TYPE_CFG1 0x5 #define PCIE_ATU_CR2 0x908 #define PCIE_ATU_ENABLE BIT(31) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30)