From patchwork Fri Oct 20 10:29:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 828548 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FMRB/Sbd"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=verge.net.au header.i=@verge.net.au header.b="EDyOLioK"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yJMmm2v5sz9t32 for ; Fri, 20 Oct 2017 21:42:00 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=Qmq7/a/N4DN95gpoQdvkmhTQeYWxs5Yydxj2cjxG6X8=; b=FMRB/SbdkvSQ4J nFB4zMBMHCDk8iKezQ3UB+STov0iG0YI0/ksRW7b5tga1BH04Au4cRrwif0hBoSPQAC05VEWT1MVh eQY81BZQ4/Lg2xVkUmtBxYxJ6VlmJESvIC5XPLUC6rN329yXHLoLACIZO8eiA9Snw1Hp0AMAHB4Ib 7+if+6NU78GqFW4CX1h6QFqID7WamDvc9RybDcD9Q18QdwobjFj+D3QmprqAjN3PBE2XymYMw1Eoj QKkkuEEAOs0adXrywFzCKWpFggV2ClOx+59iYDXghevD8a9N0urzcTSA60vXHlKXGdNUoeMaDtTEu kZj6aUjKnbRZlDGtwEQw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1e5UkT-0002P6-O8; Fri, 20 Oct 2017 10:41:53 +0000 Received: from kirsty.vergenet.net ([202.4.237.240]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1e5Uf2-0003Ht-Qu for linux-arm-kernel@lists.infradead.org; Fri, 20 Oct 2017 10:36:20 +0000 Received: from penelope.horms.nl (unknown [217.111.208.18]) by kirsty.vergenet.net (Postfix) with ESMTPA id 09E8725BEDA; Fri, 20 Oct 2017 21:29:28 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1508495368; bh=90febUuICYHSefhLwQ1YvS0h5Cz3y187k17+cgcHgto=; h=From:To:Cc:Subject:Date:From; b=EDyOLioKTt5b0tE0qRue6FKGJMUvm1PhfQ8V2rScmb83TPiJ425NaciKyA03VYKu7 RY4g3eI0iEUVkP1uvpnAQ087dH13OqJM5QUrup/1nWQf2TTit89U33yB1iG07z7DoS LheOWU1WZAwSpMgY5iJB8iEEQbNyzGv1fNyqP654= Received: by penelope.horms.nl (Postfix, from userid 7100) id 94D24E2032C; Fri, 20 Oct 2017 12:29:08 +0200 (CEST) From: Simon Horman To: arm@kernel.org Subject: [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.15 Date: Fri, 20 Oct 2017 12:29:04 +0200 Message-Id: X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171020_033617_158731_0E7564B6 X-CRM114-Status: GOOD ( 20.30 ) X-Spam-Score: -4.3 (----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-4.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [202.4.237.240 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain 0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Arnd Bergmann , Kevin Hilman , Magnus Damm , linux-renesas-soc@vger.kernel.org, Olof Johansson , Simon Horman , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Hi Olof, Hi Kevin, Hi Arnd, Please consider these second round of Renesas ARM based SoC DT updates for v4.15. This pull request is based on the previous round of such requests, tagged as renesas-dt-for-v4.15, which you have already pulled. The following changes since commit 7031a219f649d12acda8a70a4b6b816ee123c8e2: ARM: dts: r8a7743: Add MSIOF[012] support (2017-09-28 08:02:04 +0200) are available in the git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-dt2-for-v4.15 for you to fetch changes up to b6d3b649441936621c87b79bff8dd436e2397e3c: ARM: dts: r8a7743: Add xhci support to SoC dtsi (2017-10-18 07:21:36 +0200) ---------------------------------------------------------------- Second Round of Renesas ARM Based SoC DT Updates for v4.15 * r8a77430 (RZ/G1M) SoC - Add XHCI support to SoC DT. Boards may enable this as appropriate * All Renesas ARM based SoCs - Add missing clocks for ARM CPU cores Geert Uytterhoeven says "This series improves DT hardware descriptions for Renesas arm32 SoCs by adding missing clocks properties to the device nodes corresponding to ARM CPU cores." * R-Car Gen 1 and 2, and RZ/G SoCs - Use R-Car Fallback compat strings for GPIO Simon Horman says "Use newly added R-Car GPIO Gen 1, 2 and 3 fallback compat strings in peace of now deprecated non-generation specific R-Car GPIO fallback compat string in the DT of Renesas ARM and arm64 based SoCs. As noted in the changelogs for the r8a777[89] changes, this introduces an incompatibility with pre-v4.14 kernels used with new DTBs. There is no run-time effect for other SoCs updated by this changeset." * r7s72100 (RZ/A1H) GR-Peach board - Add pin configuration subnode for ETHER pin group. This avoids relying on boot-loader configuration of these pins. - Enable ostm0 and ostm1 timers Jacopo Mondi says these are "to be used as clock source and clockevent source. The timers provides greater accuracy than the already enabled mtu2 one." - Correct leds node name indent - Enable MTU2 timer pulse unit Jacopo Mondi says "MTU2 multi-function/multi-channel timer/counter is not enabled for GR-Peach board. The timer is used as clock event source to schedule wake-ups, and without this enabled all sleeps not performed through busy waiting hang the board." * r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM - Add USB function support * r8a7745 (RZ/G1E) iW-RainboW-G22D development platform - Add USB2.0 Host support * r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven development platform - Rework DT architecture and add DT for camera DB Fabrizio Castro says "Some of the serial interfaces are exposed on the camera daughter board. The camera daughter board can be connected to the carrier board by means of expansion connectors 1, 2 and 3. The carrier board may host an RZ/G1M or an RZ/G1N based SoM. While adding support for the serial interfaces on the camera daughter board we faced the dilemma of how to properly describe all of the possible HW configurations and how to maximize code reuse. The best option would be to use device tree overlays, however there is still some work to be done on that front before actually using them, therefore for the time being we decided to provide .dtsi files to describe the carrier board and the camera daughter board, and provide .dts files to describe the HW configurations we need to support." * r8a779[0-4] R-Car Gen2 SoCs - Use generic node name for VSP1 nodes Geert Uytterhoeven says "This patch series replaces the specific node names used for the VSP1 nodes by the preferred generic node names, cfr. commit 0e1bfb72b076b07d ("v4l: vsp1: Use generic node name")." ---------------------------------------------------------------- Biju Das (9): ARM: dts: r8a7745: Add internal PCI bridge nodes ARM: dts: r8a7745: Add USB PHY DT support ARM: dts: r8a7745: Link PCI USB devices to USB PHY ARM: dts: iwg22d-sodimm: Enable internal PCI ARM: dts: iwg22d-sodimm: Enable USB PHY ARM: dts: r8a7743: Add HS-USB device node ARM: dts: iwg20d-q7: Enable HS-USB ARM: dts: r8a7743: Add USB-DMAC device nodes ARM: dts: r8a7743: Enable DMA for HSUSB Dietmar Eggemann (1): ARM: dts: r8a7790: add cpu capacity-dmips-mhz information Fabrizio Castro (3): ARM: dts: iwg20d-q7: Rework DT architecture ARM: dts: iwg20d-q7-dbcm-ca: Add device trees for camera DB ARM: dts: r8a7743: Add xhci support to SoC dtsi Geert Uytterhoeven (17): ARM: dts: r8a7790: Use generic node name for VSP1 nodes ARM: dts: r8a7791: Use generic node name for VSP1 nodes ARM: dts: r8a7792: Use generic node name for VSP1 nodes ARM: dts: r8a7794: Use generic node name for VSP1 nodes ARM: dts: r8a73a4: Add clock for CA15 CPU0 core ARM: dts: r8a7743: Add missing clock for secondary CA15 CPU core ARM: dts: r8a7778: Add clock for CA9 CPU core ARM: dts: r8a7779: Add clocks for CA9 CPU cores ARM: dts: r8a7790: Add missing clocks for secondary CA15 CPU cores ARM: dts: r8a7790: Add clocks for CA7 CPU cores ARM: dts: r8a7791: Add missing clock for secondary CA15 CPU core ARM: dts: r8a7792: Add missing clock for secondary CA15 CPU core ARM: dts: r8a7793: Add missing clock for secondary CA15 CPU core ARM: dts: r8a7794: Add missing clock for secondary CA7 CPU core ARM: dts: sh73a0: Add clocks for CA9 CPU cores dt-bindings: clk: r7s72100: Add missing I and G clocks ARM: dts: r7s72100: Add clock for CA9 CPU core Jacopo Mondi (4): ARM: dts: gr-peach: Fix 'leds' node name indent ARM: dts: gr-peach: Enable MTU2 timer pulse unit ARM: dts: gr-peach: Add ETHER pin group ARM: dts: gr-peach: Enable ostm0 and ostm1 timers Simon Horman (8): ARM: dts: r8a7778: Use R-Car GPIO Gen1 fallback compat string ARM: dts: r8a7779: Use R-Car GPIO Gen1 fallback compat string ARM: dts: r8a7743: Use R-Car GPIO Gen2 fallback compat string ARM: dts: r8a7790: Use R-Car GPIO Gen2 fallback compat string ARM: dts: r8a7791: Use R-Car GPIO Gen2 fallback compat string ARM: dts: r8a7792: Use R-Car GPIO Gen2 fallback compat string ARM: dts: r8a7793: Use R-Car GPIO Gen2 fallback compat string ARM: dts: r8a7794: Use R-Car GPIO Gen2 fallback compat string arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/iwg20d-q7-common.dtsi | 152 ++++++++++++++++++++++++ arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi | 43 +++++++ arch/arm/boot/dts/r7s72100-gr-peach.dts | 53 ++++++++- arch/arm/boot/dts/r7s72100.dtsi | 1 + arch/arm/boot/dts/r8a73a4.dtsi | 1 + arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts | 19 +++ arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 139 +--------------------- arch/arm/boot/dts/r8a7743.dtsi | 82 +++++++++++-- arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 15 +++ arch/arm/boot/dts/r8a7745.dtsi | 92 ++++++++++++++ arch/arm/boot/dts/r8a7778.dtsi | 11 +- arch/arm/boot/dts/r8a7779.dtsi | 18 +-- arch/arm/boot/dts/r8a7790.dtsi | 35 ++++-- arch/arm/boot/dts/r8a7791.dtsi | 23 ++-- arch/arm/boot/dts/r8a7792.dtsi | 31 ++--- arch/arm/boot/dts/r8a7793.dtsi | 17 +-- arch/arm/boot/dts/r8a7794.dtsi | 19 +-- arch/arm/boot/dts/sh73a0.dtsi | 2 + include/dt-bindings/clock/r7s72100-clock.h | 2 + 20 files changed, 545 insertions(+), 211 deletions(-) create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi create mode 100644 arch/arm/boot/dts/iwg20d-q7-dbcm-ca.dtsi create mode 100644 arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dts From patchwork Fri Oct 20 10:28:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 828551 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="MdmXC2cX"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=verge.net.au header.i=@verge.net.au header.b="B8zfTWqO"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yJMvq1b3jz9t6J for ; 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Fri, 20 Oct 2017 10:47:59 +0000 Received: from kirsty.vergenet.net ([202.4.237.240]) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1e5Ug6-0003Ht-5L for linux-arm-kernel@lists.infradead.org; Fri, 20 Oct 2017 10:37:46 +0000 Received: from penelope.horms.nl (unknown [217.111.208.18]) by kirsty.vergenet.net (Postfix) with ESMTPA id 3704325BEFA; Fri, 20 Oct 2017 21:29:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1508495385; bh=d9ITX4Sg108EKe/N7RfQLHtwhf/FloPjiumqhic2Jz4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B8zfTWqO3ZHsi1u+T3sdMGTVAXbv22RIpQb0ng1NVuNaOsRB2Qr9WBrHFmWZDgO0o DfIdhQIwmMk7Ix8aC4CWx9cSi+0Kkhc52lgWAQw2VuI3Y0fIjOPbb+EbmiTd05K8P+ 5Z+WfDMxfvDchVR86Vb8iRuN9XoqVsO764nuqmNw= Received: by penelope.horms.nl (Postfix, from userid 7100) id 3B8FFE20364; Fri, 20 Oct 2017 12:29:11 +0200 (CEST) From: Simon Horman To: linux-renesas-soc@vger.kernel.org Subject: [PATCH 07/42] ARM: dts: iwg20d-q7: Rework DT architecture Date: Fri, 20 Oct 2017 12:28:34 +0200 Message-Id: <4f0b2563c4c0c67fc5b5e2369d5f62f91abc42e7.1508493785.git.horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171020_033723_223522_6FDF58D7 X-CRM114-Status: GOOD ( 14.91 ) X-Spam-Score: -4.3 (----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-4.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [202.4.237.240 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain 0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fabrizio Castro , Simon Horman , Chris Paterson , Magnus Damm , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Fabrizio Castro Since the same carrier board may host RZ/G1M and RZ/G1N based Systems on Module, the DT architecture for iwg20d-q7 needs better decoupling. This patch provides: * iwg20d-q7-common.dtsi - its purpose is to define the carrier board definitions, and its content is basically the same as the previous version of r8a7743-iwg20d-q7.dts, only it has no reference to the SoM .dtsi, and that's why the filename doesn't mention the SoC name any more. * r8a7743-iwg20d-q7.dts - its new purpose is to put together the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board .dtsi defined by this very patch, along with "model" and "compatible" properties. The final DT architecture to describe the board is now: r8a7743-iwg20d-q7.dts # Carrier Board + SoM ├── r8a7743-iwg20m.dtsi # SoM │   └── r8a7743.dtsi # SoC └── iwg20d-q7-common.dtsi # Carrier Board and maximizes the reuse of the definitions for the carrier board and for the SoM. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/iwg20d-q7-common.dtsi | 147 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 139 +----------------------------- 2 files changed, 149 insertions(+), 137 deletions(-) create mode 100644 arch/arm/boot/dts/iwg20d-q7-common.dtsi diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi new file mode 100644 index 000000000000..1c072c0a4888 --- /dev/null +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -0,0 +1,147 @@ +/* + * Device Tree Source for the iWave-RZ/G1M/G1N Qseven carrier board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/ { + aliases { + serial0 = &scif0; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + reg = <3>; + micrel,led-mode = <1>; + }; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + }; +}; + +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; + +&pfc { + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + + scif0_pins: scif0 { + groups = "scif0_data_d"; + function = "scif0"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 0136864bc595..6aa6b7467704 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for the iWave-RZG1M Qseven carrier board + * Device Tree Source for the iWave-RZ/G1M Qseven board * * Copyright (C) 2017 Renesas Electronics Corp. * @@ -10,144 +10,9 @@ /dts-v1/; #include "r8a7743-iwg20m.dtsi" +#include "iwg20d-q7-common.dtsi" / { model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M"; compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743"; - - aliases { - serial0 = &scif0; - ethernet0 = &avb; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; - stdout-path = "serial0:115200n8"; - }; - - vcc_sdhi1: regulator-vcc-sdhi1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI1 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&gpio1 16 GPIO_ACTIVE_LOW>; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; - gpios-states = <1>; - states = <3300000 1 - 1800000 0>; - }; -}; - -&pfc { - i2c2_pins: i2c2 { - groups = "i2c2"; - function = "i2c2"; - }; - - scif0_pins: scif0 { - groups = "scif0_data_d"; - function = "scif0"; - }; - - avb_pins: avb { - groups = "avb_mdio", "avb_gmii"; - function = "avb"; - }; - - sdhi1_pins: sd1 { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <3300>; - }; - - sdhi1_pins_uhs: sd1_uhs { - groups = "sdhi1_data4", "sdhi1_ctrl"; - function = "sdhi1"; - power-source = <1800>; - }; - - usb0_pins: usb0 { - groups = "usb0"; - function = "usb0"; - }; - - usb1_pins: usb1 { - groups = "usb1"; - function = "usb1"; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&avb { - pinctrl-0 = <&avb_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy3>; - phy-mode = "gmii"; - renesas,no-ether-link; - status = "okay"; - - phy3: ethernet-phy@3 { - reg = <3>; - micrel,led-mode = <1>; - }; -}; - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&vcc_sdhi1>; - vqmmc-supply = <&vccq_sdhi1>; - cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - sd-uhs-sdr50; - status = "okay"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - rtc@68 { - compatible = "ti,bq32000"; - reg = <0x68>; - }; -}; - -&pci0 { - status = "okay"; - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; -}; - -&pci1 { - status = "okay"; - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; -}; - -&usbphy { - status = "okay"; }; From patchwork Fri Oct 20 10:28:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 828555 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="nvCfG0tC"; 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Fri, 20 Oct 2017 12:29:11 +0200 (CEST) From: Simon Horman To: linux-renesas-soc@vger.kernel.org Subject: [PATCH 09/42] ARM: dts: r8a7790: add cpu capacity-dmips-mhz information Date: Fri, 20 Oct 2017 12:28:36 +0200 Message-Id: <5bdc81259bb0efd5bd71820ef15757b70beae751.1508493785.git.horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171020_033701_996983_A9F6B6EB X-CRM114-Status: UNSURE ( 7.88 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -4.3 (----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-4.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [202.4.237.240 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain 0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Simon Horman , Magnus Damm , Dietmar Eggemann , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Dietmar Eggemann The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived form the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex™-A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platform is affected once cpu-invariant accounting support is re-connected to the task scheduler: r8a7790-lager Signed-off-by: Dietmar Eggemann Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 17a48199b7a9..92b7f3bd8b69 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -56,6 +56,7 @@ clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; /* kHz - uV - OPPs unknown yet */ operating-points = <1400000 1000000>, @@ -73,6 +74,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu2: cpu@2 { @@ -82,6 +84,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu3: cpu@3 { @@ -91,6 +94,7 @@ clock-frequency = <1300000000>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; }; cpu4: cpu@100 { @@ -100,6 +104,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu5: cpu@101 { @@ -109,6 +114,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu6: cpu@102 { @@ -118,6 +124,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU2>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; cpu7: cpu@103 { @@ -127,6 +134,7 @@ clock-frequency = <780000000>; power-domains = <&sysc R8A7790_PD_CA7_CPU3>; next-level-cache = <&L2_CA7>; + capacity-dmips-mhz = <539>; }; L2_CA15: cache-controller-0 {