From patchwork Mon Feb 18 18:36:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044233 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496524-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="fa9ifowI"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="l6Apkp0n"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CJp0SQWz9sCh for ; Tue, 19 Feb 2019 05:37:13 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=wIg f4bjzndAc8JCb6GLcX3UDIdIvjukaE0mquuAdM5MyhHDF0nuWYFltal7d1ocOwB5 U8n8yd0XzObxiWo2PxjrrCUDJkrJAP3He7qfv1PxdGJZNIU9z6UGnyX+7NjHj9tf mRHuDwm1x9tMLrywib0pou/lTRICkwRdmGJbBL8k= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=6MmDLLkdA N/x6qoD1tJDUyIpQpo=; b=fa9ifowIT6SbkAP/0wehZwqPCJ7nmASa/TB9W2/Dz bKKNIazwnGhnoMLs4pPQFjuVuBGQd/8UgVQJ3Sil157Xzun6Vr+T571y5APnz8Mx y9P5Q37hvxJ08Jc7pXMR5YDP53wGDqCXhuauPf3tblOntqQ4KIdeIoSKf+awCCHM 9E= Received: (qmail 58623 invoked by alias); 18 Feb 2019 18:37:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 58427 invoked by uid 89); 18 Feb 2019 18:37:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Hx-spam-relays-external:209.85.215.195 X-HELO: mail-pg1-f195.google.com Received: from mail-pg1-f195.google.com (HELO mail-pg1-f195.google.com) (209.85.215.195) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:02 +0000 Received: by mail-pg1-f195.google.com with SMTP id u9so5345821pgo.7 for ; Mon, 18 Feb 2019 10:37:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9d5VnGJUi05gsFI4s1QYixnHpzLtRSruIIsnIomzvoc=; b=l6Apkp0niONtvOYuX6dF7PLJO16glT3UTZZyJaMKE5o2Y2IiUO0FZ5tsqT4/J3CgUf cW5XaZO0DT5xUC8aQpJ8Yshk9LY1YkmY9R9pNY1J6SMYyxeGuDgnhef40CHI9NY99MmE TD2Ht9eyfrtXqcRX70pW/2XgLkJulWUCa9A8GjAzt5s5o8x20iXc8Nw8VyHSucw42SL6 UtFSSFQXNkaZKo6POwwTGNSfqMoeWwL1AmQahhlSmLDKstShLLcWWyQmt0Vu+W5NAYNn EFroQUmWHlbtEZMwCiwolAdXZtfG//+l2YtbMO3uu8C7hHdJ0Cm0Y7jSXjLZPHqdo8cv EiTw== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id f67sm28622021pfc.141.2019.02.18.10.36.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:36:58 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 70B0FC02CF; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 01/41] i386: Allow MMX register modes in SSE registers Date: Mon, 18 Feb 2019 10:36:17 -0800 Message-Id: <20190218183657.16296-2-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes In 64-bit mode, SSE2 can be used to emulate MMX instructions without 3DNOW. We can use SSE2 to support MMX register modes. PR target/89021 * config/i386/i386-c.c (ix86_target_macros_internal): Define __MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE. * config/i386/i386.c (ix86_set_reg_reg_cost): Add support for TARGET_MMX_WITH_SSE with VALID_MMX_REG_MODE. (ix86_vector_mode_supported_p): Likewise. * config/i386/i386.h (TARGET_MMX_WITH_SSE): New. --- gcc/config/i386/i386-c.c | 2 ++ gcc/config/i386/i386.c | 5 +++-- gcc/config/i386/i386.h | 2 ++ 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 5e7e46fcebe..213e1b56c6b 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -548,6 +548,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__CLDEMOTE__"); if (isa_flag2 & OPTION_MASK_ISA_PTWRITE) def_or_undef (parse_in, "__PTWRITE__"); + if (TARGET_MMX_WITH_SSE) + def_or_undef (parse_in, "__MMX_WITH_SSE__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 0df792a41d1..eb642165264 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -40503,7 +40503,8 @@ ix86_set_reg_reg_cost (machine_mode mode) || (TARGET_AVX && VALID_AVX256_REG_MODE (mode)) || (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode)) || (TARGET_SSE && VALID_SSE_REG_MODE (mode)) - || (TARGET_MMX && VALID_MMX_REG_MODE (mode))) + || ((TARGET_MMX || TARGET_MMX_WITH_SSE) + && VALID_MMX_REG_MODE (mode))) units = GET_MODE_SIZE (mode); } @@ -44329,7 +44330,7 @@ ix86_vector_mode_supported_p (machine_mode mode) return true; if (TARGET_AVX512F && VALID_AVX512F_REG_MODE (mode)) return true; - if (TARGET_MMX && VALID_MMX_REG_MODE (mode)) + if ((TARGET_MMX ||TARGET_MMX_WITH_SSE) && VALID_MMX_REG_MODE (mode)) return true; if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode)) return true; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 4fd8bc40a34..91b233022c2 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -201,6 +201,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_16BIT TARGET_CODE16 #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) +#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) + #include "config/vxworks-dummy.h" #include "config/i386/i386-opts.h" From patchwork Mon Feb 18 18:36:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496526-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="M3RR4UIR"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="oEUFbNuh"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CKK11Z0z9rxp for ; Tue, 19 Feb 2019 05:37:40 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=KzG LrWcP0IWV3iq0uOCgmtlpvTebV6H3sAjXj2iE359P2gK8GX6ShVjVz+nEwP3K1Aj X/B7euejRfFFh/h+H4b/FJLx5HEit8k0Vm5alzvE1MJ0t93LFK6ZFe5tAJ3otOHB OUaI2ksHkwR58ZUFjF52NKGezJqlxvTmxBJOF1cs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=cLAvYkClT kV+YxB+WIzYoUbencg=; b=M3RR4UIRWnUu2H6YGPdFs+oaPvqEGczkJotMW8Wdw lAwxc0EidO/UwT7NVdTVtkm68Yw6Df2sbB13FnO/eTqjeiCDP6313ORx1xTZF2ac nLoBwTJNSBgJ5uY+ZgBxE4ciChDtdksZnnUBFgYNOROfwl6TfV/aSLPZGeMSwR44 OM= Received: (qmail 59048 invoked by alias); 18 Feb 2019 18:37:06 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 58918 invoked by uid 89); 18 Feb 2019 18:37:06 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.4 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pl1-f174.google.com Received: from mail-pl1-f174.google.com (HELO mail-pl1-f174.google.com) (209.85.214.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:03 +0000 Received: by mail-pl1-f174.google.com with SMTP id q3so1766749pll.4 for ; Mon, 18 Feb 2019 10:37:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OpHGD5Wv20XHAP+KORWduJhrM+IhI3AdlQ8Bpckb/60=; b=oEUFbNuh8voKKWXq/uMyDStANaLXzMguPAA9Gk4F5ycWtQs4w0HQBifJnHR9Du1w6/ 3mf5TJB/eMhMVWypxhPJ0VTpa3KWE3OhNHuqJaGYan2CPiL0HxwyT9MQfzBSw99LrnUb gxoXkqhzXfl+VK6a4j3TWgFMOdXp5XhVtoIefbXnsIKQFGCBGIm3HUnrTgcwK5D7I1se ESP+xscP1rXV9tCP0mVRcqSh4yFpT7eymle3llB8uLkjFuDeuDxjAzxOvEdW3QaQjZsG W1uZ4xV1/9N/42Uhj0OjECIKhbCGQ3PUcJegNMIgE+2PyjgYI+KlsFFIlV4+4h3mPgdU 8Abg== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id q7sm32746746pfa.119.2019.02.18.10.36.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:36:58 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 7BEF4C0323; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 02/41] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 Date: Mon, 18 Feb 2019 10:36:18 -0800 Message-Id: <20190218183657.16296-3-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. 2019-02-08 H.J. Lu Uros Bizjak PR target/89021 * config/i386/i386-protos.h (ix86_move_vector_high_sse_to_mmx): New prototype. (ix86_split_mmx_pack): Likewise. * config/i386/i386.c (ix86_move_vector_high_sse_to_mmx): New function. (ix86_split_mmx_pack): Likewise. * config/i386/i386.md (mmx_isa): New. (enabled): Also check mmx_isa. * config/i386/mmx.md (any_s_truncate): New code iterator. (s_trunsuffix): New code attr. (mmx_packsswb): Removed. (mmx_packssdw): Likewise. (mmx_packuswb): Likewise. (mmx_packswb): New define_insn_and_split to emulate MMX packsswb/packuswb with SSE2. (mmx_packssdw): Likewise. * config/i386/predicates.md (register_mmxmem_operand): New. --- gcc/config/i386/i386-protos.h | 3 ++ gcc/config/i386/i386.c | 54 ++++++++++++++++++++++++++++ gcc/config/i386/i386.md | 13 +++++++ gcc/config/i386/mmx.md | 67 +++++++++++++++++++---------------- gcc/config/i386/predicates.md | 7 ++++ 5 files changed, 114 insertions(+), 30 deletions(-) diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index 27f5cc13abf..a53b48438ec 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -202,6 +202,9 @@ extern void ix86_expand_vecop_qihi (enum rtx_code, rtx, rtx, rtx); extern rtx ix86_split_stack_guard (void); +extern void ix86_move_vector_high_sse_to_mmx (rtx); +extern void ix86_split_mmx_pack (rtx[], enum rtx_code); + #ifdef TREE_CODE extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int); #endif /* TREE_CODE */ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index eb642165264..563bc9aec69 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -20221,6 +20221,60 @@ ix86_expand_vector_move_misalign (machine_mode mode, rtx operands[]) gcc_unreachable (); } +/* Move bits 64:95 to bits 32:63. */ + +void +ix86_move_vector_high_sse_to_mmx (rtx op) +{ + rtx mask = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (4, GEN_INT (0), GEN_INT (2), + GEN_INT (0), GEN_INT (0))); + rtx dest = lowpart_subreg (V4SImode, op, GET_MODE (op)); + op = gen_rtx_VEC_SELECT (V4SImode, dest, mask); + rtx insn = gen_rtx_SET (dest, op); + emit_insn (insn); +} + +/* Split MMX pack with signed/unsigned saturation with SSE/SSE2. */ + +void +ix86_split_mmx_pack (rtx operands[], enum rtx_code code) +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + + machine_mode dmode = GET_MODE (op0); + machine_mode smode = GET_MODE (op1); + machine_mode inner_dmode = GET_MODE_INNER (dmode); + machine_mode inner_smode = GET_MODE_INNER (smode); + + /* Get the corresponding SSE mode for destination. */ + int nunits = 16 / GET_MODE_SIZE (inner_dmode); + machine_mode sse_dmode = mode_for_vector (GET_MODE_INNER (dmode), + nunits).require (); + machine_mode sse_half_dmode = mode_for_vector (GET_MODE_INNER (dmode), + nunits / 2).require (); + + /* Get the corresponding SSE mode for source. */ + nunits = 16 / GET_MODE_SIZE (inner_smode); + machine_mode sse_smode = mode_for_vector (GET_MODE_INNER (smode), + nunits).require (); + + /* Generate SSE pack with signed/unsigned saturation. */ + rtx dest = lowpart_subreg (sse_dmode, op0, GET_MODE (op0)); + op1 = lowpart_subreg (sse_smode, op1, GET_MODE (op1)); + op2 = lowpart_subreg (sse_smode, op2, GET_MODE (op2)); + + op1 = gen_rtx_fmt_e (code, sse_half_dmode, op1); + op2 = gen_rtx_fmt_e (code, sse_half_dmode, op2); + rtx insn = gen_rtx_SET (dest, gen_rtx_VEC_CONCAT (sse_dmode, + op1, op2)); + emit_insn (insn); + + ix86_move_vector_high_sse_to_mmx (op0); +} + /* Helper function of ix86_fixup_binary_operands to canonicalize operand order. Returns true if the operands should be swapped. */ diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 240384917df..04ec0eeaa57 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -792,6 +792,10 @@ avx512vl,noavx512vl,x64_avx512dq,x64_avx512bw" (const_string "base")) +;; Define instruction set of MMX instructions +(define_attr "mmx_isa" "base,native,x64,x64_noavx,x64_avx" + (const_string "base")) + (define_attr "enabled" "" (cond [(eq_attr "isa" "x64") (symbol_ref "TARGET_64BIT") (eq_attr "isa" "x64_sse2") @@ -830,6 +834,15 @@ (eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ") (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL") (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL") + + (eq_attr "mmx_isa" "native") + (symbol_ref "!TARGET_MMX_WITH_SSE") + (eq_attr "mmx_isa" "x64") + (symbol_ref "TARGET_MMX_WITH_SSE") + (eq_attr "mmx_isa" "x64_avx") + (symbol_ref "TARGET_MMX_WITH_SSE && TARGET_AVX") + (eq_attr "mmx_isa" "x64_noavx") + (symbol_ref "TARGET_MMX_WITH_SSE && !TARGET_AVX") ] (const_int 1))) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 57060b9d233..63a390923b6 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1021,41 +1021,48 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn "mmx_packsswb" - [(set (match_operand:V8QI 0 "register_operand" "=y") +;; Used in signed and unsigned truncations with saturation. +(define_code_iterator any_s_truncate [ss_truncate us_truncate]) +;; Instruction suffix for truncations with saturation. +(define_code_attr s_trunsuffix [(ss_truncate "s") (us_truncate "u")]) + +(define_insn_and_split "mmx_packswb" + [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv") (vec_concat:V8QI - (ss_truncate:V4QI - (match_operand:V4HI 1 "register_operand" "0")) - (ss_truncate:V4QI - (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))] - "TARGET_MMX" - "packsswb\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxshft") - (set_attr "mode" "DI")]) + (any_s_truncate:V4QI + (match_operand:V4HI 1 "register_operand" "0,0,Yv")) + (any_s_truncate:V4QI + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv"))))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + packswb\t{%2, %0|%0, %2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] + "ix86_split_mmx_pack (operands, ); DONE;" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxshft,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) -(define_insn "mmx_packssdw" - [(set (match_operand:V4HI 0 "register_operand" "=y") +(define_insn_and_split "mmx_packssdw" + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (vec_concat:V4HI (ss_truncate:V2HI - (match_operand:V2SI 1 "register_operand" "0")) + (match_operand:V2SI 1 "register_operand" "0,0,Yv")) (ss_truncate:V2HI - (match_operand:V2SI 2 "nonimmediate_operand" "ym"))))] - "TARGET_MMX" - "packssdw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxshft") - (set_attr "mode" "DI")]) - -(define_insn "mmx_packuswb" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (vec_concat:V8QI - (us_truncate:V4QI - (match_operand:V4HI 1 "register_operand" "0")) - (us_truncate:V4QI - (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))] - "TARGET_MMX" - "packuswb\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxshft") - (set_attr "mode" "DI")]) + (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + packssdw\t{%2, %0|%0, %2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] + "ix86_split_mmx_pack (operands, SS_TRUNCATE); DONE;" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxshft,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_punpckhbw" [(set (match_operand:V8QI 0 "register_operand" "=y") diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 99226e86436..f3c2f72de54 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -49,6 +49,13 @@ (and (match_code "reg") (match_test "MMX_REGNO_P (REGNO (op))"))) +;; Match register operands, but include memory operands for +;; !TARGET_MMX_WITH_SSE. +(define_predicate "register_mmxmem_operand" + (ior (match_operand 0 "register_operand") + (and (not (match_test "TARGET_MMX_WITH_SSE")) + (match_operand 0 "memory_operand")))) + ;; True if the operand is an SSE register. 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[73.93.86.59]) by smtp.gmail.com with ESMTPSA id y21sm16989320pfe.57.2019.02.18.10.36.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:36:58 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 86A8EC032A; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 03/41] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX Date: Mon, 18 Feb 2019 10:36:19 -0800 Message-Id: <20190218183657.16296-4-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX, move bits 64:127 to bits 0:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/i386-protos.h (ix86_split_mmx_punpck): New prototype. * config/i386/i386.c (ix86_split_mmx_punpck): New function. * config/i386/mmx.m (mmx_punpckhbw): Changed to define_insn_and_split to support SSE emulation. (mmx_punpcklbw): Likewise. (mmx_punpckhwd): Likewise. (mmx_punpcklwd): Likewise. (mmx_punpckhdq): Likewise. (mmx_punpckldq): Likewise. --- gcc/config/i386/i386-protos.h | 1 + gcc/config/i386/i386.c | 77 +++++++++++++++++++ gcc/config/i386/mmx.md | 138 ++++++++++++++++++++++------------ 3 files changed, 168 insertions(+), 48 deletions(-) diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index a53b48438ec..37581837a32 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -204,6 +204,7 @@ extern rtx ix86_split_stack_guard (void); extern void ix86_move_vector_high_sse_to_mmx (rtx); extern void ix86_split_mmx_pack (rtx[], enum rtx_code); +extern void ix86_split_mmx_punpck (rtx[], bool); #ifdef TREE_CODE extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 563bc9aec69..3db41555462 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -20275,6 +20275,83 @@ ix86_split_mmx_pack (rtx operands[], enum rtx_code code) ix86_move_vector_high_sse_to_mmx (op0); } +/* Split MMX punpcklXX/punpckhXX with SSE punpcklXX. */ + +void +ix86_split_mmx_punpck (rtx operands[], bool high_p) +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + machine_mode mode = GET_MODE (op0); + rtx mask; + /* The corresponding SSE mode. */ + machine_mode sse_mode, double_sse_mode; + + switch (mode) + { + case E_V8QImode: + sse_mode = V16QImode; + double_sse_mode = V32QImode; + mask = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (16, + GEN_INT (0), GEN_INT (16), + GEN_INT (1), GEN_INT (17), + GEN_INT (2), GEN_INT (18), + GEN_INT (3), GEN_INT (19), + GEN_INT (4), GEN_INT (20), + GEN_INT (5), GEN_INT (21), + GEN_INT (6), GEN_INT (22), + GEN_INT (7), GEN_INT (23))); + break; + + case E_V4HImode: + sse_mode = V8HImode; + double_sse_mode = V16HImode; + mask = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (8, + GEN_INT (0), GEN_INT (8), + GEN_INT (1), GEN_INT (9), + GEN_INT (2), GEN_INT (10), + GEN_INT (3), GEN_INT (11))); + break; + + case E_V2SImode: + sse_mode = V4SImode; + double_sse_mode = V8SImode; + mask = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (4, + GEN_INT (0), GEN_INT (4), + GEN_INT (1), GEN_INT (5))); + break; + + default: + gcc_unreachable (); + } + + /* Generate SSE punpcklXX. */ + rtx dest = lowpart_subreg (sse_mode, op0, GET_MODE (op0)); + op1 = lowpart_subreg (sse_mode, op1, GET_MODE (op1)); + op2 = lowpart_subreg (sse_mode, op2, GET_MODE (op2)); + + op1 = gen_rtx_VEC_CONCAT (double_sse_mode, op1, op2); + op2 = gen_rtx_VEC_SELECT (sse_mode, op1, mask); + rtx insn = gen_rtx_SET (dest, op2); + emit_insn (insn); + + if (high_p) + { + /* Move bits 64:127 to bits 0:63. */ + mask = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (4, GEN_INT (2), GEN_INT (3), + GEN_INT (0), GEN_INT (0))); + dest = lowpart_subreg (V4SImode, dest, GET_MODE (dest)); + op1 = gen_rtx_VEC_SELECT (V4SImode, dest, mask); + insn = gen_rtx_SET (dest, op1); + emit_insn (insn); + } +} + /* Helper function of ix86_fixup_binary_operands to canonicalize operand order. Returns true if the operands should be swapped. */ diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 63a390923b6..0aa793395fb 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1064,87 +1064,129 @@ (set_attr "type" "mmxshft,sselog,sselog") (set_attr "mode" "DI,TI,TI")]) -(define_insn "mmx_punpckhbw" - [(set (match_operand:V8QI 0 "register_operand" "=y") +(define_insn_and_split "mmx_punpckhbw" + [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv") (vec_select:V8QI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "0") - (match_operand:V8QI 2 "nonimmediate_operand" "ym")) + (match_operand:V8QI 1 "register_operand" "0,0,Yv") + (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")) (parallel [(const_int 4) (const_int 12) (const_int 5) (const_int 13) (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))] - "TARGET_MMX" - "punpckhbw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxcvt") - (set_attr "mode" "DI")]) + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + punpckhbw\t{%2, %0|%0, %2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] + "ix86_split_mmx_punpck (operands, true); DONE;" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcvt,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) -(define_insn "mmx_punpcklbw" - [(set (match_operand:V8QI 0 "register_operand" "=y") +(define_insn_and_split "mmx_punpcklbw" + [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv") (vec_select:V8QI (vec_concat:V16QI - (match_operand:V8QI 1 "register_operand" "0") - (match_operand:V8QI 2 "nonimmediate_operand" "ym")) + (match_operand:V8QI 1 "register_operand" "0,0,Yv") + (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")) (parallel [(const_int 0) (const_int 8) (const_int 1) (const_int 9) (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))] - "TARGET_MMX" - "punpcklbw\t{%2, %0|%0, %k2}" - [(set_attr "type" "mmxcvt") - (set_attr "mode" "DI")]) + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + punpcklbw\t{%2, %0|%0, %k2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] + "ix86_split_mmx_punpck (operands, false); DONE;" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcvt,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) -(define_insn "mmx_punpckhwd" - [(set (match_operand:V4HI 0 "register_operand" "=y") +(define_insn_and_split "mmx_punpckhwd" + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (vec_select:V4HI (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "0") - (match_operand:V4HI 2 "nonimmediate_operand" "ym")) + (match_operand:V4HI 1 "register_operand" "0,0,Yv") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] - "TARGET_MMX" - "punpckhwd\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxcvt") - (set_attr "mode" "DI")]) + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + punpckhwd\t{%2, %0|%0, %2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] + "ix86_split_mmx_punpck (operands, true); DONE;" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcvt,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) -(define_insn "mmx_punpcklwd" - [(set (match_operand:V4HI 0 "register_operand" "=y") +(define_insn_and_split "mmx_punpcklwd" + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (vec_select:V4HI (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "0") - (match_operand:V4HI 2 "nonimmediate_operand" "ym")) + (match_operand:V4HI 1 "register_operand" "0,0,Yv") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] - "TARGET_MMX" - "punpcklwd\t{%2, %0|%0, %k2}" - [(set_attr "type" "mmxcvt") - (set_attr "mode" "DI")]) + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + punpcklwd\t{%2, %0|%0, %k2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] + "ix86_split_mmx_punpck (operands, false); DONE;" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcvt,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) -(define_insn "mmx_punpckhdq" - [(set (match_operand:V2SI 0 "register_operand" "=y") +(define_insn_and_split "mmx_punpckhdq" + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv") (vec_select:V2SI (vec_concat:V4SI - (match_operand:V2SI 1 "register_operand" "0") - (match_operand:V2SI 2 "nonimmediate_operand" "ym")) + (match_operand:V2SI 1 "register_operand" "0,0,Yv") + (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")) (parallel [(const_int 1) (const_int 3)])))] - "TARGET_MMX" - "punpckhdq\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxcvt") - (set_attr "mode" "DI")]) + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + punpckhdq\t{%2, %0|%0, %2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] + "ix86_split_mmx_punpck (operands, true); DONE;" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcvt,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) -(define_insn "mmx_punpckldq" - [(set (match_operand:V2SI 0 "register_operand" "=y") +(define_insn_and_split "mmx_punpckldq" + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv") (vec_select:V2SI (vec_concat:V4SI - (match_operand:V2SI 1 "register_operand" "0") - (match_operand:V2SI 2 "nonimmediate_operand" "ym")) + (match_operand:V2SI 1 "register_operand" "0,0,Yv") + (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")) (parallel [(const_int 0) (const_int 2)])))] - "TARGET_MMX" - "punpckldq\t{%2, %0|%0, %k2}" - [(set_attr "type" "mmxcvt") - (set_attr "mode" "DI")]) + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + punpckldq\t{%2, %0|%0, %k2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] + "ix86_split_mmx_punpck (operands, false); DONE;" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcvt,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_pinsrw" [(set (match_operand:V4HI 0 "register_operand") From patchwork Mon Feb 18 18:36:20 2019 Content-Type: text/plain; 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[73.93.86.59]) by smtp.gmail.com with ESMTPSA id i8sm27838292pfj.18.2019.02.18.10.36.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:36:58 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 91AEEC032B; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 04/41] i386: Emulate MMX plusminus/sat_plusminus with SSE Date: Mon, 18 Feb 2019 10:36:20 -0800 Message-Id: <20190218183657.16296-5-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI. (plusminus:mmx_3): Check TARGET_MMX_WITH_SSE. (sat_plusminus:mmx_3): Likewise. (3): New. (*mmx_3): Add SSE emulation. (*mmx_3): Likewise. --- gcc/config/i386/mmx.md | 59 +++++++++++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 21 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 0aa793395fb..587e31b299e 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -45,7 +45,7 @@ ;; 8 byte integral modes handled by MMX (and by extension, SSE) (define_mode_iterator MMXMODEI [V8QI V4HI V2SI]) -(define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI V1DI]) +(define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI (V1DI "TARGET_SSE2")]) ;; All 8-byte vector modes handled by MMX (define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF]) @@ -663,39 +663,56 @@ (define_expand "mmx_3" [(set (match_operand:MMXMODEI8 0 "register_operand") (plusminus:MMXMODEI8 - (match_operand:MMXMODEI8 1 "nonimmediate_operand") - (match_operand:MMXMODEI8 2 "nonimmediate_operand")))] - "TARGET_MMX || (TARGET_SSE2 && mode == V1DImode)" + (match_operand:MMXMODEI8 1 "register_mmxmem_operand") + (match_operand:MMXMODEI8 2 "register_mmxmem_operand")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "ix86_fixup_binary_operands_no_copy (, mode, operands);") + +(define_expand "3" + [(set (match_operand:MMXMODEI 0 "register_operand") + (plusminus:MMXMODEI + (match_operand:MMXMODEI 1 "register_operand") + (match_operand:MMXMODEI 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (, mode, operands);") (define_insn "*mmx_3" - [(set (match_operand:MMXMODEI8 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI8 0 "register_operand" "=y,x,Yv") (plusminus:MMXMODEI8 - (match_operand:MMXMODEI8 1 "nonimmediate_operand" "0") - (match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))] - "(TARGET_MMX || (TARGET_SSE2 && mode == V1DImode)) + (match_operand:MMXMODEI8 1 "register_mmxmem_operand" "0,0,Yv") + (match_operand:MMXMODEI8 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && ix86_binary_operator_ok (, mode, operands)" - "p\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + "@ + p\t{%2, %0|%0, %2} + p\t{%2, %0|%0, %2} + vp\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sseadd,sseadd") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_3" [(set (match_operand:MMXMODE12 0 "register_operand") (sat_plusminus:MMXMODE12 - (match_operand:MMXMODE12 1 "nonimmediate_operand") - (match_operand:MMXMODE12 2 "nonimmediate_operand")))] - "TARGET_MMX" + (match_operand:MMXMODE12 1 "register_mmxmem_operand") + (match_operand:MMXMODE12 2 "register_mmxmem_operand")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (, mode, operands);") (define_insn "*mmx_3" - [(set (match_operand:MMXMODE12 0 "register_operand" "=y") + [(set (match_operand:MMXMODE12 0 "register_operand" "=y,x,Yv") (sat_plusminus:MMXMODE12 - (match_operand:MMXMODE12 1 "nonimmediate_operand" "0") - (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX && ix86_binary_operator_ok (, mode, operands)" - "p\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + (match_operand:MMXMODE12 1 "register_mmxmem_operand" "0,0,Yv") + (match_operand:MMXMODE12 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (, mode, operands)" + "@ + p\t{%2, %0|%0, %2} + p\t{%2, %0|%0, %2} + vp\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sseadd,sseadd") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_mulv4hi3" [(set (match_operand:V4HI 0 "register_operand") From patchwork Mon Feb 18 18:36:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044244 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496535-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="IBQW40LA"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="RqfLVtPv"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CMm0ww8z9rxp for ; Tue, 19 Feb 2019 05:39:47 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=j9D FwR9+90Y/mGaNtuBsWUNch1c7rmsJPheHjkhrU3Cmo9ZInB0SEV86hoC6rxzEAt+ OhfqS5MEA22GkF+imjBr9L0T+lPskqMPN1XeEWRwKlWyiky9iw5aPc/oN/j1e9z3 H3gPij6fclAEUjeFvsNBfhp1wjFBKFzmWtSUNRQI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=Q8apP3lox 4oe++xmWxDpkmvXWfo=; b=IBQW40LAD4vzousfkIB0yC+pwd1sehEpodRiryE7W 4cQGhNqW+vQw8EVTdlPgrPd7JWg1hWDIi133zwlFCiVN08YVacuM6e6wDFvjnllU 9DdWUAnJXSn1PlmDW2uQ+OGTQ9krhkzO0IA6FdLqYcl+nnYxPWNbXWlLAu8bYUDo ow= Received: (qmail 61685 invoked by alias); 18 Feb 2019 18:37:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 60288 invoked by uid 89); 18 Feb 2019 18:37:12 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-pl1-f180.google.com Received: from mail-pl1-f180.google.com (HELO mail-pl1-f180.google.com) (209.85.214.180) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:11 +0000 Received: by mail-pl1-f180.google.com with SMTP id q3so1766915pll.4 for ; Mon, 18 Feb 2019 10:37:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G5TmSSCJu/V+GYFlC6ny9B3YOspbIjkhU8pyefZRCoI=; b=RqfLVtPveTDofc5gdnZmsH8+zsgBu5P2ifOwEY10hiStJwCitWC7a+meO3+PqJQi+K m5NuMo8ONve4MGdE+EzZKrL/0XDF+aC639ffENdh6jHOWLaYq6c6Ps5XtyW1AEAI+uzl Jtfcq5QlfrgWH2DC8M/fOJeoRrGBFD6ZJXwonN1wfo4BNIHIsUuaCtyYO8BhHz/x6Qk/ 5gPo/0x7U7b6qmG1+F3uBTjTJXxrR789ZuVQloCGmkfqwfjglFHNBqj8aRbcFTMpFa2A o/aTQjK8dHtavgQjz00fl0IbeaHzRWdGWj0rf6LxdSiBg7QmJA5gtfhNZ9Gj5zf5a63a dpZw== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id w10sm15220809pgr.42.2019.02.18.10.37.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:02 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 9C9FEC032E; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 05/41] i386: Emulate MMX mulv4hi3 with SSE Date: Mon, 18 Feb 2019 10:36:21 -0800 Message-Id: <20190218183657.16296-6-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. (mulv4hi3): New. (*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 587e31b299e..fd0189eae60 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -716,19 +716,31 @@ (define_expand "mmx_mulv4hi3" [(set (match_operand:V4HI 0 "register_operand") - (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand") - (match_operand:V4HI 2 "nonimmediate_operand")))] - "TARGET_MMX" + (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand") + (match_operand:V4HI 2 "register_mmxmem_operand")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") + +(define_expand "mulv4hi3" + [(set (match_operand:V4HI 0 "register_operand") + (mult:V4HI (match_operand:V4HI 1 "register_operand") + (match_operand:V4HI 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") (define_insn "*mmx_mulv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") - (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0") - (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" - "pmullw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxmul") - (set_attr "mode" "DI")]) + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") + (mult:V4HI (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (MULT, V4HImode, operands)" + "@ + pmullw\t{%2, %0|%0, %2} + pmullw\t{%2, %0|%0, %2} + vpmullw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxmul,ssemul,ssemul") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_smulv4hi3_highpart" [(set (match_operand:V4HI 0 "register_operand") From patchwork Mon Feb 18 18:36:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044237 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496528-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="n2tJE82M"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Ejup/IND"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CL55sHHz9rxp for ; Tue, 19 Feb 2019 05:38:21 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=QeZ PfkduxJ5qkONPpyn7M7+E9JPgpBdTW5p9WQUTJlYciCfwmVFni81J7ezp10ELnmU haRuaY2xjjYZjK8Hr7yIvaiqV0r3h9WlvLEoQKBRQ3IPdVVgJMiHBo1P+DuKtyJE cE370YNMrvGpVjEeiH2103YxySRN3F34DZUQu4qY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=vPgpXJYwG l5mcALx7hUBPbhLqPY=; b=n2tJE82MCs+jzsPC4DJM1a28+Q0SKIcPRVswmHNrk o7RMch1TmsO5pc/4xinTmIGthLj4rooKub7Iccs+eOGjzEcqVYQ22jiWM+rJxSBM paWuVdgWedUrMJtDB6aG7UuEXl2lwH+htjUDvrlHKyDoU4ZWxj+803bMnjWBtpoK 0E= Received: (qmail 59287 invoked by alias); 18 Feb 2019 18:37:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59100 invoked by uid 89); 18 Feb 2019 18:37:07 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=sk:smulv4h, HContent-Transfer-Encoding:8bit X-HELO: mail-pf1-f179.google.com Received: from mail-pf1-f179.google.com (HELO mail-pf1-f179.google.com) (209.85.210.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:05 +0000 Received: by mail-pf1-f179.google.com with SMTP id c123so9006788pfb.0 for ; Mon, 18 Feb 2019 10:37:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HUC1DAL0wjaOYvsaWtZOtV9E1cSPpcVYcnoThiVL3sg=; b=Ejup/INDFpvGuZVbUstcogymlywf4DuWh1c0512rDJI87rr2zcgMUOfYaNIDxPciVZ jBQWgSkJTwHqJEVatc+5oTCthwand7983j0N6eJSp/yr6lpO8AQYYYtWOFAdQ5DmH0GJ +YuwNYmC75Os1EizD8RsUaGfc66AOozldAUY4OwxYqGzKt3z7peeyQLBEzvwtu/mWHlK p/+BA8Eq8upW1fR8BPDtAbVk2d5Qs6EYesUzF5VG7pQ1vMz4oQ9wjQLPGTeMZtyrYZqK 78ZQIN8pug3ydAiDqj5gv0poiNYBLAVBVOvf5PbAfX4N9HLeOIIR988DDIOkpVpN2i/7 iZgQ== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id s1sm10272808pgv.30.2019.02.18.10.37.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:02 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id A897FC0330; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 06/41] i386: Emulate MMX smulv4hi3_highpart with SSE Date: Mon, 18 Feb 2019 10:36:22 -0800 Message-Id: <20190218183657.16296-7-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. (*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index fd0189eae60..01c80602b5b 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -748,27 +748,32 @@ (lshiftrt:V4SI (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand")) + (match_operand:V4HI 1 "register_mmxmem_operand")) (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand"))) + (match_operand:V4HI 2 "register_mmxmem_operand"))) (const_int 16))))] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") (define_insn "*mmx_smulv4hi3_highpart" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (truncate:V4HI (lshiftrt:V4SI (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "%0")) + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv")) (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv"))) (const_int 16))))] - "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" - "pmulhw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxmul") - (set_attr "mode" "DI")]) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (MULT, V4HImode, operands)" + "@ + pmulhw\t{%2, %0|%0, %2} + pmulhw\t{%2, %0|%0, %2} + vpmulhw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxmul,ssemul,ssemul") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_umulv4hi3_highpart" [(set (match_operand:V4HI 0 "register_operand") From patchwork Mon Feb 18 18:36:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044238 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496529-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="IXaBHVLm"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="C2MyprbZ"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CLL3BLWz9rxp for ; Tue, 19 Feb 2019 05:38:34 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=I3r uIfIpE+8oOCz619FXzG3H6XJTnKrzVsfmEuBzYkXEqjTk/F2OSStY98CXhCoN+RB 4U7xg4MVTX+8psdD86CmSUBaGYhhhweFldkwKutgzucIJ7cA+10H4lO+h0HLUN4y rBA3QkgsOuYIsDI9gfyQqXLR6WjtmkUK4uAgtbz0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=PdFkGHlwy CCi5xER5f3zJnM7HCg=; b=IXaBHVLmMqMqo0ugN/9kgk+s/NZ9/+9blevcrD9fj jnb9JYffvouynEQHyv1TBdf7GcYbv+aFd8hmjv9wVqIfqY1W9qL2gA5zxfEhJ1ZW yqLviO3yiY5LjyjIPp8nM6mzLG76pwTTr1O6W2oK/j9g89bHdKMM/qBbSeAwtPnF t8= Received: (qmail 59461 invoked by alias); 18 Feb 2019 18:37:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59312 invoked by uid 89); 18 Feb 2019 18:37:08 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Received:2bc4, HX-Received:sk:r187mr2, HContent-Transfer-Encoding:8bit X-HELO: mail-pg1-f180.google.com Received: from mail-pg1-f180.google.com (HELO mail-pg1-f180.google.com) (209.85.215.180) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:06 +0000 Received: by mail-pg1-f180.google.com with SMTP id r11so8870448pgp.6 for ; Mon, 18 Feb 2019 10:37:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2FCxKsr5icQMCDBSS4gOreRSfGWcLRuvNjOL03nbiFc=; b=C2MyprbZSmZEXCE+e+tTMcav9MMACH8nw8XZ/ZivqojfNF9KGQ/3OsxP8hdaRTebDV FCJF/DAF3Q5ZeWGw7/9ShqtX1kBj3Ugj7B3sZdbI4oDKeKLreUpzE8YHgMe3Fn10miyC f2OgJF2mCvigSNoMo5Qj9Rbu/qv1Z3VKVXMnBGIfeRQQDbvgIYPBoBHvnpC8Lh1IWyVd LUFlc//1SY9i+6P0sa9kDCfyR56xblS5wUAvlOblcMtgdROtwDO5+CUgL5GPx/qpQYjg bjszHVJ0q6lQtw0VvtfyQ/dApRHxQZ4JElfm6cVEbKJq8q1UCG6ypUEmDMA6c1mfCgdQ ZJXQ== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id u87sm34583479pfi.2.2019.02.18.10.37.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:02 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id B51CDC033A; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 07/41] i386: Emulate MMX mmx_pmaddwd with SSE Date: Mon, 18 Feb 2019 10:36:23 -0800 Message-Id: <20190218183657.16296-8-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX pmaddwd with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. (*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 01c80602b5b..fe746a487d1 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -810,11 +810,11 @@ (mult:V2SI (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 1 "nonimmediate_operand") + (match_operand:V4HI 1 "register_mmxmem_operand") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 2 "nonimmediate_operand") + (match_operand:V4HI 2 "register_mmxmem_operand") (parallel [(const_int 0) (const_int 2)])))) (mult:V2SI (sign_extend:V2SI @@ -823,20 +823,20 @@ (sign_extend:V2SI (vec_select:V2HI (match_dup 2) (parallel [(const_int 1) (const_int 3)]))))))] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") (define_insn "*mmx_pmaddwd" - [(set (match_operand:V2SI 0 "register_operand" "=y") + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv") (plus:V2SI (mult:V2SI (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 1 "nonimmediate_operand" "%0") + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 2 "nonimmediate_operand" "ym") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv") (parallel [(const_int 0) (const_int 2)])))) (mult:V2SI (sign_extend:V2SI @@ -845,10 +845,15 @@ (sign_extend:V2SI (vec_select:V2HI (match_dup 2) (parallel [(const_int 1) (const_int 3)]))))))] - "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" - "pmaddwd\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxmul") - (set_attr "mode" "DI")]) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (MULT, V4HImode, operands)" + "@ + pmaddwd\t{%2, %0|%0, %2} + pmaddwd\t{%2, %0|%0, %2} + vpmaddwd\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxmul,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_pmulhrwv4hi3" [(set (match_operand:V4HI 0 "register_operand") From patchwork Mon Feb 18 18:36:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044239 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496530-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="cIaCFdoa"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZMORq/tk"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CLZ2Zgfz9s9G for ; Tue, 19 Feb 2019 05:38:46 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=EHM zb1UtemJP4vRfsc6CsxxvlDvIQ80wbvuDx+OJMWuazWXlFXBTCu+OEy0R7th3tG4 U0GVtIH5x/XanPnQrN6mRZwGB/VS9vy3o6z92GuwWTsrPFZj+PnT2oOnx5jriDg0 pMLD0PLTaENkt2GPXx0rpuO3nUQomHNlRVlSsSN4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=857m0hszb JPDmQ2pKXvdjp055M4=; b=cIaCFdoaxCAhxAnZSYJyp/Vw8B8wNP0zpXHuao2x2 qwEL99JGdPRHAoXMQmD7X7pdem0W+fW9L9ybw6roQobsUqI0Y4ZjeKmflK5h+HT+ UZA5WLdsNbokg5V18iG3e+xA5gxUAV7yffRgxy6LFkvq6nOrBTO4JP8am+Jbiglf cM= Received: (qmail 59592 invoked by alias); 18 Feb 2019 18:37:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59424 invoked by uid 89); 18 Feb 2019 18:37:08 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=ashr, shift_insn, HX-Gm-Message-State:AHQUAua, psra X-HELO: mail-pl1-f182.google.com Received: from mail-pl1-f182.google.com (HELO mail-pl1-f182.google.com) (209.85.214.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:07 +0000 Received: by mail-pl1-f182.google.com with SMTP id e5so9142332plb.5 for ; Mon, 18 Feb 2019 10:37:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZoaSPc5G13Q+0GAqsfe/Btzr+OSVfX8jerx1+qfAnqU=; b=ZMORq/tkJTe8kr1HkI2ki0D5mVippDVHu3zd6ImTC1eBsMBXWLyHAiJXTdMfrJjZST CXdbFuUcFahrpyeJNRWX5jBXcQBfz+c5g2XeYy9mlUmhIKA/W8/QSGeih7i6u25oiOdf O14VmknzUJJcvAvILJjfwH0gRU00Bqn+Orqv0xxVKBm4++mTZWH6rws0PPDbZxiAIOwR NX+GqYHW4VXCidwZAh31Wu4uBHfun/8ug8S7SkwnLgBVp9uK+kOuYXKUf1UXDDX2WzLd O257vGap2KRpPNFAVxIuD1y5SqYaGIbXKnBzmn2sZXTaty+35BYw1LicFseyTgMmH/w4 8lwA== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id 67sm50206186pfl.175.2019.02.18.10.37.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:02 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id C1EE5C033B; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 08/41] i386: Emulate MMX ashr3/3 with SSE Date: Mon, 18 Feb 2019 10:36:24 -0800 Message-Id: <20190218183657.16296-9-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX ashr3/3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_ashr3): Also allow TARGET_MMX_WITH_SSE. Add SSE emulation. (mmx_3): Likewise. (ashr3): New. (3): Likewise. --- gcc/config/i386/mmx.md | 50 ++++++++++++++++++++++++++++++------------ 1 file changed, 36 insertions(+), 14 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index fe746a487d1..6af05a1881e 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -959,32 +959,54 @@ (set_attr "mode" "DI")]) (define_insn "mmx_ashr3" - [(set (match_operand:MMXMODE24 0 "register_operand" "=y") + [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,Yv") (ashiftrt:MMXMODE24 - (match_operand:MMXMODE24 1 "register_operand" "0") - (match_operand:DI 2 "nonmemory_operand" "yN")))] - "TARGET_MMX" - "psra\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxshft") + (match_operand:MMXMODE24 1 "register_operand" "0,0,Yv") + (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + psra\t{%2, %0|%0, %2} + psra\t{%2, %0|%0, %2} + vpsra\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxshft,sseishft,sseishft") (set (attr "length_immediate") (if_then_else (match_operand 2 "const_int_operand") (const_string "1") (const_string "0"))) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) + +(define_expand "ashr3" + [(set (match_operand:MMXMODE24 0 "register_operand") + (ashiftrt:MMXMODE24 + (match_operand:MMXMODE24 1 "register_operand") + (match_operand:DI 2 "nonmemory_operand")))] + "TARGET_MMX_WITH_SSE") (define_insn "mmx_3" - [(set (match_operand:MMXMODE248 0 "register_operand" "=y") + [(set (match_operand:MMXMODE248 0 "register_operand" "=y,x,Yv") (any_lshift:MMXMODE248 - (match_operand:MMXMODE248 1 "register_operand" "0") - (match_operand:DI 2 "nonmemory_operand" "yN")))] - "TARGET_MMX" - "p\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxshft") + (match_operand:MMXMODE248 1 "register_operand" "0,0,Yv") + (match_operand:DI 2 "nonmemory_operand" "yN,xN,YvN")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + p\t{%2, %0|%0, %2} + p\t{%2, %0|%0, %2} + vp\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxshft,sseishft,sseishft") (set (attr "length_immediate") (if_then_else (match_operand 2 "const_int_operand") (const_string "1") (const_string "0"))) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) + +(define_expand "3" + [(set (match_operand:MMXMODE248 0 "register_operand") + (any_lshift:MMXMODE248 + (match_operand:MMXMODE248 1 "register_operand") + (match_operand:DI 2 "nonmemory_operand")))] + "TARGET_MMX_WITH_SSE") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; From patchwork Mon Feb 18 18:36:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044241 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496532-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="kQcICxJ8"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="m9FXEgEg"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CM327mWz9rxp for ; Tue, 19 Feb 2019 05:39:11 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=XfX y12qxajDIzVmKMhPxURmadqN+wy++4lY1v0TNh9J4GykA4SvrIChBl0WM+HvOjV9 CZy3HSpRexXKl5VNqE5WgmzRJnr8dg0QavEs3FkDwHwLv5ln76oV/RKTd1AtdaLo AoXk+/Yb9Rvu/UxFl971Pxya8avEXdkQV3WU1ZJM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=cC+4zGlOm bKgjg9FQCrXeORalG0=; b=kQcICxJ860uKWPbpKvV6lzV32g1talQh7ZjrjLN9H 9l+MuOhc60wBVRyEMEGPntMpFIF7Ce0Cs8QywRa4iGK/W4G4aMyoVEgK0cmlr/xr wXRxETNdEE6LL37GzgC6KhcT0nHCY3vXiAb8VfYfBcgzCMtm9avGNwGQYwbYuDid +M= Received: (qmail 59773 invoked by alias); 18 Feb 2019 18:37:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59611 invoked by uid 89); 18 Feb 2019 18:37:09 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-pg1-f175.google.com Received: from mail-pg1-f175.google.com (HELO mail-pg1-f175.google.com) (209.85.215.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:07 +0000 Received: by mail-pg1-f175.google.com with SMTP id h11so6520504pgl.0 for ; Mon, 18 Feb 2019 10:37:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KMoZ340GLHRcNnvjIVTzZDKLw8RUekEc6Jh+HbXxB9o=; b=m9FXEgEg13uqTfgUHf8/HZ8VZK0+B7g1FmB8p2HO8yfcV6b0/NtiSBkAxgtwt/VC+V nxeNw7KhMQTpYfuePo4zaVO+B3n5wFYwZKatwvOtNh+3WE5pz68k+a0Na8qFKJebx5nw FzFxBKTpxNfKHBXhvt4YWv6bdmePcAZu2DIEST2c8CeembqmrWHgLR455CIhdZal1nEE Cuxg7Bk2Vf6S3Jl78+V+u6EitRS8VALiMA2suk9u8MLlBZ6ogjevjUxYnNFX4eGTNnL3 mbIsMQzXZh/b3mhpAyXPazPmGTkcF6imT50WlNChytjvXFDw/u+zk/R67qranG8g0fda Iqug== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id 23sm8920042pft.187.2019.02.18.10.37.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:02 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id CE622C033C; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 09/41] i386: Emulate MMX 3 with SSE Date: Mon, 18 Feb 2019 10:36:25 -0800 Message-Id: <20190218183657.16296-10-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX 3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (any_logic:mmx_3): Also allow TARGET_MMX_WITH_SSE. (any_logic:3): New. (any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 6af05a1881e..33f6c2aa774 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1061,20 +1061,33 @@ (define_expand "mmx_3" [(set (match_operand:MMXMODEI 0 "register_operand") (any_logic:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand") - (match_operand:MMXMODEI 2 "nonimmediate_operand")))] - "TARGET_MMX" + (match_operand:MMXMODEI 1 "register_mmxmem_operand") + (match_operand:MMXMODEI 2 "register_mmxmem_operand")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "ix86_fixup_binary_operands_no_copy (, mode, operands);") + +(define_expand "3" + [(set (match_operand:MMXMODEI 0 "register_operand") + (any_logic:MMXMODEI + (match_operand:MMXMODEI 1 "register_operand") + (match_operand:MMXMODEI 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (, mode, operands);") (define_insn "*mmx_3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") (any_logic:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX && ix86_binary_operator_ok (, mode, operands)" - "p\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,Yv") + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (, mode, operands)" + "@ + p\t{%2, %0|%0, %2} + p\t{%2, %0|%0, %2} + vp\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; From patchwork Mon Feb 18 18:36:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044245 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496536-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="CZ1refEM"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="T6JBdXGk"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CMz677Xz9s9G for ; Tue, 19 Feb 2019 05:39:59 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=VCQ HBAARbpVBzIbAGP+dZkPgN35UVGNae1pxZpFmw2BAwxxw5RirO8LFxQuP/hUmWe0 5V3M9fl4jD8dSYlK6gdWJO5ydw6l5ik53+3rMWbfszzLz2KAMuY7vePTpFzLwihh fJfuyWdo4hwuFJIOsPXwcc9FOEl3ShDwwoWOm0bk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=n3UXf+k3y Z+gAFZGewzsqvVePWM=; b=CZ1refEMozOl618UjhEjDv1fAbyxW4B+zHI8b6SNh HXcLo4QLe6JQNsrmr03ojEFzWOWzXleUyNf3T9QsEe62I1twohYWp8KTAtz1VAhx TMj1YLkG0BpBfpEZXQz0DhA8h0kUckP6CMUxgKTcmtv+t+TCPSb9XJWDw2tdITfJ Tw= Received: (qmail 61824 invoked by alias); 18 Feb 2019 18:37:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 60443 invoked by uid 89); 18 Feb 2019 18:37:13 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-pl1-f182.google.com Received: from mail-pl1-f182.google.com (HELO mail-pl1-f182.google.com) (209.85.214.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:12 +0000 Received: by mail-pl1-f182.google.com with SMTP id q3so1766976pll.4 for ; Mon, 18 Feb 2019 10:37:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tTDOSUG/4UdJwfF872B6k+ioJaGc/TP9/5ZquyXZn44=; b=T6JBdXGkAJrS7KrMRD8Wc7iWExSmuYaNTtHxQqb0wWX2pIoPmDTpT41CK6Qd2V+4Ni 413cHom7tuzf+UvPxMLoXB2jkvAWF84JaXA0VuITy225OCcIsC2igT06oQ5NPm2cdce6 G+r3fk09U+4mIB7emMcsi2eek7DvDWbxJogHR/nAnjvrPbCD5bP6NHAoTRUTMS5BpKMO mtPB80gxE7pLzEBkqb+vO3C+TGFZun5DutaYcmzEJ4JYeSPTMzFthrdapvAFnrvy7W3C NH/FuAgJ1UAZCbjUh2GKJ9dmvlUR6Ic+csDUAq5aEtUit3nzbxuvqC4PXLthSpKuWnLk MYug== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id 14sm20377027pgq.22.2019.02.18.10.37.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:02 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id DA9EBC0344; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 10/41] i386: Emulate MMX mmx_andnot3 with SSE Date: Mon, 18 Feb 2019 10:36:26 -0800 Message-Id: <20190218183657.16296-11-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_andnot3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 33f6c2aa774..b3df46dd563 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1049,14 +1049,18 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_insn "mmx_andnot3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") (and:MMXMODEI - (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0")) - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX" - "pandn\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0,0,Yv")) + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + pandn\t{%2, %0|%0, %2} + pandn\t{%2, %0|%0, %2} + vpandn\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_3" [(set (match_operand:MMXMODEI 0 "register_operand") From patchwork Mon Feb 18 18:36:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044242 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496533-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="RsZL/bMZ"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="H8dnQnaM"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CMH5b5Zz9sCh for ; Tue, 19 Feb 2019 05:39:23 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=DL5 iprv238mBDvccYCd8BIw9P2P9xdqVkc72HNhNHs7z4cs+mXuewQbrEBle5ZBYs0j P68JIgedf6OJe8HIuyV43BwJyiQ8WgWg4SBwN5Adhyb7msqtqg0k3DhDu3evFYJl xuvJ4LLYT+LvARdYQsK5v772CbRgiiqNftR+W418= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=S/RjcT8d9 8cKCpCFbuHJFvJve4g=; b=RsZL/bMZKVqepP993YLtuHsDzL0aQe00MXJhKH30p X9ralCOBzHqcbqQ5ys5zmkaTJnd0x/XLHLbCjjAW8ayaIOnYq2JysD2Ybmc5JubB G+JKyDln0Z3ixLwfcuDxMUEp34Q7pO7s2MPGoM5LLFoY+tzIMTTvt/XPAWlJJVvE Qg= Received: (qmail 59977 invoked by alias); 18 Feb 2019 18:37:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59826 invoked by uid 89); 18 Feb 2019 18:37:10 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Received:5d5f, HContent-Transfer-Encoding:8bit X-HELO: mail-pg1-f171.google.com Received: from mail-pg1-f171.google.com (HELO mail-pg1-f171.google.com) (209.85.215.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:08 +0000 Received: by mail-pg1-f171.google.com with SMTP id y4so8868596pgc.12 for ; Mon, 18 Feb 2019 10:37:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9gAPl/ZSUAf0fRjLhVX/HkDkAvmEEQwd3Q+OBISpYLM=; b=H8dnQnaM++zyPPL5VTBwK8U1pmyH6mYVf7Ac34qzKcWbvk3sM0GxTKcHFjIX8V8n6f UMVWtGEEcnFeCVmZQMVJhpC3bHLtaJ7zIvM75Kx5TtPiKjKHDYyGQIB3oQVrzqovCFfk v/EttuoOxIzs1k66hFJgX213kpGxGCqL8aG7nX2ackyvG4hGP8HFObtLQ5F8aOvQVE75 a0JAw6EdtyvAR5Sc+Je61SfxJ0YIwc61lzYDchy8YZS0gUrGvRj9+5tJio4D9VvuC8WU Yc/PmT/o4Mn7qbuhZ+a9nJwMj+KtvooQHUlyzgHAJtcMUn1TeXlLvoX3Og2dd2SY/qfg gxIA== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id i71sm43608977pfi.170.2019.02.18.10.37.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:02 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id E6D41C034A; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 11/41] i386: Emulate MMX mmx_eq/mmx_gt3 with SSE Date: Mon, 18 Feb 2019 10:36:27 -0800 Message-Id: <20190218183657.16296-12-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_eq3): Also allow TARGET_MMX_WITH_SSE. (*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE support. (mmx_gt3): Likewise. --- gcc/config/i386/mmx.md | 43 +++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index b3df46dd563..aeebb4f5741 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1017,30 +1017,39 @@ (define_expand "mmx_eq3" [(set (match_operand:MMXMODEI 0 "register_operand") (eq:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand") - (match_operand:MMXMODEI 2 "nonimmediate_operand")))] - "TARGET_MMX" + (match_operand:MMXMODEI 1 "register_mmxmem_operand") + (match_operand:MMXMODEI 2 "register_mmxmem_operand")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (EQ, mode, operands);") (define_insn "*mmx_eq3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") (eq:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX && ix86_binary_operator_ok (EQ, mode, operands)" - "pcmpeq\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxcmp") - (set_attr "mode" "DI")]) + (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,Yv") + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (EQ, mode, operands)" + "@ + pcmpeq\t{%2, %0|%0, %2} + pcmpeq\t{%2, %0|%0, %2} + vpcmpeq\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcmp,ssecmp,ssecmp") + (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_gt3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") (gt:MMXMODEI - (match_operand:MMXMODEI 1 "register_operand" "0") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX" - "pcmpgt\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxcmp") - (set_attr "mode" "DI")]) + (match_operand:MMXMODEI 1 "register_operand" "0,0,Yv") + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + pcmpgt\t{%2, %0|%0, %2} + pcmpgt\t{%2, %0|%0, %2} + vpcmpgt\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcmp,ssecmp,ssecmp") + (set_attr "mode" "DI,TI,TI")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; From patchwork Mon Feb 18 18:36:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044243 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496534-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="PrYlYNq3"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KflJDCDj"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CMX0kLtz9s9G for ; Tue, 19 Feb 2019 05:39:35 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=Kdq ZbZacuWTEmCP/c75gyGS/0+n4IY8GkRBwGoIBe0TtzEdaTjkVX24LxsnIjKT24ZD Sq7mc1au9lwyRzF3OVm709KdYIw5hQ1VWrudhKS2rmm84ofzapOe+TNu1eDdz6bo EXxGzQ3IipzsFHDX+9aHlKMe4AfbLSH7TQO7DTVs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=AKvLxY7qz 2V6D/gxWHue6oTXQbM=; b=PrYlYNq3Hyt7eWIbcRIIjLFPTDv/2BPzdUSYwlakT Zugp7crBsKjEE4Psxn+fS+FCUvbVdHsYDjlmjrZkNOEPIMcSZlsuhQQK0IK0iWAY 6iVdwBTAdLZosUMAaAZCSaPZPxEjRECs1NFNtp+or7Hu5MWflCd0NCyE8FaQS/Mr EI= Received: (qmail 61135 invoked by alias); 18 Feb 2019 18:37:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 60201 invoked by uid 89); 18 Feb 2019 18:37:12 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pl1-f171.google.com Received: from mail-pl1-f171.google.com (HELO mail-pl1-f171.google.com) (209.85.214.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:10 +0000 Received: by mail-pl1-f171.google.com with SMTP id r14so9127777pls.12 for ; Mon, 18 Feb 2019 10:37:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3OCDzQol2MYl7eKdiaFxOV4rsjm29x5FSsXIWTkXvZ8=; b=KflJDCDj0Q0WvCLBiFhroAkxRQYDdlTGiMzHl6qjuV9Lx1dk0fDM6ZhNhlZs3zxrVE oYlH1Eh1WxcWG7yc1kqDOfdyqpOgqXSPuo0qzT3H5JUaLK7DEtp9wrut5yBV3E3YacE0 dhb+Cx+Lkid0oifUla0MSi5oMDPZ5veCTQQqYW9wJbQibbbQ76Al8yupF+t0UvWDB1zm TZr+hEEyIAdIJHvodOquPT4C8Ok5ExHgdMv4hM9w5s1sLZiPfouznxRTlV8sL9hE20IN NvyN2IP/052wB+Y9p0lPC1SUnNPvfojUfBodzAVWI2Z/k8J3nynMgzI1yTZMUV1094wE xbnQ== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id d13sm23222255pfd.58.2019.02.18.10.37.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:02 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id F30D6C034B; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 12/41] i386: Emulate MMX vec_dupv2si with SSE Date: Mon, 18 Feb 2019 10:36:28 -0800 Message-Id: <20190218183657.16296-13-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX vec_dupv2si with SSE. Add the "Yw" constraint to allow broadcast from integer register for AVX512BW with TARGET_AVX512VL. Only SSE register source operand is allowed. PR target/89021 * config/i386/constraints.md (Yw): New constraint. * config/i386/mmx.md (*vec_dupv2si): Changed to define_insn_and_split and also allow TARGET_MMX_WITH_SSE to support SSE emulation. --- gcc/config/i386/constraints.md | 6 ++++++ gcc/config/i386/mmx.md | 24 +++++++++++++++++------- 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 16075b4acf3..c546b20d9dc 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -110,6 +110,8 @@ ;; v any EVEX encodable SSE register for AVX512VL target, ;; otherwise any SSE register ;; h EVEX encodable SSE register with number factor of four +;; w any EVEX encodable SSE register for AVX512BW with TARGET_AVX512VL +;; target. (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" "First SSE register (@code{%xmm0}).") @@ -146,6 +148,10 @@ "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS" "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.") +(define_register_constraint "Yw" + "TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : NO_REGS" + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target.") + ;; We use the B prefix to denote any number of internal operands: ;; f FLAGS_REG ;; g GOT memory operand. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index aeebb4f5741..b441f36dfc6 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1381,14 +1381,24 @@ (set_attr "length_immediate" "1") (set_attr "mode" "DI")]) -(define_insn "*vec_dupv2si" - [(set (match_operand:V2SI 0 "register_operand" "=y") +(define_insn_and_split "*vec_dupv2si" + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv,Yw") (vec_duplicate:V2SI - (match_operand:SI 1 "register_operand" "0")))] - "TARGET_MMX" - "punpckldq\t%0, %0" - [(set_attr "type" "mmxcvt") - (set_attr "mode" "DI")]) + (match_operand:SI 1 "register_operand" "0,0,Yv,r")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + punpckldq\t%0, %0 + # + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(set (match_dup 0) + (vec_duplicate:V4SI (match_dup 1)))] + "operands[0] = lowpart_subreg (V4SImode, operands[0], + GET_MODE (operands[0]));" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx,x64_avx") + (set_attr "type" "mmxcvt,ssemov,ssemov,ssemov") + (set_attr "mode" "DI,TI,TI,TI")]) (define_insn "*mmx_concatv2si" [(set (match_operand:V2SI 0 "register_operand" "=y,y") From patchwork Mon Feb 18 18:36:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044249 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496540-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="JoQz+bZY"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fiNHvWWY"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CNy3Pgsz9rxp for ; Tue, 19 Feb 2019 05:40:50 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=RUB NFKQlmPbYwOgyjsctUuSIioaX33iKT+voCiQmd3ZFDk8R0j/XA+EkCgNff+K8iGh cPze8sRKeDtedfPOI85YTHxEKIfdHrUXWVl7YPXXozPxeIkhqv38T5BqWimluTp8 fnRAukaUsG1zNfaFeNUzj2wfFWBgyk4wKKrj9WJk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=n9jOrLWRW V0VQ1nm3NxIacbcMYo=; b=JoQz+bZYqDHtoTPO+jiL2oG+FHAzhTFluG6TWVN5s c6qRi7siZ811foZtwYSJXr8KvwxcTUMyoNULypgWtiVdocWifFJVyJPmxjVWKEMC vazTmc9UkukhwDwRZUNvEc8t4Scca1M1qWvc4izq0PbL23XxRJ+qVHz3r1kPzJH2 lE= Received: (qmail 62944 invoked by alias); 18 Feb 2019 18:37:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 61178 invoked by uid 89); 18 Feb 2019 18:37:18 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pl1-f172.google.com Received: from mail-pl1-f172.google.com (HELO mail-pl1-f172.google.com) (209.85.214.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:16 +0000 Received: by mail-pl1-f172.google.com with SMTP id g9so9152541plo.3 for ; Mon, 18 Feb 2019 10:37:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1/y09jqmxUImLAA1O9YElOfjwNz1OzsQuuzbaGYGPPE=; b=fiNHvWWYf0HuJZqQRGfhcXz6z3fuLlpJ1ElJ1EPA3UcNcqef1uqJCZYhANp8/mgLKn IEJt50OV5tFqqWc7Jz4vLnZiWkklD15/XhHcm3TTwIybTkMj8ExPtFoJl7uDU+oMgk3a 4vci9Ve0fYgzMKrOU9eEYEMBZ5zYAspCfic8rP+t7xXxKRdk3P9SyB/qMIsnAt0HEhha uma7JTsdwOWLUGfrRQQE+yPqm72srPti8xFYKU3QObv3dgmfcXszO5EgB7VoiYdF1kwP tjfuYeJLBjctXQa/oFoe+f9e258WXVCA+qqG0oQQTLyFT7KUs6CdVp11gXP3ajNmC8sd 288w== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id 86sm29503284pfk.157.2019.02.18.10.37.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:10 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 0B801C034C; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 13/41] i386: Emulate MMX pshufw with SSE Date: Mon, 18 Feb 2019 10:36:29 -0800 Message-Id: <20190218183657.16296-14-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX pshufw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_pshufw_1): Add SSE emulation. (*vec_dupv4hi): Changed to define_insn_and_split and also allow TARGET_MMX_WITH_SSE to support SSE emulation. --- gcc/config/i386/mmx.md | 81 +++++++++++++++++++++++++++++++++--------- 1 file changed, 65 insertions(+), 16 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index b441f36dfc6..09e78ac5f74 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1323,9 +1323,10 @@ (define_expand "mmx_pshufw" [(match_operand:V4HI 0 "register_operand") - (match_operand:V4HI 1 "nonimmediate_operand") + (match_operand:V4HI 1 "register_mmxmem_operand") (match_operand:SI 2 "const_int_operand")] - "TARGET_SSE || TARGET_3DNOW_A" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" { int mask = INTVAL (operands[2]); emit_insn (gen_mmx_pshufw_1 (operands[0], operands[1], @@ -1337,14 +1338,15 @@ }) (define_insn "mmx_pshufw_1" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,Yv") (vec_select:V4HI - (match_operand:V4HI 1 "nonimmediate_operand" "ym") + (match_operand:V4HI 1 "register_mmxmem_operand" "ym,Yv") (parallel [(match_operand 2 "const_0_to_3_operand") (match_operand 3 "const_0_to_3_operand") (match_operand 4 "const_0_to_3_operand") (match_operand 5 "const_0_to_3_operand")])))] - "TARGET_SSE || TARGET_3DNOW_A" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" { int mask = 0; mask |= INTVAL (operands[2]) << 0; @@ -1353,11 +1355,20 @@ mask |= INTVAL (operands[5]) << 6; operands[2] = GEN_INT (mask); - return "pshufw\t{%2, %1, %0|%0, %1, %2}"; + switch (which_alternative) + { + case 0: + return "pshufw\t{%2, %1, %0|%0, %1, %2}"; + case 1: + return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}"; + default: + gcc_unreachable (); + } } - [(set_attr "type" "mmxcvt") + [(set_attr "mmx_isa" "native,x64") + (set_attr "type" "mmxcvt,sselog") (set_attr "length_immediate" "1") - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI")]) (define_insn "mmx_pswapdv2si2" [(set (match_operand:V2SI 0 "register_operand" "=y") @@ -1370,16 +1381,54 @@ (set_attr "prefix_extra" "1") (set_attr "mode" "DI")]) -(define_insn "*vec_dupv4hi" - [(set (match_operand:V4HI 0 "register_operand" "=y") +(define_insn_and_split "*vec_dupv4hi" + [(set (match_operand:V4HI 0 "register_operand" "=y,Yv,Yw") (vec_duplicate:V4HI (truncate:HI - (match_operand:SI 1 "register_operand" "0"))))] - "TARGET_SSE || TARGET_3DNOW_A" - "pshufw\t{$0, %0, %0|%0, %0, 0}" - [(set_attr "type" "mmxcvt") - (set_attr "length_immediate" "1") - (set_attr "mode" "DI")]) + (match_operand:SI 1 "register_operand" "0,Yv,r"))))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "@ + pshufw\t{$0, %0, %0|%0, %0, 0} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] +{ + rtx op; + operands[0] = lowpart_subreg (V8HImode, operands[0], + GET_MODE (operands[0])); + if (TARGET_AVX2) + { + operands[1] = lowpart_subreg (HImode, operands[1], + GET_MODE (operands[1])); + op = gen_rtx_VEC_DUPLICATE (V8HImode, operands[1]); + } + else + { + operands[1] = lowpart_subreg (V8HImode, operands[1], + GET_MODE (operands[1])); + rtx mask = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (8, + GEN_INT (0), + GEN_INT (0), + GEN_INT (0), + GEN_INT (0), + GEN_INT (4), + GEN_INT (5), + GEN_INT (6), + GEN_INT (7))); + + op = gen_rtx_VEC_SELECT (V8HImode, operands[1], mask); + } + rtx insn = gen_rtx_SET (operands[0], op); + emit_insn (insn); + DONE; +} + [(set_attr "mmx_isa" "native,x64,x64_avx") + (set_attr "type" "mmxcvt,sselog1,ssemov") + (set_attr "length_immediate" "1,1,0") + (set_attr "mode" "DI,TI,TI")]) (define_insn_and_split "*vec_dupv2si" [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv,Yw") From patchwork Mon Feb 18 18:36:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044248 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496539-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="wjeNtAMV"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LmILgQTR"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CNk1KY0z9rxp for ; Tue, 19 Feb 2019 05:40:37 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=vHw TrLpaMEvjfZ86JtmQvQsnzZO4u9iMS2RVUfBWUr/VZyBbIXvVY+P/RsKigiOjKYk tkt00DdNSArtMyXUQuDh5hyD1e5kMXmtGhPq3wXMv9LnLyivFJw6t8Iw8L5dxhGb ZjbSxgxkPqE7X5V9uLaA6wB740nGMF46zUpGQhr0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=ea6bFLVoy ShP8fjtdQnYbVrd//U=; b=wjeNtAMVyfX3XgY4ITJItf7ECSNgRzD6otq0OKoxp eEx9DUJ79suO+KjpuXypYpPC0dLfY41YyhKIvJsa8akylcMuaIuc7QpDCRvGYJie rbCFt5DZgkI3R1WMrfr1P6MmuLAsrd49a4U1eyytsSlXYetMjCgJGtirwM/4GJns rk= Received: (qmail 62279 invoked by alias); 18 Feb 2019 18:37:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 61371 invoked by uid 89); 18 Feb 2019 18:37:19 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-pf1-f182.google.com Received: from mail-pf1-f182.google.com (HELO mail-pf1-f182.google.com) (209.85.210.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:17 +0000 Received: by mail-pf1-f182.google.com with SMTP id f132so8996652pfa.6 for ; Mon, 18 Feb 2019 10:37:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iDT7PLHBcG98KbqMSETW3Jb65T9sAMjDk21QMe3S5PY=; b=LmILgQTRyESKT6mSbgugMadvDrSy0MHvpVygzvReoQRRUcHb9SIss9TZWZDCGnJlro NwdBbQo1OLwo7jt9QogEkY5RRll1Mtniwt6EUSitrswzVM/TsjBxtgineHTypxwP0FIf zz6nWyDw0QKC7a6L+zC+b5eR0zzxNZoktkVhYmm/O71g6oQ+V57aMNK5KscRiwuYBJD0 Ha1/LJWB8JuYpiRpV13Sp9Gx0PjPNvo0q/4C1V0U9gLRN9nWuFddWEOBP1+OcLbjm8XG 57Up6lls4IVShrhpziU7H49CdbJibE+UFMmmCTiun+DEOUNlO4H++CSHvW9EoJrvPeIQ FL8g== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id w185sm23546636pfb.135.2019.02.18.10.37.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:10 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 17A86C034D; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 14/41] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE Date: Mon, 18 Feb 2019 10:36:30 -0800 Message-Id: <20190218183657.16296-15-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE. PR target/89021 * config/i386/sse.md (sse_cvtps2pi): Add SSE emulation. (sse_cvttps2pi): Likewise. --- gcc/config/i386/sse.md | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 30bf7e23122..dd3a3d9ba67 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4582,26 +4582,32 @@ (set_attr "mode" "V4SF")]) (define_insn "sse_cvtps2pi" - [(set (match_operand:V2SI 0 "register_operand" "=y") + [(set (match_operand:V2SI 0 "register_operand" "=y,Yv") (vec_select:V2SI - (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] + (unspec:V4SI [(match_operand:V4SF 1 "register_mmxmem_operand" "xm,YvBm")] UNSPEC_FIX_NOTRUNC) (parallel [(const_int 0) (const_int 1)])))] - "TARGET_SSE" - "cvtps2pi\t{%1, %0|%0, %q1}" - [(set_attr "type" "ssecvt") - (set_attr "unit" "mmx") + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE" + "@ + cvtps2pi\t{%1, %0|%0, %q1} + %vcvtps2dq\t{%1, %0|%0, %1}" + [(set_attr "mmx_isa" "native,x64") + (set_attr "type" "ssecvt") + (set_attr "unit" "mmx,*") (set_attr "mode" "DI")]) (define_insn "sse_cvttps2pi" - [(set (match_operand:V2SI 0 "register_operand" "=y") + [(set (match_operand:V2SI 0 "register_operand" "=y,Yv") (vec_select:V2SI - (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")) + (fix:V4SI (match_operand:V4SF 1 "register_mmxmem_operand" "xm,YvBm")) (parallel [(const_int 0) (const_int 1)])))] - "TARGET_SSE" - "cvttps2pi\t{%1, %0|%0, %q1}" - [(set_attr "type" "ssecvt") - (set_attr "unit" "mmx") + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE" + "@ + cvttps2pi\t{%1, %0|%0, %q1} + %vcvttps2dq\t{%1, %0|%0, %1}" + [(set_attr "mmx_isa" "native,x64") + (set_attr "type" "ssecvt") + (set_attr "unit" "mmx,*") (set_attr "prefix_rep" "0") (set_attr "mode" "SF")]) From patchwork Mon Feb 18 18:36:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044247 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496538-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="CwzNStNd"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="szGcukxH"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CNT2Rh5z9rxp for ; Tue, 19 Feb 2019 05:40:24 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=DWk vJm3bmfjlRuR5WvGrnuoamzgXgiPRC/I+1T25Wez2pVyO8D8LrTGTmeovZsnu6oz 1kdeDkuuZSdHSF4RXg/ExSL7kxOk5m1c07QNOrFdcIjPJ3ebqHScAPstClh752Uu URKDhVDQT4yAEsw+ejArXW8KP/tgMT2fYgk2Simc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=x0Luh8q9I Wf3La5yIoT9R3cZBNQ=; b=CwzNStNdqOuZQOGIXi+8Zve23t9F01Vx7u6gk2od9 MyLVxvjbv91IxXpXM1UBY7hc/8X5lOvP6Zewbf+qc0e/5tyLMJr61Apgyk6c7PKy HOPekn5pn5SsVR5glj8mmHW4B+bVLRvJcwLtTxV9rpEZdQlUkqe+BhZwN1gEnxt6 cw= Received: (qmail 62056 invoked by alias); 18 Feb 2019 18:37:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 61007 invoked by uid 89); 18 Feb 2019 18:37:17 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pf1-f178.google.com Received: from mail-pf1-f178.google.com (HELO mail-pf1-f178.google.com) (209.85.210.178) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:15 +0000 Received: by mail-pf1-f178.google.com with SMTP id n125so1717137pfn.5 for ; Mon, 18 Feb 2019 10:37:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8/z8OhxLpaOP7SO3rb4KjxVXhanmcxvRPM350shZcvk=; b=szGcukxHE5GmQ/oadzhFbBFIHEuvfKRCgXKms0STXOBKwut2ITnZEj9Rl4lQ/0seiR lPBDAqkQx8H5DG21YnmXQvam8XKXa/buManZMkW0cnxJ0XE5+5rauFh4vO0oVNKuRG6Y DgbpBmEStwYT8zhhdhPRTv04Op/iYwUodr/Y+mC0mcbsJ4Ln+Da4mvUirol9yk/EWyhs MPzzAnQ/BFlfaar20ORe7zdYkwRa3EzgvrObBK60F2kXOv1Q/qbrIbh6g4eimjiiRqV8 FNC4/vHE3QZU/wVJxyMJM3shjCjwb7r8h4AG+IKnzLVPl2sbmaycvz5x6ylXvu3B7Bt8 UthA== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id f2sm15991728pgp.32.2019.02.18.10.37.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:10 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 244BCC034E; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 15/41] i386: Emulate MMX sse_cvtpi2ps with SSE Date: Mon, 18 Feb 2019 10:36:31 -0800 Message-Id: <20190218183657.16296-16-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of destination XMM register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (sse_cvtpi2ps): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add SSE emulation. --- gcc/config/i386/sse.md | 64 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 56 insertions(+), 8 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index dd3a3d9ba67..3135ce4eace 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4569,16 +4569,64 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn "sse_cvtpi2ps" - [(set (match_operand:V4SF 0 "register_operand" "=x") +(define_insn_and_split "sse_cvtpi2ps" + [(set (match_operand:V4SF 0 "register_operand" "=x,x,Yv") (vec_merge:V4SF (vec_duplicate:V4SF - (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym"))) - (match_operand:V4SF 1 "register_operand" "0") - (const_int 3)))] - "TARGET_SSE" - "cvtpi2ps\t{%2, %0|%0, %2}" - [(set_attr "type" "ssecvt") + (float:V2SF (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv"))) + (match_operand:V4SF 1 "register_operand" "0,0,Yv") + (const_int 3))) + (clobber (match_scratch:V4SF 3 "=X,x,Yv"))] + "TARGET_SSE || TARGET_MMX_WITH_SSE" + "@ + cvtpi2ps\t{%2, %0|%0, %2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] +{ + rtx op2 = lowpart_subreg (V4SImode, operands[2], + GET_MODE (operands[2])); + /* Generate SSE2 cvtdq2ps. */ + rtx insn = gen_floatv4siv4sf2 (operands[3], op2); + emit_insn (insn); + + /* Merge operands[3] with operands[0]. */ + rtx mask, op1; + if (TARGET_AVX) + { + mask = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (4, GEN_INT (0), GEN_INT (1), + GEN_INT (6), GEN_INT (7))); + op1 = gen_rtx_VEC_CONCAT (V8SFmode, operands[3], operands[1]); + op2 = gen_rtx_VEC_SELECT (V4SFmode, op1, mask); + insn = gen_rtx_SET (operands[0], op2); + } + else + { + /* NB: SSE can only concatenate OP0 and OP3 to OP0. */ + mask = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (4, GEN_INT (2), GEN_INT (3), + GEN_INT (4), GEN_INT (5))); + op1 = gen_rtx_VEC_CONCAT (V8SFmode, operands[0], operands[3]); + op2 = gen_rtx_VEC_SELECT (V4SFmode, op1, mask); + insn = gen_rtx_SET (operands[0], op2); + emit_insn (insn); + + /* Swap bits 0:63 with bits 64:127. */ + mask = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (4, GEN_INT (2), GEN_INT (3), + GEN_INT (0), GEN_INT (1))); + rtx dest = lowpart_subreg (V4SImode, operands[0], + GET_MODE (operands[0])); + op1 = gen_rtx_VEC_SELECT (V4SImode, dest, mask); + insn = gen_rtx_SET (dest, op1); + } + emit_insn (insn); + DONE; +} + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "ssecvt") (set_attr "mode" "V4SF")]) (define_insn "sse_cvtps2pi" From patchwork Mon Feb 18 18:36:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496537-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="buF1rqoe"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Bi4aas+y"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CND72sMz9rxp for ; Tue, 19 Feb 2019 05:40:12 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=y0z bqdKh/m632xLzwS8f/jZJ6zWnc8PBpA6YjfzUqis0CfQ8+di//0E51O9ExGYzSt7 YBOuebDzK5jq41kPQGrq3cdgam+AknzWy17UqkrV4hYmIWIeNo63PC9n6MK36X39 4JPOd5pHAR0JS3y6oY3P5lM3HkabmLJSWS4yEy9Y= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=DLYvfMwlm nDZ0iBjL/aorm8NGNY=; b=buF1rqoelYM/zjdl3U9DYAaNbTmBtlBOS9HVil23d VRAdXGJ+Vr7FeBWJcDGHRg621RJjz7wbCjRSS3kTF0ZJIPPdy30SQ209m7mCjNJ1 Kp9yGWSTIbR/uXe+9MkKn04pkpXwW7kGgiXe8N651lEMRn4y01BX88ZJzZQtj4H0 Dk= Received: (qmail 61941 invoked by alias); 18 Feb 2019 18:37:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 60746 invoked by uid 89); 18 Feb 2019 18:37:15 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=nn, HContent-Transfer-Encoding:8bit X-HELO: mail-pf1-f173.google.com Received: from mail-pf1-f173.google.com (HELO mail-pf1-f173.google.com) (209.85.210.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:13 +0000 Received: by mail-pf1-f173.google.com with SMTP id f132so8996570pfa.6 for ; Mon, 18 Feb 2019 10:37:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c+vcIxokzakD4MaJnLGTX5pLSx4OmtkTlBNuO+9kr7w=; b=Bi4aas+yWy2qchh+ceJwPSeQ36JIBWRnCRhGxu5AUK1N14aZT9b4gW2LE70ne1mxsC tC/elHxu43R/WnZIe588ZTW9Y9pWiNOeEHqM9A3YALCMcJiHpYAda27/Ikl4pZIYSbkZ F4CoIp6piCzA0HtgAwWm1Uv2GFikjsXW15wBhGRPP6X8SALRzvS+FxHckLW2wPszGSjV Afb2cHFt74FE2oFgJQJai9Mz75NZa5jFBo/xgpsrHfvJKbfVEpH0rDLH/a9+EtxTJ5uR JNu0QX1vk51AK3/2+6db5c0ywJ+7g3p1kVx3S+TS6Cp6AvP92zZ09SrGHaCCUBBqiDib Jwww== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id 184sm21399697pfe.106.2019.02.18.10.37.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:10 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 308D3C034F; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 16/41] i386: Emulate MMX mmx_pextrw with SSE Date: Mon, 18 Feb 2019 10:36:32 -0800 Message-Id: <20190218183657.16296-17-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 09e78ac5f74..28725f48282 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1310,16 +1310,20 @@ (set_attr "mode" "DI")]) (define_insn "mmx_pextrw" - [(set (match_operand:SI 0 "register_operand" "=r") + [(set (match_operand:SI 0 "register_operand" "=r,r") (zero_extend:SI (vec_select:HI - (match_operand:V4HI 1 "register_operand" "y") - (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))] - "TARGET_SSE || TARGET_3DNOW_A" - "pextrw\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "mmxcvt") + (match_operand:V4HI 1 "register_operand" "y,Yv") + (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "@ + pextrw\t{%2, %1, %0|%0, %1, %2} + %vpextrw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64") + (set_attr "type" "mmxcvt,sselog1") (set_attr "length_immediate" "1") - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI")]) (define_expand "mmx_pshufw" [(match_operand:V4HI 0 "register_operand") From patchwork Mon Feb 18 18:36:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044262 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496554-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="NRlaC/mt"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OFUzETYk"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CW932Y6z9s1l for ; Tue, 19 Feb 2019 05:46:13 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=DIr AwnSKm5mpAucdc8GltzZx/4LoyI0tHr+QdfOuU3RCTNNvLIedG7nKs3o8/Wov2ak WAfvt6Csh3o9RlM6Ib/0yNxV+gVsmOtWu/CRw/QKKxa+7twdVWf5oZPf6pPF8BhX yov1LT42mW1cut8VSFEFjB9WqMMKq/yOg+O6L7Og= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=wa3v1vDKV S50ppikrAqksqw5n1k=; b=NRlaC/mt/p0qs+hDdp54bvn257H3lcb+qJB5CRU/O +oYtMEUWkomKqjum59pMojWuLFr0LkrNiDqug7GpAU/B7vJvMWW1wEK35x/vMzJX JBwqB51UZQwN8UN4dACJ1OeOBU3io3zQkTtqCnn5C42RCart4idZ9PH4+BRRDRbl i8= Received: (qmail 91344 invoked by alias); 18 Feb 2019 18:44:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91199 invoked by uid 89); 18 Feb 2019 18:44:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pg1-f177.google.com Received: from mail-pg1-f177.google.com (HELO mail-pg1-f177.google.com) (209.85.215.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:18 +0000 Received: by mail-pg1-f177.google.com with SMTP id u9so5355829pgo.7 for ; Mon, 18 Feb 2019 10:44:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jvCSJ9tUgswwad2fnfV0YdoNB/2R7Kxm20CwT9zhQf8=; b=OFUzETYk54Mkf5daBoo5hzANI4NDLZxjuACH9sHl0qtVGjAhSfdFplbxxRea+gsfWH 4u7MZwoZMF5kZXPA+ud2ggSLTNrvZzyPs0kX6zc9BXjTefIogHj93jsN3ifvryiG0OYh Eg62SBOEa/QVIA++xA6UuROUCchLhROpjdqTTicyygAr756kTEugzHs1rXfeRsJnCqGX XCHe6zgsz+ure6/sW0jRwR5iOwenyoEcIlLslmUk8ZkoFsb5KqZZQSd3YLEF/63OWu2N GGMQUHC5Ytdjckufl5ciL3CtEswNfIaIehr6Zefg1XZF3aSOlQc++Pfk+8gfoI8BDjnz S8+w== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id z15sm6178220pgc.25.2019.02.18.10.44.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:13 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 3D103C0350; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 17/41] i386: Emulate MMX mmx_pinsrw with SSE Date: Mon, 18 Feb 2019 10:36:33 -0800 Message-Id: <20190218183657.16296-18-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mmx_pinsrw with SSE. Only SSE register destination operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_pinsrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 28725f48282..dea2be1d8e2 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1282,32 +1282,45 @@ (match_operand:SI 2 "nonimmediate_operand")) (match_operand:V4HI 1 "register_operand") (match_operand:SI 3 "const_0_to_3_operand")))] - "TARGET_SSE || TARGET_3DNOW_A" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" { operands[2] = gen_lowpart (HImode, operands[2]); operands[3] = GEN_INT (1 << INTVAL (operands[3])); }) (define_insn "*mmx_pinsrw" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (vec_merge:V4HI (vec_duplicate:V4HI - (match_operand:HI 2 "nonimmediate_operand" "rm")) - (match_operand:V4HI 1 "register_operand" "0") + (match_operand:HI 2 "nonimmediate_operand" "rm,rm,rm")) + (match_operand:V4HI 1 "register_operand" "0,0,Yv") (match_operand:SI 3 "const_int_operand")))] - "(TARGET_SSE || TARGET_3DNOW_A) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A) && ((unsigned) exact_log2 (INTVAL (operands[3])) < GET_MODE_NUNITS (V4HImode))" { operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); - if (MEM_P (operands[2])) - return "pinsrw\t{%3, %2, %0|%0, %2, %3}"; + if (TARGET_MMX_WITH_SSE && TARGET_AVX) + { + if (MEM_P (operands[2])) + return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}"; + else + return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}"; + } else - return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}"; + { + if (MEM_P (operands[2])) + return "pinsrw\t{%3, %2, %0|%0, %2, %3}"; + else + return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}"; + } } - [(set_attr "type" "mmxcvt") + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcvt,sselog,sselog") (set_attr "length_immediate" "1") - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_pextrw" [(set (match_operand:SI 0 "register_operand" "=r,r") From patchwork Mon Feb 18 18:36:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044267 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496559-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="vd28zUly"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kqTINSmh"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CXM4vvSz9s1l for ; Tue, 19 Feb 2019 05:47:15 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=hf1 kZU4ln5KAdbBMR1oYb168zXEqPDVcU0XIXF6nUG25g14hqqyHIwC5rorNLP4hTx9 AKYZOqCbfMECz6z8Do+DuFeqfKg5sNK9LcC0EQZ7TM+EhVpfu/mrIVnNq+RxPVs5 AqnNXViO8Rs7beOof7fpAx/YSbkLI/0SD9RluvPE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=4WCe40LV3 mGBYteSE6Q3bZKBEug=; b=vd28zUlyKJ2eiaUGhjc+htLRpb6kjhe3k5KFxcH9r H/GCBuT3vAkbsfRoKjmLvuUVuvY/9Gqn6DNUaQ+Iqkj9QIfBSdJDjjAa+RNxAlV1 erBSjtORm8BIGss4ee5bFWuftGfgcsfGhIMPgRCI+z0f0EhrIaL6QWe5i5LSwLMS II= Received: (qmail 94114 invoked by alias); 18 Feb 2019 18:44:42 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 92319 invoked by uid 89); 18 Feb 2019 18:44:29 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-pf1-f174.google.com Received: from mail-pf1-f174.google.com (HELO mail-pf1-f174.google.com) (209.85.210.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:26 +0000 Received: by mail-pf1-f174.google.com with SMTP id s22so9011971pfh.4 for ; Mon, 18 Feb 2019 10:44:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UbFZ1l529SMMrHiPrctaSZiNZQMnJpDGEABUKIwX97w=; b=kqTINSmhkjrl7xFUcyTvlqUkkzK1/LXqMrIBP4maw7Nz3l2QernPNlc3sKC98ADcq3 DdAJTVjQ51zStw7Bu7IitU3YD28XEmkKWbKZDNWQdFme1lDCz6w1GLt9YZzig5km7cOP MLE1ph2LseZ4fW+jqlAR231nM2sNuWQurwW80Am5h/35osT2zeD1ZQ43T935Xdo8j9is TgTmRBDfNTppRZJ2omswnATYbQj4ml0bZ7rPROEtjAmMRsk1VPgyx9hZJNQQUnXAWL5f eP0QN7v4uUlyFyq5CysBqtQ2RfTA5RX1RFShLiXKrBXJhLLl+xgXolHFW8bSdQmDd9tF Qv9w== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id b68sm19885971pfc.128.2019.02.18.10.44.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:23 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 495BFC0351; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 18/41] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE Date: Mon, 18 Feb 2019 10:36:34 -0800 Message-Id: <20190218183657.16296-19-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (mmx_v8qi3): Likewise. (smaxmin:v4hi3): New. (umaxmin:v8qi3): Likewise. (smaxmin:*mmx_v4hi3): Add SSE emulation. (umaxmin:*mmx_v8qi3): Likewise. --- gcc/config/i386/mmx.md | 68 +++++++++++++++++++++++++++++------------- 1 file changed, 48 insertions(+), 20 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index dea2be1d8e2..edfb8623701 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -923,40 +923,68 @@ (define_expand "mmx_v4hi3" [(set (match_operand:V4HI 0 "register_operand") (smaxmin:V4HI - (match_operand:V4HI 1 "nonimmediate_operand") - (match_operand:V4HI 2 "nonimmediate_operand")))] - "TARGET_SSE || TARGET_3DNOW_A" + (match_operand:V4HI 1 "register_mmxmem_operand") + (match_operand:V4HI 2 "register_mmxmem_operand")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "ix86_fixup_binary_operands_no_copy (, V4HImode, operands);") + +(define_expand "v4hi3" + [(set (match_operand:V4HI 0 "register_operand") + (smaxmin:V4HI + (match_operand:V4HI 1 "register_operand") + (match_operand:V4HI 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (, V4HImode, operands);") (define_insn "*mmx_v4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (smaxmin:V4HI - (match_operand:V4HI 1 "nonimmediate_operand" "%0") - (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] - "(TARGET_SSE || TARGET_3DNOW_A) + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (, V4HImode, operands)" - "pw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + "@ + pw\t{%2, %0|%0, %2} + pw\t{%2, %0|%0, %2} + vpw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_v8qi3" [(set (match_operand:V8QI 0 "register_operand") (umaxmin:V8QI - (match_operand:V8QI 1 "nonimmediate_operand") - (match_operand:V8QI 2 "nonimmediate_operand")))] - "TARGET_SSE || TARGET_3DNOW_A" + (match_operand:V8QI 1 "register_mmxmem_operand") + (match_operand:V8QI 2 "register_mmxmem_operand")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "ix86_fixup_binary_operands_no_copy (, V8QImode, operands);") + +(define_expand "v8qi3" + [(set (match_operand:V8QI 0 "register_operand") + (umaxmin:V8QI + (match_operand:V8QI 1 "register_operand") + (match_operand:V8QI 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (, V8QImode, operands);") (define_insn "*mmx_v8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") + [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv") (umaxmin:V8QI - (match_operand:V8QI 1 "nonimmediate_operand" "%0") - (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] - "(TARGET_SSE || TARGET_3DNOW_A) + (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yv") + (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (, V8QImode, operands)" - "pb\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + "@ + pb\t{%2, %0|%0, %2} + pb\t{%2, %0|%0, %2} + vpb\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_ashr3" [(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,Yv") From patchwork Mon Feb 18 18:36:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. 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[73.93.86.59]) by smtp.gmail.com with ESMTPSA id g128sm17902108pfb.121.2019.02.18.10.37.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:13 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 55CBEC0352; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 19/41] i386: Emulate MMX mmx_pmovmskb with SSE Date: Mon, 18 Feb 2019 10:36:35 -0800 Message-Id: <20190218183657.16296-20-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb from QImode to SImode. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmovmskb): Changed to define_insn_and_split to support SSE emulation. --- gcc/config/i386/mmx.md | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index edfb8623701..5ae04de205d 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1763,14 +1763,30 @@ [(set_attr "type" "mmxshft") (set_attr "mode" "DI")]) -(define_insn "mmx_pmovmskb" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] +(define_insn_and_split "mmx_pmovmskb" + [(set (match_operand:SI 0 "register_operand" "=r,r") + (unspec:SI [(match_operand:V8QI 1 "register_operand" "y,x")] UNSPEC_MOVMSK))] - "TARGET_SSE || TARGET_3DNOW_A" - "pmovmskb\t{%1, %0|%0, %1}" - [(set_attr "type" "mmxcvt") - (set_attr "mode" "DI")]) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "@ + pmovmskb\t{%1, %0|%0, %1} + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(set (match_dup 0) + (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)) + (set (match_dup 0) + (zero_extend:SI (match_dup 2)))] +{ + /* Generate SSE pmovmskb and zero-extend from QImode to SImode. */ + operands[1] = lowpart_subreg (V16QImode, operands[1], + GET_MODE (operands[1])); + operands[2] = lowpart_subreg (QImode, operands[0], + GET_MODE (operands[0])); +} + [(set_attr "mmx_isa" "native,x64") + (set_attr "type" "mmxcvt,ssemov") + (set_attr "mode" "DI,TI")]) (define_expand "mmx_maskmovq" [(set (match_operand:V8QI 0 "memory_operand") From patchwork Mon Feb 18 18:36:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. 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[73.93.86.59]) by smtp.gmail.com with ESMTPSA id s73sm39513673pfi.124.2019.02.18.10.44.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:14 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 6242CC0353; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 20/41] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE Date: Mon, 18 Feb 2019 10:36:36 -0800 Message-Id: <20190218183657.16296-21-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_umulv4hi3_highpart): Add SSE emulation. --- gcc/config/i386/mmx.md | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 5ae04de205d..5a342256cbc 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -781,28 +781,34 @@ (lshiftrt:V4SI (mult:V4SI (zero_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand")) + (match_operand:V4HI 1 "register_mmxmem_operand")) (zero_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand"))) + (match_operand:V4HI 2 "register_mmxmem_operand"))) (const_int 16))))] - "TARGET_SSE || TARGET_3DNOW_A" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") (define_insn "*mmx_umulv4hi3_highpart" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (truncate:V4HI (lshiftrt:V4SI (mult:V4SI (zero_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "%0")) + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv")) (zero_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv"))) (const_int 16))))] - "(TARGET_SSE || TARGET_3DNOW_A) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (MULT, V4HImode, operands)" - "pmulhuw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxmul") - (set_attr "mode" "DI")]) + "@ + pmulhuw\t{%2, %0|%0, %2} + pmulhuw\t{%2, %0|%0, %2} + vpmulhuw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxmul,ssemul,ssemul") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_pmaddwd" [(set (match_operand:V2SI 0 "register_operand") From patchwork Mon Feb 18 18:36:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044266 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496558-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="j4RQQ7m5"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="d+bUMOM6"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CX64x07z9s1l for ; Tue, 19 Feb 2019 05:47:02 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=lkr R/2Ueuxem3jIwcJ3lpoPVZcMG0uavyvmDbpfkWnp7HNrqqP14jegs0dDdcdhI70e RiXYpRF8hZqRrJMsc4ahPpf1cUmvc7SmGoDDQYZLju441RWpUnSC/7HHFSbUenhD 6zFYDr14NO2YOG70hkLem4JnzwQ8dz1rUsIrUPd4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=839APznaQ J9ljICFcLHtXnJcRWo=; b=j4RQQ7m5234KmGPXz/zSmoxt+HpzHWpNZY8puyYsl 9n5RpDCBeDXli6ly+ld5OU79aLG1G+kcj+tFY3EiUFpaonE30TwMNfUdfw/R5o+v Tex9TEEwNUx0juwG77o9ZfL6mL9kWxFpOjW9ljEGhnWhYx8P/T3AaRnUpNhw2ccX sE= Received: (qmail 93954 invoked by alias); 18 Feb 2019 18:44:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91576 invoked by uid 89); 18 Feb 2019 18:44:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=__SIZE_TYPE__, __size_type__, HContent-Transfer-Encoding:8bit X-HELO: mail-pl1-f169.google.com Received: from mail-pl1-f169.google.com (HELO mail-pl1-f169.google.com) (209.85.214.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:20 +0000 Received: by mail-pl1-f169.google.com with SMTP id bj4so9148371plb.7 for ; Mon, 18 Feb 2019 10:44:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mJxoB46kDnXYhP5duvNLabcKUTGqihekjMlS7gmSNYw=; b=d+bUMOM6FrVOxPTcfGolc3FR2HgYWBwAHQRkC4FcCWcKQSjJ9Wv8EKedpEz3LAORs0 SikAU8l488MMywNrF1uqMbD0xGsamQJ+uv9e1a6K2drEHITX66R6mWPwotEwKQ9knjfU JR+E7snLRwPRslf/fDsH4rPe8xg/iifwGcvFRTHGiJAjMLTw5mJFugfDVrBtL73SMBN9 W1kYbps91k9O9+fhKb4+DGAmToWpM38VKWF0NWcB50/XdFb3C9qTzb4d2PZWuoscF8Db osgeGnRbYyaz70+cqeADsuUCmwziP8BqySKCPtE+8pLwx2ETd77neh64ZDChwy+/RVF2 lAQg== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id 4sm24296550pft.96.2019.02.18.10.44.13 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:14 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 6EA5EC0354; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 21/41] i386: Emulate MMX maskmovq with SSE2 maskmovdqu Date: Mon, 18 Feb 2019 10:36:37 -0800 Message-Id: <20190218183657.16296-22-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by zero-extending source and mask operands to 128 bits. Handle unmapped bits 64:127 at memory address by adjusting source and mask operands together with memory address. PR target/89021 * config/i386/xmmintrin.h: Emulate MMX maskmovq with SSE2 maskmovdqu for __MMX_WITH_SSE__. --- gcc/config/i386/xmmintrin.h | 61 +++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/gcc/config/i386/xmmintrin.h b/gcc/config/i386/xmmintrin.h index 58284378514..a915f6c87d7 100644 --- a/gcc/config/i386/xmmintrin.h +++ b/gcc/config/i386/xmmintrin.h @@ -1165,7 +1165,68 @@ _m_pshufw (__m64 __A, int const __N) extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P) { +#ifdef __MMX_WITH_SSE__ + /* Emulate MMX maskmovq with SSE2 maskmovdqu and handle unmapped bits + 64:127 at address __P. */ + typedef long long __v2di __attribute__ ((__vector_size__ (16))); + typedef char __v16qi __attribute__ ((__vector_size__ (16))); + /* Zero-extend __A and __N to 128 bits. */ + __v2di __A128 = __extension__ (__v2di) { ((__v1di) __A)[0], 0 }; + __v2di __N128 = __extension__ (__v2di) { ((__v1di) __N)[0], 0 }; + + /* Check the alignment of __P. */ + __SIZE_TYPE__ offset = ((__SIZE_TYPE__) __P) & 0xf; + if (offset) + { + /* If the misalignment of __P > 8, subtract __P by 8 bytes. + Otherwise, subtract __P by the misalignment. */ + if (offset > 8) + offset = 8; + __P = (char *) (((__SIZE_TYPE__) __P) - offset); + + /* Shift __A128 and __N128 to the left by the adjustment. */ + switch (offset) + { + case 1: + __A128 = __builtin_ia32_pslldqi128 (__A128, 8); + __N128 = __builtin_ia32_pslldqi128 (__N128, 8); + break; + case 2: + __A128 = __builtin_ia32_pslldqi128 (__A128, 2 * 8); + __N128 = __builtin_ia32_pslldqi128 (__N128, 2 * 8); + break; + case 3: + __A128 = __builtin_ia32_pslldqi128 (__A128, 3 * 8); + __N128 = __builtin_ia32_pslldqi128 (__N128, 3 * 8); + break; + case 4: + __A128 = __builtin_ia32_pslldqi128 (__A128, 4 * 8); + __N128 = __builtin_ia32_pslldqi128 (__N128, 4 * 8); + break; + case 5: + __A128 = __builtin_ia32_pslldqi128 (__A128, 5 * 8); + __N128 = __builtin_ia32_pslldqi128 (__N128, 5 * 8); + break; + case 6: + __A128 = __builtin_ia32_pslldqi128 (__A128, 6 * 8); + __N128 = __builtin_ia32_pslldqi128 (__N128, 6 * 8); + break; + case 7: + __A128 = __builtin_ia32_pslldqi128 (__A128, 7 * 8); + __N128 = __builtin_ia32_pslldqi128 (__N128, 7 * 8); + break; + case 8: + __A128 = __builtin_ia32_pslldqi128 (__A128, 8 * 8); + __N128 = __builtin_ia32_pslldqi128 (__N128, 8 * 8); + break; + default: + break; + } + } + __builtin_ia32_maskmovdqu ((__v16qi)__A128, (__v16qi)__N128, __P); +#else __builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P); +#endif } extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) From patchwork Mon Feb 18 18:36:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044260 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496552-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="A4rPWfOV"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="F9L87ajo"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CVW6D52z9s9G for ; Tue, 19 Feb 2019 05:45:39 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=cnr OX98BP5trobezcENNDqh+538DEO/M9ZIvdI489jqweti7dVjmrLoSNW10gKQbk5K /RWDnATRBovcqgTPCf5FJDYSaTLImTk6L6WLCXX4KIfZTe0UHJyBCAKgj67NEmR4 IQDwRWcGlzk9hudVmi7bYgkDBfIbHGOvTexKZDr0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=U2yYPsXex 5yxiyJ5DyszLZlnjM4=; b=A4rPWfOVbN+z1sLlIk7rrGedrWGirtTh+bCXfDue1 8iohcR607hdmWbGcqX3yFDpnYWTYbyH0SaQnaFnH0sy34piZirF9a9jpde3cKI4J kbelRGr3wjYY15lK/sRgxt456I5rt05FxkpPJOYelyIFUtyfAobjsCDlyN8CR64d +Y= Received: (qmail 90977 invoked by alias); 18 Feb 2019 18:44:18 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90893 invoked by uid 89); 18 Feb 2019 18:44:18 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pg1-f179.google.com Received: from mail-pg1-f179.google.com (HELO mail-pg1-f179.google.com) (209.85.215.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:16 +0000 Received: by mail-pg1-f179.google.com with SMTP id r11so8880447pgp.6 for ; Mon, 18 Feb 2019 10:44:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Tfujoa45wBZJ/oOZZqR8pURSrC7Y8FKpuo7JSeU4bf4=; b=F9L87ajohu5NtVa/mtCZtEu9hmpIXBe9r8hducGhipLZols9MESqbN7XparHo8XQc+ jmCdLks6bAC1+V6my9bibgrOKadwgoBNrS9KB57+2DXXqpeVmyVXLPBsA/tP75MBi45e okqnk2yUN7tvRdkhfyMKECqTEQsl0Gh4GATV6t/DPH+s2g7iQ3S3v3+qlO9VTgOn2a5w ei/b5mdGAGTT3CedgmdT777bfH7HA2PPDIz8mxDlPIrlljQMMfO6CQWP/mvoaljPDAek VAHl4t6Rcb7kOsWXiGVsiOKo1XhqW1/a8iZl6+whbaj9y7QvsH3LtMCL39MKmK+E/+YY vwuQ== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id k65sm14269933pge.74.2019.02.18.10.44.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:13 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 7B394C0355; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 22/41] i386: Emulate MMX mmx_uavgv8qi3 with SSE Date: Mon, 18 Feb 2019 10:36:38 -0800 Message-Id: <20190218183657.16296-23-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv8qi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 5a342256cbc..8866354dea9 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1679,50 +1679,55 @@ (plus:V8HI (plus:V8HI (zero_extend:V8HI - (match_operand:V8QI 1 "nonimmediate_operand")) + (match_operand:V8QI 1 "register_mmxmem_operand")) (zero_extend:V8HI - (match_operand:V8QI 2 "nonimmediate_operand"))) + (match_operand:V8QI 2 "register_mmxmem_operand"))) (const_vector:V8HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1)])) (const_int 1))))] - "TARGET_SSE || TARGET_3DNOW" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);") (define_insn "*mmx_uavgv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") + [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv") (truncate:V8QI (lshiftrt:V8HI (plus:V8HI (plus:V8HI (zero_extend:V8HI - (match_operand:V8QI 1 "nonimmediate_operand" "%0")) + (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yv")) (zero_extend:V8HI - (match_operand:V8QI 2 "nonimmediate_operand" "ym"))) + (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv"))) (const_vector:V8HI [(const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1) (const_int 1)])) (const_int 1))))] - "(TARGET_SSE || TARGET_3DNOW) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (PLUS, V8QImode, operands)" { /* These two instructions have the same operation, but their encoding is different. Prefer the one that is de facto standard. */ - if (TARGET_SSE || TARGET_3DNOW_A) + if (TARGET_MMX_WITH_SSE && TARGET_AVX) + return "vpavgb\t{%2, %1, %0|%0, %1, %2}"; + else if (TARGET_SSE || TARGET_3DNOW_A) return "pavgb\t{%2, %0|%0, %2}"; else return "pavgusb\t{%2, %0|%0, %2}"; } - [(set_attr "type" "mmxshft") + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxshft,sseiadd,sseiadd") (set (attr "prefix_extra") (if_then_else (not (ior (match_test "TARGET_SSE") (match_test "TARGET_3DNOW_A"))) (const_string "1") (const_string "*"))) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_uavgv4hi3" [(set (match_operand:V4HI 0 "register_operand") From patchwork Mon Feb 18 18:36:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044273 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496566-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="jnMR+ry8"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Zm33Veiq"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443Chb2WMHz9s3l for ; Tue, 19 Feb 2019 05:54:23 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=ANx QdiGxPXoYjwuw48IsWqILYuF3STbkNHpiT2noMsYNmh2n273vnxrJgPKvE5If+lH jTHdOoGbuHYmd4RUkTWJ9FuyAb1IdHC8T2gHwzeQMpqYO2KeqeAwPQJ50/H4dtyF XDEdrKuDPs7CV3ocC6j8VoPkdvegt7QXXfFWvS64= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=2224DYXVx me3orwpi2Zx1tAHcd0=; b=jnMR+ry8jqiizoNakInPQDhl7zjw8NKPz2fHsqv2e AdMrieh0qViBb5/q7RgUclUKKeqdWFIynQXDEoghRBfYl1aN4gUCWffreMo2iPqW U/I4kfMOL9VZWVqaPDCw671UvoCuDfycAeiU74j9fYPpNB/gIgT1Zl38IE3yDa2h jM= Received: (qmail 122152 invoked by alias); 18 Feb 2019 18:54:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 122124 invoked by uid 89); 18 Feb 2019 18:54:13 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=H*RU:209.85.215.193, Hx-spam-relays-external:209.85.215.193, HContent-Transfer-Encoding:8bit X-HELO: mail-pg1-f193.google.com Received: from mail-pg1-f193.google.com (HELO mail-pg1-f193.google.com) (209.85.215.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:54:12 +0000 Received: by mail-pg1-f193.google.com with SMTP id s198so8905086pgs.2 for ; Mon, 18 Feb 2019 10:54:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U9Jils2oGVoHEMy1++Y5pMCMOg9wSzTKrRDmphyaAcs=; b=Zm33Veiqc4uam2qVd69ZkVw2aOjkYDdwpg7u3Gls+p65v+PDyizXBVO3cDR2e07c8w Pfsw2a4OFs1bTjVbhgGN1s4+UG2nosZneU+bbszrIcaS28yAuERHxoIVXubKSwhGpXTY OAUXIpHz+qkhjPZVtEbM9RYV7EbrsfKbvxcYfH3OQPuhZTr5Kko7gRJhNq/vgDjb8VLO Gh275rgfABT4LuUhHSaP7cmZLQDYW3gRvLJog5QmmwiC0JCxQhlNf8rvBhawWKAVR5V/ zXBVjFtaSGVlAmmUkEg0Irn4epK23WphYqMqg1Atvqv0Y+R7C9m5NWMYeiJNP86RTpAQ Sxig== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id b7sm569253pfi.36.2019.02.18.10.54.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:54:09 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 877D4C0356; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 23/41] i386: Emulate MMX mmx_uavgv4hi3 with SSE Date: Mon, 18 Feb 2019 10:36:39 -0800 Message-Id: <20190218183657.16296-24-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_uavgv4hi3): Add SSE emulation. --- gcc/config/i386/mmx.md | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 8866354dea9..d647dc28baa 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1736,33 +1736,39 @@ (plus:V4SI (plus:V4SI (zero_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand")) + (match_operand:V4HI 1 "register_mmxmem_operand")) (zero_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand"))) + (match_operand:V4HI 2 "register_mmxmem_operand"))) (const_vector:V4SI [(const_int 1) (const_int 1) (const_int 1) (const_int 1)])) (const_int 1))))] - "TARGET_SSE || TARGET_3DNOW_A" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" "ix86_fixup_binary_operands_no_copy (PLUS, V4HImode, operands);") (define_insn "*mmx_uavgv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (truncate:V4HI (lshiftrt:V4SI (plus:V4SI (plus:V4SI (zero_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "%0")) + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv")) (zero_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv"))) (const_vector:V4SI [(const_int 1) (const_int 1) (const_int 1) (const_int 1)])) (const_int 1))))] - "(TARGET_SSE || TARGET_3DNOW_A) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (PLUS, V4HImode, operands)" - "pavgw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxshft") - (set_attr "mode" "DI")]) + "@ + pavgw\t{%2, %0|%0, %2} + pavgw\t{%2, %0|%0, %2} + vpavgw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxshft,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_psadbw" [(set (match_operand:V1DI 0 "register_operand" "=y") From patchwork Mon Feb 18 18:36:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044258 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496550-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="fN8V1vxB"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="GeXjblXF"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CTm6WpQz9rxp for ; Tue, 19 Feb 2019 05:45:00 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=HgD dNdHbyvruxV0VulDu2Jhs3ynpz8ngUEdAEMllxZ1hVZF7j4pP7pvD5lh7m/5AtRE 3tMPs/zHCVt2jTAFLvbeNn2azImsvpPGHJp0TJ/X0jtyn4mkvDyD6sq+UufyqLDE gj1TA/LHQOWXY+6TYJ6vVyktWEtINUzRZpslkDEc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=AxwU5dp4t wnjmGAyoq0atqrUBmk=; b=fN8V1vxBR+SPBtCC6S4rPKDUqxD3cn1JmZ/LJHpxh Mr7Gn27hS8Qrh5mE9FxalhHF9nqAk2kMsg1Ay0L+T2uP8LssVtIHdCjLm3OypedC /vC3LkBXAUhWAhJ85qBO2PQZR/4heSlN+rEQ74qAl1ePBDPHPoIy1ddVnOi8b3Wp IE= Received: (qmail 90651 invoked by alias); 18 Feb 2019 18:44:16 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90547 invoked by uid 89); 18 Feb 2019 18:44:16 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-pg1-f169.google.com Received: from mail-pg1-f169.google.com (HELO mail-pg1-f169.google.com) (209.85.215.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:14 +0000 Received: by mail-pg1-f169.google.com with SMTP id r124so8890976pgr.3 for ; Mon, 18 Feb 2019 10:44:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6iVVy1FYnq8SKXL1gHHPMzGvTJyXbvTIHSJ7BzVOP4c=; b=GeXjblXFxJUcIFCaHCg9n3kVGpIrc6FaV4H9aooO4n9Xnq9PfFvwHlzkdtGmwN3AES u8XYoeTnPLYW1C6tgJVhcaqXtGDPsO7+TmtumYy8ixU7wEm9XCXWBRkmMiO6KHgJXsDH zHcV+Gya88958XLT0PaIG6fkSsXbAfSQ1rU/U9JoHVgQe/7Mx3OARQyB+qeO6V2HVuJ2 CcliNzwlMbWxhQLBbDKQ+RkFbuqUoEOl81T3Gz7dnqOOCi3Wc906JhYPp/7rE+VFIlZ2 lshAfZGl+E5hx+lAllUWimnhPUV7/tizeAKFp2CaJa8XY/KGH+c9ZrtOaYTsvheg7Dda nsgw== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id a4sm5654828pga.52.2019.02.18.10.44.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:09 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 938F8C0357; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 24/41] i386: Emulate MMX mmx_psadbw with SSE Date: Mon, 18 Feb 2019 10:36:40 -0800 Message-Id: <20190218183657.16296-25-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_psadbw): Add SSE emulation. --- gcc/config/i386/mmx.md | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index d647dc28baa..098e41e19c3 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1771,14 +1771,19 @@ (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_psadbw" - [(set (match_operand:V1DI 0 "register_operand" "=y") - (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0") - (match_operand:V8QI 2 "nonimmediate_operand" "ym")] + [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv") + (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0,0,Yv") + (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")] UNSPEC_PSADBW))] - "TARGET_SSE || TARGET_3DNOW_A" - "psadbw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxshft") - (set_attr "mode" "DI")]) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "@ + psadbw\t{%2, %0|%0, %2} + psadbw\t{%2, %0|%0, %2} + vpsadbw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxshft,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_insn_and_split "mmx_pmovmskb" [(set (match_operand:SI 0 "register_operand" "=r,r") From patchwork Mon Feb 18 18:36:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044264 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496556-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="UIb23T1G"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ekyGpt78"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CWf4w78z9s9G for ; Tue, 19 Feb 2019 05:46:38 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=xdM gm1U/xpxcruZQrt+IYzpLuXiRFcANR+tV27nn5px8DwXABW8eqc9G7Yn5btMJGu3 nMUv53+h5wM4pMeSQ6YgiTmvnm4tlFco1Vq6iPGhG/DawAd/8fMXJCdgmaYdnjM4 PeVfcABFhYJTZvm1xoHWTiASlX2eSRn8zCHx8fRQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=+77A3GJDD BpG/AlyQwwOmTdhMRc=; b=UIb23T1GsBeka0bTKsfCOpoyM1DQPBg6LipSldfGY aPF/BtQGsWbuILlBJAO/f6EF3PIGDTiPfjBPs4POZjfyQrfJ+Cl0aG7urwfiF2hW GYUsbS9LNDI6qnKWFSLcXP067No6e0a83DDvP9feu5CPFsmEd00mPzqoACEdK3F8 Ck= Received: (qmail 91438 invoked by alias); 18 Feb 2019 18:44:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91251 invoked by uid 89); 18 Feb 2019 18:44:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-pf1-f181.google.com Received: from mail-pf1-f181.google.com (HELO mail-pf1-f181.google.com) (209.85.210.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:19 +0000 Received: by mail-pf1-f181.google.com with SMTP id n74so8998351pfi.9 for ; Mon, 18 Feb 2019 10:44:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CiETYUFwIwS0F4odSg4z58IDOFBJ/KCrUWCKCHd+Zj4=; b=ekyGpt78qtCUP3xH5QFIfOab37gGv/vrHGeGP/6lYzM4ws9P4l6ZfbDAnt/0AUzosd ly0WBOhvZFJ/mgqs8ATrf6d49N7xY2Iy2kYt9rpUD1sib0ubUL5SpZMszGRiY6pF+Ip8 p4+Qz0L/cmQ92NKzUt5YS6kec5NcKqN25OAnGoIOo6uISzbJ+Xo8eWwnfr7UPdSzO2X3 aiNiKEnx3EztxmSr2uXPw02P/sT0niGeT/ms8qoL8vpNGYOLHZLvrtap+19mDVNF7UPc MFIXVlSt0ywfMINtaArQrCxWZKzlKTdwEJcCNP1FOp73s6POnTgpGxWTBTf6kFAkrAIv t/IA== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id g7sm22243613pfm.10.2019.02.18.10.44.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:13 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 9FE35C0358; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 25/41] i386: Emulate MMX movntq with SSE2 movntidi Date: Mon, 18 Feb 2019 10:36:41 -0800 Message-Id: <20190218183657.16296-26-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX movntq with SSE2 movntidi. Only register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse_movntq): Add SSE2 emulation. --- gcc/config/i386/mmx.md | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 098e41e19c3..b06f0af984a 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -214,12 +214,16 @@ }) (define_insn "sse_movntq" - [(set (match_operand:DI 0 "memory_operand" "=m") - (unspec:DI [(match_operand:DI 1 "register_operand" "y")] + [(set (match_operand:DI 0 "memory_operand" "=m,m") + (unspec:DI [(match_operand:DI 1 "register_operand" "y,r")] UNSPEC_MOVNTQ))] - "TARGET_SSE || TARGET_3DNOW_A" - "movntq\t{%1, %0|%0, %1}" - [(set_attr "type" "mmxmov") + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "@ + movntq\t{%1, %0|%0, %1} + movnti\t{%1, %0|%0, %1}" + [(set_attr "mmx_isa" "native,x64") + (set_attr "type" "mmxmov,ssemov") (set_attr "mode" "DI")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; From patchwork Mon Feb 18 18:36:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044255 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496547-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="hkJDEeom"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="FXDXPzrM"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CT33cLnz9s9G for ; Tue, 19 Feb 2019 05:44:23 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=i6Q Mb5JqcvHj2eDVmUh/XMdc9WSJGGvzNMmRePXnKW8HDRKyiuBFC3zS5pj6bDC4WrT vE3jbmBzK+zyH5J6ssgRflzS6NI3rvtYK3v2cF8N/tBx91qywc6mnm9qopdGBaYc rBRUwtUqo5Yk92YAxhMW4I/4OHKlrcCBzbtN+hMc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=fm80maVqY W1i8eneTDkyczugaWg=; b=hkJDEeomnbY+N1WBVP+qESYbmaS5iNJ9uY/oH96Bj 1QwEmlh4WjxSuMcQbPAjX6+4B911b5xI7ipxekIRLkKjJfTbPtJDEK4olTWEfVKY VVxJgenyXYrwqnKm8aYJUaVsA4W4QaC/d2CmzUwti1DbLqQYHhlSNNcYZslqIneq bs= Received: (qmail 90189 invoked by alias); 18 Feb 2019 18:44:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90177 invoked by uid 89); 18 Feb 2019 18:44:14 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.4 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-pg1-f179.google.com Received: from mail-pg1-f179.google.com (HELO mail-pg1-f179.google.com) (209.85.215.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:12 +0000 Received: by mail-pg1-f179.google.com with SMTP id u9so5355737pgo.7 for ; Mon, 18 Feb 2019 10:44:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qx7MkfEklSwteST834wWUy0ChLxiOVLCiX5MIqwM8M4=; b=FXDXPzrMQbGgFiNrzxV68njn/2ysXlJXQ5UQopySE7rPU/tZyx67rxh5+xhkCssU40 Jp6nApl/toQYj2PMtSL+y7D0yrPDE2kk4fLikoFt5W3Bg0LqvTMlkgMURJAaIlgWjR7L 7iICuLjckdSzFASybCzlOpTykQNXI0w8f98mplaKgHKwXWgbT4iOP2an4F3DMypmUOR5 Qo5k9SBZfkqdy92vRqRdA4bx67NYlGv1kcu7mMDDcjxjFTUkUb4eyiDCFIC3mJup4Erl 4NVAF+QBytinMcESWuOPm8JLG6KI28TbkDypRxoVuR5pIxd/hcA4GDTaAb5PlosCUwxu FoJQ== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id t3sm26678691pfa.50.2019.02.18.10.44.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:09 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id AC656C0359; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 26/41] i386: Emulate MMX umulv1siv1di3 with SSE2 Date: Mon, 18 Feb 2019 10:36:42 -0800 Message-Id: <20190218183657.16296-27-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation support. (*sse2_umulv1siv1di3): Add SSE2 emulation. --- gcc/config/i386/mmx.md | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index b06f0af984a..f27513f7f2c 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -905,30 +905,36 @@ (mult:V1DI (zero_extend:V1DI (vec_select:V1SI - (match_operand:V2SI 1 "nonimmediate_operand") + (match_operand:V2SI 1 "register_mmxmem_operand") (parallel [(const_int 0)]))) (zero_extend:V1DI (vec_select:V1SI - (match_operand:V2SI 2 "nonimmediate_operand") + (match_operand:V2SI 2 "register_mmxmem_operand") (parallel [(const_int 0)])))))] - "TARGET_SSE2" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE2" "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);") (define_insn "*sse2_umulv1siv1di3" - [(set (match_operand:V1DI 0 "register_operand" "=y") + [(set (match_operand:V1DI 0 "register_operand" "=y,x,Yv") (mult:V1DI (zero_extend:V1DI (vec_select:V1SI - (match_operand:V2SI 1 "nonimmediate_operand" "%0") + (match_operand:V2SI 1 "register_mmxmem_operand" "%0,0,Yv") (parallel [(const_int 0)]))) (zero_extend:V1DI (vec_select:V1SI - (match_operand:V2SI 2 "nonimmediate_operand" "ym") + (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv") (parallel [(const_int 0)])))))] - "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)" - "pmuludq\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxmul") - (set_attr "mode" "DI")]) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && TARGET_SSE2 + && ix86_binary_operator_ok (MULT, V2SImode, operands)" + "@ + pmuludq\t{%2, %0|%0, %2} + pmuludq\t{%2, %0|%0, %2} + vpmuludq\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxmul,ssemul,ssemul") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_v4hi3" [(set (match_operand:V4HI 0 "register_operand") From patchwork Mon Feb 18 18:36:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044252 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496543-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="WTy1mEOt"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="e424kZRt"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CPh2NkZz9rxp for ; Tue, 19 Feb 2019 05:41:28 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=sMY 3madK4QFgWXn+NloRl0NAnH+BI7xQ8rHcf/f/yfNJvwhBBV0q++0QoI19iUpLhA2 ZPGSy15Wnvue2TjhRLdo1FMOsXZ5TYidIyqKjuXjNG8guyehtSD1vmvWUGkSBm8q +iIYVjj9cbNlASt2HTv6ytln+WLqRZRq7rJEAmwk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=+X7q/XR0o DeMyeyUP0OaluwgkD0=; b=WTy1mEOt37dJInvuJbWipWmO+Wwe4moP0ZXFRvXhY bmAhtFobxIG5F/Xe48+WFdTE94RPAWLDSEdt9k7Zn6OFFdVDaYQ04toZaAnZvAzv FknNJ+PXwIyFd+eTEvpyX+r4D+xkE+rxzj5fAakls4kyN1CXWy6dlkKnHFMD57eD 10= Received: (qmail 66120 invoked by alias); 18 Feb 2019 18:37:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 61826 invoked by uid 89); 18 Feb 2019 18:37:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-pg1-f169.google.com Received: from mail-pg1-f169.google.com (HELO mail-pg1-f169.google.com) (209.85.215.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:20 +0000 Received: by mail-pg1-f169.google.com with SMTP id s198so8885420pgs.2 for ; Mon, 18 Feb 2019 10:37:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PtfjuJjWZQags8oFItW6jXraUrkcAaZrbaKov89uO7I=; b=e424kZRtD6Fr5JejU2tcLvmkTlVcOsUeB5EdGRbndXxLCURtLXrG2ygR1iAUyoSilS ywbQETZ2UDA65YBgIKdN20iuIAF+Lsx8IQ+o1uw6UnP5jIKwuXoOZ5lHXyqAgHvODKMo DNFMC7xRHJ/zbJMyHytD7t6Qvp4Tg036t5WZST/VUoNm4Bynjush4wRfGp7IZGdSpV1f uWT2y/JgbGLmm9gcuvPD8lHD1u9f+Rec+UvDgdEtSHw5ka8YEYVCbG6tUsqUfff/Mgv+ jMk/yY8F8NR6HJxCMU9vvNwaGpQb6jlbswdSSsO6dvOknr3w7nB6j1Chc+teER22a6g0 Vopg== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id h15sm18208216pgl.43.2019.02.18.10.37.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:15 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id B8D70C035A; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 27/41] i386: Make _mm_empty () as NOP without MMX Date: Mon, 18 Feb 2019 10:36:43 -0800 Message-Id: <20190218183657.16296-28-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP without MMX. PR target/89021 * config/i386/mmx.md (mmx_): Renamed to ... (*mmx_): This. (mmx_): New expander. --- gcc/config/i386/mmx.md | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index f27513f7f2c..c48d42c7d59 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1849,7 +1849,35 @@ [(UNSPECV_EMMS "emms") (UNSPECV_FEMMS "femms")]) -(define_insn "mmx_" +(define_expand "mmx_" + [(parallel + [(unspec_volatile [(const_int 0)] EMMS) + (clobber (reg:XF ST0_REG)) + (clobber (reg:XF ST1_REG)) + (clobber (reg:XF ST2_REG)) + (clobber (reg:XF ST3_REG)) + (clobber (reg:XF ST4_REG)) + (clobber (reg:XF ST5_REG)) + (clobber (reg:XF ST6_REG)) + (clobber (reg:XF ST7_REG)) + (clobber (reg:DI MM0_REG)) + (clobber (reg:DI MM1_REG)) + (clobber (reg:DI MM2_REG)) + (clobber (reg:DI MM3_REG)) + (clobber (reg:DI MM4_REG)) + (clobber (reg:DI MM5_REG)) + (clobber (reg:DI MM6_REG)) + (clobber (reg:DI MM7_REG))])] + "TARGET_MMX || TARGET_MMX_WITH_SSE" +{ + if (!TARGET_MMX) + { + emit_insn (gen_nop ()); + DONE; + } +}) + +(define_insn "*mmx_" [(unspec_volatile [(const_int 0)] EMMS) (clobber (reg:XF ST0_REG)) (clobber (reg:XF ST1_REG)) From patchwork Mon Feb 18 18:36:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044274 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496567-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="L6eH+/r8"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="c6X7Bm0n"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443Chr2xyfz9s9G for ; Tue, 19 Feb 2019 05:54:36 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=NbK 2MEnnr5cO76BN4UkfYT8fqnQr9Y8RkklVx8fV259O136WivmyWTb1xZdaUAy3QF8 idiWDmyYzBxptinKOuaC0aqsfGquqCh2Jv+KifsLPQFbdqQEnzdmLEL8JL8exBmu /BVlWLb61QroooJqSuea82uIL1DD7fEMYUjE4zuE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=saJjg1q9Q pt+eJaCXoauqs1bXvA=; b=L6eH+/r8rh5n1vWXo8BUTl5eFx0lrz808ABbG2BGP uv+cmm+oG9uZZSiM5qSl0PEniS7oOqAZjN6+8xCImxsTBvB7L2yuMl+j7qXV857l J7MIVUUex32Yhyx1bOLVqWzJjGFE6fvINUy+Vc2L0s8Jy2vgO7yj+5JtmxKOuDCL Vg= Received: (qmail 122186 invoked by alias); 18 Feb 2019 18:54:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 122159 invoked by uid 89); 18 Feb 2019 18:54:14 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pg1-f173.google.com Received: from mail-pg1-f173.google.com (HELO mail-pg1-f173.google.com) (209.85.215.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:54:13 +0000 Received: by mail-pg1-f173.google.com with SMTP id u9so5365847pgo.7 for ; Mon, 18 Feb 2019 10:54:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H4A1f1ve6RA/aPQDFlbxfsVPpyAkypedr+uxqbXbdd0=; b=c6X7Bm0nDvUaG/3/Fxm/D8hcnEskF/mT1RbgDjI94La4NAUEj+OmR6YMY8uqX7PXgl /TdCXnFZgc8P9xMVFLTc2xe2TVXe5rEbpikchSPE7WCX0F5Fng8m5h8uLDqUwBWZfZOA fTajo+xKlH+I9oqscJ3rr3N8rG+j89wtwxXDxugT8R9eU+OmJ/QpGwIbQqAMcDb91B7r XOINEfyHfmdmqpc7BvD8PDvNid1NiqHiJmlvO7HyWb10CJ76+cJABa/sdI2Grh8sn2Ps CozbynphuZ3D0JjRxJetOEcrXrVllaFD1KGSUpNJLqt8IBzvsFR3nd33LcGlPPyL+2k1 TYrg== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id n73sm20306134pfj.148.2019.02.18.10.54.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:54:09 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id C56ADC035B; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 28/41] i386: Emulate MMX ssse3_phwv4hi3 with SSE Date: Mon, 18 Feb 2019 10:36:44 -0800 Message-Id: <20190218183657.16296-29-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX ssse3_phwv4hi3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phwv4hi3): Changed to define_insn_and_split to support SSE emulation. --- gcc/config/i386/sse.md | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 3135ce4eace..5f29f2c3595 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15243,13 +15243,13 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_insn "ssse3_phwv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") +(define_insn_and_split "ssse3_phwv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (vec_concat:V4HI (vec_concat:V2HI (ssse3_plusminus:HI (vec_select:HI - (match_operand:V4HI 1 "register_operand" "0") + (match_operand:V4HI 1 "register_operand" "0,0,Yv") (parallel [(const_int 0)])) (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))) (ssse3_plusminus:HI @@ -15258,19 +15258,37 @@ (vec_concat:V2HI (ssse3_plusminus:HI (vec_select:HI - (match_operand:V4HI 2 "nonimmediate_operand" "ym") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv") (parallel [(const_int 0)])) (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))) (ssse3_plusminus:HI (vec_select:HI (match_dup 2) (parallel [(const_int 2)])) (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))] - "TARGET_SSSE3" - "phw\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" + "@ + phw\t{%2, %0|%0, %2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] +{ + /* Generate SSE version of the operation. */ + rtx op0 = lowpart_subreg (V8HImode, operands[0], + GET_MODE (operands[0])); + rtx op1 = lowpart_subreg (V8HImode, operands[1], + GET_MODE (operands[1])); + rtx op2 = lowpart_subreg (V8HImode, operands[2], + GET_MODE (operands[2])); + emit_insn (gen_ssse3_phwv8hi3 (op0, op1, op2)); + ix86_move_vector_high_sse_to_mmx (op0); + DONE; +} + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "sseiadd") (set_attr "atom_unit" "complex") (set_attr "prefix_extra" "1") (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_insn "avx2_phdv8si3" [(set (match_operand:V8SI 0 "register_operand" "=x") From patchwork Mon Feb 18 18:36:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044275 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496568-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="mH3caDcY"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Jsw5JM40"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443Cj55Z7qz9s3l for ; Tue, 19 Feb 2019 05:54:49 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=Zih Vm3yEd4t0XlPQ6wDpVckKVByqszJ6GfMBSX+SEnGw/B4FVHDXARvFodrv6xUwrma Smy9bzPQNQ0PoYaqsVNfVasAdjzwMaYzzW6tyeKA6CREZzzQjIm59a3/J01qi3nd bn+KOiTViRiLy4ypHcfLLeia6sASsVrbXNmd1QYc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=RJLhzk6ad jjZhY9rVDl6OHsJ9W8=; b=mH3caDcYjkqsNmuB7GBIkneWFu73G1Q+qFMdPWAWT gxuWDJOf+Sq3qFdCAUeF8rg2NAJDqG4MKw2yJLt09449znIsjfTB5Dz7NhQuAkbN 5TD6Dj4SmKxqz6V93FFPDrzW3Lv8xGANlkRS7+wvUhNXEqjCQfI6FjMKmyGqgkC2 68= Received: (qmail 122430 invoked by alias); 18 Feb 2019 18:54:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 122309 invoked by uid 89); 18 Feb 2019 18:54:15 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pf1-f172.google.com Received: from mail-pf1-f172.google.com (HELO mail-pf1-f172.google.com) (209.85.210.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:54:13 +0000 Received: by mail-pf1-f172.google.com with SMTP id n125so1737747pfn.5 for ; Mon, 18 Feb 2019 10:54:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wnamIMFeG3eZhUj6vSql/0n7cglADzxtVKj5aLijDvs=; b=Jsw5JM40gWuRLPCfx0d0+RPzUxSFY0ajLj+oNSBbTj3pSXjsG0AZq60VRxfFITVRNU 1yfrzqiNL4qTzh7/U3x0hL7B1PUurxotT6saEn3bK+9m9Pl76iWN66IHfUbze92NMOmz SKssiv7L6uC3E/yLSvrRUAzQWZi4JwlIl2qo1lxHFfpYfQBxcQ0Nei7SBj/fzlH4rgXp UxLX2KssoySUuwo8kEJ8yK7KxTB3GAEyg2lXDZYqKxhAjXsu5hS57OKXNi8bfJtBMjfi xIGncfNGO9wYkmVqRHgJJrFrOkgd82GVsEnig1TrzQMbhvYTO0yMULGJznsILNh4cSAn vIKA== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id o6sm13026168pgo.27.2019.02.18.10.54.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:54:09 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id D1D38C035C; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 29/41] i386: Emulate MMX ssse3_phdv2si3 with SSE Date: Mon, 18 Feb 2019 10:36:45 -0800 Message-Id: <20190218183657.16296-30-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX ssse3_phdv2si3 with SSE by moving bits 64:95 to bits 32:63 in SSE register. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_phdv2si3): Changed to define_insn_and_split to support SSE emulation. --- gcc/config/i386/sse.md | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5f29f2c3595..551a1cb1eb2 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15367,26 +15367,44 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_insn "ssse3_phdv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y") +(define_insn_and_split "ssse3_phdv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv") (vec_concat:V2SI (plusminus:SI (vec_select:SI - (match_operand:V2SI 1 "register_operand" "0") + (match_operand:V2SI 1 "register_operand" "0,0,Yv") (parallel [(const_int 0)])) (vec_select:SI (match_dup 1) (parallel [(const_int 1)]))) (plusminus:SI (vec_select:SI - (match_operand:V2SI 2 "nonimmediate_operand" "ym") + (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv") (parallel [(const_int 0)])) (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))] - "TARGET_SSSE3" - "phd\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" + "@ + phd\t{%2, %0|%0, %2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(const_int 0)] +{ + /* Generate SSE version of the operation. */ + rtx op0 = lowpart_subreg (V4SImode, operands[0], + GET_MODE (operands[0])); + rtx op1 = lowpart_subreg (V4SImode, operands[1], + GET_MODE (operands[1])); + rtx op2 = lowpart_subreg (V4SImode, operands[2], + GET_MODE (operands[2])); + emit_insn (gen_ssse3_phdv4si3 (op0, op1, op2)); + ix86_move_vector_high_sse_to_mmx (op0); + DONE; +} + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "sseiadd") (set_attr "atom_unit" "complex") (set_attr "prefix_extra" "1") (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_insn "avx2_pmaddubsw256" [(set (match_operand:V16HI 0 "register_operand" "=x,v") From patchwork Mon Feb 18 18:36:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044270 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496562-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="sJ9sczLa"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JY2VxLgI"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CY85dBQz9s9G for ; Tue, 19 Feb 2019 05:47:56 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=F2j FhhVKuGpq68TFJ7THtnOKm/orra1Ao0jgZFgCsc5CQQnGThCA8Yv8ATjWdazVV4J Z9JjKielmOcWrJe/2LobgLYgHRWhqqI7FtYieJ7fM0uklK/ORQjtxUZ+InyrVJBU rBFDBiLETd8LZID3aaFfXmACcZ2P0mpCKXr/03ys= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=P/I77fIFw gJ3OAHGEootTSQetZc=; b=sJ9sczLaJfUaDV0oaQGScAu0LGW9AKZV5pUacUQTb mASSctlfMqJNBMems/4QQqckf/UFG6lAnVXjPdBoRQD2wsHSQPSb/E8FjvEBJStR 5J05p5UVR52hUpnxVBlIXgHFvIExqcjaVySK7DZvtRGYg7iOkN879qxjwtpGViRs zc= Received: (qmail 94524 invoked by alias); 18 Feb 2019 18:44:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 92056 invoked by uid 89); 18 Feb 2019 18:44:26 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-pl1-f179.google.com Received: from mail-pl1-f179.google.com (HELO mail-pl1-f179.google.com) (209.85.214.179) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:24 +0000 Received: by mail-pl1-f179.google.com with SMTP id g9so9162999plo.3 for ; Mon, 18 Feb 2019 10:44:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NyzICDeUYFSIOtIIoH2GDHBkWhBxiwvIfoPTLmMO37I=; b=JY2VxLgIr5q1OQUq9FfbnZYi6RCr7FclSaBeYqLtX36cIKEvhFI/UUTj6uAe7ZprNJ O0wUNs7lCB6pGZcZC2gx6/d2Ij4zvT4X3Sdfls3vdNi4smtEELdE2ke3sltcaJXpDhTN +SllbxI7z2+xGyP/sRJfUsWYXRGv5ZM6P/8g/QDnHdYG2B1H51mnyCjmVOeSAzb1xaUB Ld2+WFS/i+7cSo4ucSWoL6KCb682D/PUT7oCaVJKrVatQScscsqK12mw2Yk+Y6AbOEco cKjjmFFUmjyygyhviO8kf6iUJACr4/RrUAp11fDGVnKjpT8oxkRqzlwtz818jBrYeCld leDg== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id f8sm5263659pgs.77.2019.02.18.10.44.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:19 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id DE624C035D; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 30/41] i386: Emulate MMX ssse3_pmaddubsw with SSE Date: Mon, 18 Feb 2019 10:36:46 -0800 Message-Id: <20190218183657.16296-31-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation. --- gcc/config/i386/sse.md | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 551a1cb1eb2..e8d9bec9766 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15555,17 +15555,17 @@ (set_attr "mode" "TI")]) (define_insn "ssse3_pmaddubsw" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (ss_plus:V4HI (mult:V4HI (zero_extend:V4HI (vec_select:V4QI - (match_operand:V8QI 1 "register_operand" "0") + (match_operand:V8QI 1 "register_operand" "0,0,Yv") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (sign_extend:V4HI (vec_select:V4QI - (match_operand:V8QI 2 "nonimmediate_operand" "ym") + (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))) (mult:V4HI @@ -15577,13 +15577,17 @@ (vec_select:V4QI (match_dup 2) (parallel [(const_int 1) (const_int 3) (const_int 5) (const_int 7)]))))))] - "TARGET_SSSE3" - "pmaddubsw\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" + "@ + pmaddubsw\t{%2, %0|%0, %2} + pmaddubsw\t{%2, %0|%0, %2} + vpmaddubsw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "sseiadd") (set_attr "atom_unit" "simul") (set_attr "prefix_extra" "1") (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_mode_iterator PMULHRSW [V8HI (V16HI "TARGET_AVX2")]) From patchwork Mon Feb 18 18:36:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044251 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496542-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Zstwu2gr"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZRD3U8A6"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CPS2dhbz9rxp for ; Tue, 19 Feb 2019 05:41:16 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=pPs CNtBkLSuZENxNeItIROhRNjaRRZRAftlkZOihfR3O+UZ/F20szDnYV6VVSZkt4Kv uE//GHW/AFNIYJr+RjRau2qQBuYpRWgbWy9Ym45SVmg3BDzeAKUpqWDvzZSkF2yd tEiawsByGf/SwipMXSlbcFfPy8TFi6uSm+YtvoxU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=cNt8AoSli /RXql7r3tNXRtTIO5w=; b=Zstwu2gr9zwPauK8RtEkmad1zu+xqoUOrgisv7FZg VdMDpO6yN+Mo6ujjrAoo5HrQ4Dx1orhSpUamN4c15FGCF0dA7NAZ9ecCOtidoPRA HJvRbaKVrWT/lqwcUCR1WyUob3SDqdeKERou+7DfwNlfZGnzNjU1qAPbG7Yzl+kv yA= Received: (qmail 64553 invoked by alias); 18 Feb 2019 18:37:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 61670 invoked by uid 89); 18 Feb 2019 18:37:21 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-pf1-f193.google.com Received: from mail-pf1-f193.google.com (HELO mail-pf1-f193.google.com) (209.85.210.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:37:19 +0000 Received: by mail-pf1-f193.google.com with SMTP id j5so4490715pfa.2 for ; Mon, 18 Feb 2019 10:37:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o8QkBGGCtupRzkaSvy5PrEiuYxO0aofx3xuPT9awVwk=; b=ZRD3U8A6/7lxvBk8Gt12qXeGvLouATTXxw/i5RCgySUeYNe9+Gj2O2hA0XEIlz3Vk/ HsxbHkLciHhb6XJrDVe0DNmkHXgqqrYQciQTIkL/63kVZT8vZZsY2tpwqg/h8lciRwhZ SgaNm/1dGkrGI+5klsBlL2f2uBJpSChIQMJzFLGeLHzPqiyG0UGt5x947TdWHVEftx6t 3X5oxC32YyV/kIIXb7jSX2J95E12CCMUcgav2dNkHZXYQXiMS/uLwy228vmWhYaGHShx IVGAVQUf06uEmOdO/swWnXOKbG7IVAEqWxcCdpZaH5JAVYbv6rS1XcOa3531M2rS+sJf cSVA== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id z185sm20872624pfb.17.2019.02.18.10.37.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:15 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id EAF5FC035E; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 31/41] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE Date: Mon, 18 Feb 2019 10:36:47 -0800 Message-Id: <20190218183657.16296-32-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pmulhrswv4hi3): Require TARGET_MMX or TARGET_MMX_WITH_SSE. (*ssse3_pmulhrswv4hi3): Add SSE emulation. --- gcc/config/i386/sse.md | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e8d9bec9766..b08a577d1e4 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15670,38 +15670,44 @@ (lshiftrt:V4SI (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand")) + (match_operand:V4HI 1 "register_mmxmem_operand")) (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand"))) + (match_operand:V4HI 2 "register_mmxmem_operand"))) (const_int 14)) (match_dup 3)) (const_int 1))))] - "TARGET_SSSE3" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" { operands[3] = CONST1_RTX(V4HImode); ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands); }) (define_insn "*ssse3_pmulhrswv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (truncate:V4HI (lshiftrt:V4SI (plus:V4SI (lshiftrt:V4SI (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "%0")) + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv")) (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv"))) (const_int 14)) (match_operand:V4HI 3 "const1_operand")) (const_int 1))))] - "TARGET_SSSE3 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" - "pmulhrsw\t{%2, %0|%0, %2}" - [(set_attr "type" "sseimul") + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && TARGET_SSSE3 + && !(MEM_P (operands[1]) && MEM_P (operands[2]))" + "@ + pmulhrsw\t{%2, %0|%0, %2} + pmulhrsw\t{%2, %0|%0, %2} + vpmulhrsw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "sseimul") (set_attr "prefix_extra" "1") (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_insn "_pshufb3" [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,x,v") From patchwork Mon Feb 18 18:36:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044268 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496560-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Lk4bFxq0"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MQWR4aeV"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CXf1NxDz9s1l for ; Tue, 19 Feb 2019 05:47:29 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=wiH J6fZZFRaMHmYY6WBz/loqq6oH/ZcQC0M/4aUASLW46TPpaqynwuJc9FrYto6Kgl2 jwpKJW7QMwgqR6jEqu3h4zawHg/xUd+C0jTAkXFxGe4yH4t4NrZFxL1Sk90y+FgL pWFmWuTW5Mjdw0lLuUEz2/f1XXSp5CcJYZK+RQxY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=RAUuu3ktm cnMn5ppfNh7g863fCY=; b=Lk4bFxq0SgERTPNkE0MRwPN8xg7TEzexlW1phQsvp J+7z04HrbGgLMVg9dI4buibXQJwMId5DIXat73cwXQZdi+x97XaBrA3wUy49D/HO ys8mKyNz1k7JOv2cRagPpmg4lp/QXScxy92PcTCck27iaGE5rAhXxkPltIRi/Osx a8= Received: (qmail 94225 invoked by alias); 18 Feb 2019 18:44:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91970 invoked by uid 89); 18 Feb 2019 18:44:26 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pf1-f194.google.com Received: from mail-pf1-f194.google.com (HELO mail-pf1-f194.google.com) (209.85.210.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:23 +0000 Received: by mail-pf1-f194.google.com with SMTP id n74so8998455pfi.9 for ; Mon, 18 Feb 2019 10:44:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YX0Sm5eH86di0p8gUvqMLyXQT2YLn9k1iipu7cprKEc=; b=MQWR4aeV6I6W12InxJjllTiL+9lmqV9CZ0xBhR9NCINX6v0LeOt5pREPQ5HQ49F5T1 kgZxWYXlAlapjHgKoKMvzYxJ421NBYundDAlx6f4kPgmrHuun7jbjibBdXcQJVq8vU9Y YaVuTIXe6NMCpUMhHhK/IzktcYVwvR5lgQyE4PT8T7+jcJaTCASXQz2qD2CctlEf65zC Xu1fB4+SF8Tddfszhc24barAAsQ+dE7DvVRdKtJIUYKCV5eClP1Gr/tHhcU7c9wa8L72 VAzbYnSXPoD7YpEBSY9Kijy4lRmaJeydnLUEC24mfvzawMalwcnnV6s5NzxseWzjzPAY xD2A== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id o16sm15786943pgv.41.2019.02.18.10.44.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:18 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 041C8C035F; Mon, 18 Feb 2019 10:36:59 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 32/41] i386: Emulate MMX pshufb with SSE version Date: Mon, 18 Feb 2019 10:36:48 -0800 Message-Id: <20190218183657.16296-33-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX version of pshufb with SSE version by masking out the bit 3 of the shuffle control byte. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_pshufbv8qi3): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add SSE emulation. --- gcc/config/i386/sse.md | 46 +++++++++++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 9 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b08a577d1e4..79b35d95424 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15728,17 +15728,45 @@ (set_attr "btver2_decode" "vector") (set_attr "mode" "")]) -(define_insn "ssse3_pshufbv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") - (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0") - (match_operand:V8QI 2 "nonimmediate_operand" "ym")] - UNSPEC_PSHUFB))] - "TARGET_SSSE3" - "pshufb\t{%2, %0|%0, %2}"; - [(set_attr "type" "sselog1") +(define_insn_and_split "ssse3_pshufbv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv") + (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,0,Yv") + (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")] + UNSPEC_PSHUFB)) + (clobber (match_scratch:V4SI 3 "=X,x,Yv"))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" + "@ + pshufb\t{%2, %0|%0, %2} + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(set (match_dup 3) (match_dup 5)) + (set (match_dup 3) + (and:V4SI (match_dup 3) (match_dup 2))) + (set (match_dup 0) + (unspec:V16QI [(match_dup 1) (match_dup 4)] UNSPEC_PSHUFB))] +{ + /* Emulate MMX version of pshufb with SSE version by masking out the + bit 3 of the shuffle control byte. */ + operands[0] = lowpart_subreg (V16QImode, operands[0], + GET_MODE (operands[0])); + operands[1] = lowpart_subreg (V16QImode, operands[1], + GET_MODE (operands[1])); + operands[2] = lowpart_subreg (V4SImode, operands[2], + GET_MODE (operands[2])); + operands[4] = lowpart_subreg (V16QImode, operands[3], + GET_MODE (operands[3])); + rtvec par = gen_rtvec (4, GEN_INT (0xf7f7f7f7), + GEN_INT (0xf7f7f7f7), + GEN_INT (0xf7f7f7f7), + GEN_INT (0xf7f7f7f7)); + rtx vec_const = gen_rtx_CONST_VECTOR (V4SImode, par); + operands[5] = force_const_mem (V4SImode, vec_const); +} + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") (set_attr "prefix_extra" "1") (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_insn "_psign3" [(set (match_operand:VI124_AVX2 0 "register_operand" "=x,x") From patchwork Mon Feb 18 18:36:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044257 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496549-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="UQjJehpJ"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="I1wozhgY"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CTX1g6Tz9rxp for ; Tue, 19 Feb 2019 05:44:48 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=Dd9 uAIDublRrcELblY4gn3BZ6nvr+xE2yMYkOPnsckkAZaM90Uc00IqJzlR2xMl69M4 toyeyBgYZvFNWrjmz8eGpGFrOWOdxhl1CjxPvK9j9Zhp+VBGTcWArU2Lv4ELXL4a vYS15ZIMj3QJaGLy2z1jOwVOuQ+UqiQIyNqEtyV0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=BXusIANLY DIlAaedC+m2H5kok5U=; b=UQjJehpJ0NV50iJfP+0ZCG/OyLdOb0bn2ySjJ2jUc wyErcPAE3D/t/OC+Q1bhyAswdGIo5PqvWJA9mn8Uw01hOIiip5E0kH5fAuxTJZUt boD/q8TevhZQ+b56QGLk+LcOjmxH11Eozz6ryKKNfipEFZ3v3kD0VhHWloje8BHo Nw= Received: (qmail 90432 invoked by alias); 18 Feb 2019 18:44:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90233 invoked by uid 89); 18 Feb 2019 18:44:14 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Received:ab8f, HContent-Transfer-Encoding:8bit X-HELO: mail-pl1-f170.google.com Received: from mail-pl1-f170.google.com (HELO mail-pl1-f170.google.com) (209.85.214.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:13 +0000 Received: by mail-pl1-f170.google.com with SMTP id g9so9162834plo.3 for ; Mon, 18 Feb 2019 10:44:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yuCtJ1aO9uMRTZG/1bkZH1fwGJ4dGkCOCWKn+kO8U00=; b=I1wozhgYoOAY+pe56uoBoDk6JyxjXRdk2tjAQJm++AXOrZqqQmF8EWUuohRwpGvcY8 e3uyxQ7qDEoSBitPBUzNfEsTNK7HhrCH6ac7S+Z8nhphHmCQG0QUVq98Wl4na0UZ+HN3 CBuq4q+QBZxWXkxH7BaQCORqCypLJhGaNglHMNC1jzQPHmjSEUJGUUwONjB7h17Ohevs OfJjJ8twz8PT118qDBvznIDTtiw5+pxQ72J+rOvkeuPnTXRLgtgq/F+wEidrThmazsHx bdV0cmUMlCGW0Gwnp/TJA+LzK8ZowC52oCJizlXYpBrc4pRxBfJmmfDdRGv+XcCLqwgs FCmg== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id g7sm22243547pfm.10.2019.02.18.10.44.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:09 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 10F93C0360; Mon, 18 Feb 2019 10:36:59 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 33/41] i386: Emulate MMX ssse3_psign3 with SSE Date: Mon, 18 Feb 2019 10:36:49 -0800 Message-Id: <20190218183657.16296-34-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_psign3): Add SSE emulation. --- gcc/config/i386/sse.md | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 79b35d95424..1d90af0a4b0 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15786,17 +15786,21 @@ (set_attr "mode" "")]) (define_insn "ssse3_psign3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") (unspec:MMXMODEI - [(match_operand:MMXMODEI 1 "register_operand" "0") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")] + [(match_operand:MMXMODEI 1 "register_operand" "0,0,Yv") + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")] UNSPEC_PSIGN))] - "TARGET_SSSE3" - "psign\t{%2, %0|%0, %2}"; - [(set_attr "type" "sselog1") + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" + "@ + psign\t{%2, %0|%0, %2} + psign\t{%2, %0|%0, %2} + vpsign\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_insn "_palignr_mask" [(set (match_operand:VI1_AVX512 0 "register_operand" "=v") From patchwork Mon Feb 18 18:36:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044256 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496548-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="MdyE9r8G"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WwlEDK97"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CTJ2qJJz9s9G for ; Tue, 19 Feb 2019 05:44:35 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=jxu a7Q/8c3M4FIOQVHqrOkeuKmruk0ZQ2gYWddBTcjkZ6bRoFixskMMOlZY5fwMkgvi 4AhSJsaQqaNjZ0eE47U6KqpPBziuFwqeDVj3Adq4lCnnv9gnI8xPoWeJ7eq1txrW YBWMZ0LDGQC1WnQIGlLFUPqSJMbnf6GVjrozZHTU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=4viKeqvi0 5LQ0mBRv6eBKdB1GEc=; b=MdyE9r8G37LGvJ5nsJYnO5IP8Sp5mHpCK+JD1uBED RHbUh8/v09jUMbPNydQj6GCzTe3XJFOeZ5qiqwGibmGJuK5QVYQxzkLqs7Yj2ZQB fuJorA54AxwHTFI/b1DADPxOnA6rt/PbLSbY0pxvo6UNkMBIHe7Sn2oEdjJKmu+h FM= Received: (qmail 90371 invoked by alias); 18 Feb 2019 18:44:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90202 invoked by uid 89); 18 Feb 2019 18:44:14 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=nnn X-HELO: mail-pg1-f177.google.com Received: from mail-pg1-f177.google.com (HELO mail-pg1-f177.google.com) (209.85.215.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:13 +0000 Received: by mail-pg1-f177.google.com with SMTP id r11so8880390pgp.6 for ; Mon, 18 Feb 2019 10:44:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YiLIMGgh5/uk5Chy3zn8Np5N0Frq/7QMkrwyuPbQUo4=; b=WwlEDK97Rxg8Z+YhkXT4IxFmLjoP3fRpbyzIoVZ/b9Do3ql9qNuec81C8MmbA+kkcw EF6xzXqjD9ifdd1CSZnYwnwraFfWQkWSfHYhaSqQiLtQ4yHyZbLCHoIXr5K7z624vkwq C+qyU8suj8F7xbeMffNxXsTnwLzaI53XWLIfMX8JqejursgBugkTgIzxLY/xtHLyjnH2 wKyqUlobxSqpnYd7Pz9odP0ZS6ok+fN7+l2zRNGgyZVDITMb0lSO8YoTMWzoap7q4FBM UlL1qMM8xa2uHnkieO9jbF/r92/8Bqn4gr8TVW3yeC3waR0V2Ck035ne1jf94oVVSe2O yP4Q== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id v9sm15945471pgs.3.2019.02.18.10.44.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:09 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 1DD1CC0361; Mon, 18 Feb 2019 10:36:59 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 34/41] i386: Emulate MMX ssse3_palignrdi with SSE Date: Mon, 18 Feb 2019 10:36:50 -0800 Message-Id: <20190218183657.16296-35-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX version of palignrq with SSE version by concatenating 2 64-bit MMX operands into a single 128-bit SSE operand, followed by SSE psrldq. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (ssse3_palignrdi): Changed to define_insn_and_split to support SSE emulation. --- gcc/config/i386/sse.md | 58 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 48 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1d90af0a4b0..b69a467291c 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15855,23 +15855,61 @@ (set_attr "prefix" "orig,vex,evex") (set_attr "mode" "")]) -(define_insn "ssse3_palignrdi" - [(set (match_operand:DI 0 "register_operand" "=y") - (unspec:DI [(match_operand:DI 1 "register_operand" "0") - (match_operand:DI 2 "nonimmediate_operand" "ym") - (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")] +(define_insn_and_split "ssse3_palignrdi" + [(set (match_operand:DI 0 "register_operand" "=y,x,Yv") + (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv") + (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yv") + (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n,n")] UNSPEC_PALIGNR))] - "TARGET_SSSE3" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" { - operands[3] = GEN_INT (INTVAL (operands[3]) / 8); - return "palignr\t{%3, %2, %0|%0, %2, %3}"; + switch (which_alternative) + { + case 0: + operands[3] = GEN_INT (INTVAL (operands[3]) / 8); + return "palignr\t{%3, %2, %0|%0, %2, %3}"; + case 1: + case 2: + return "#"; + default: + gcc_unreachable (); + } } - [(set_attr "type" "sseishft") + "TARGET_MMX_WITH_SSE && reload_completed" + [(set (match_dup 0) + (lshiftrt:V1TI (match_dup 0) (match_dup 3)))] +{ + /* Emulate MMX palignrdi with SSE psrldq. */ + rtx op0 = lowpart_subreg (V2DImode, operands[0], + GET_MODE (operands[0])); + rtx insn; + if (TARGET_AVX) + insn = gen_vec_concatv2di (op0, operands[2], operands[1]); + else + { + /* NB: SSE can only concatenate OP0 and OP1 to OP0. */ + insn = gen_vec_concatv2di (op0, operands[1], operands[2]); + emit_insn (insn); + /* Swap bits 0:63 with bits 64:127. */ + rtx mask = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (4, GEN_INT (2), + GEN_INT (3), + GEN_INT (0), + GEN_INT (1))); + rtx op1 = lowpart_subreg (V4SImode, op0, GET_MODE (op0)); + rtx op2 = gen_rtx_VEC_SELECT (V4SImode, op1, mask); + insn = gen_rtx_SET (op1, op2); + } + emit_insn (insn); + operands[0] = lowpart_subreg (V1TImode, op0, GET_MODE (op0)); +} + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "sseishft") (set_attr "atom_unit" "sishuf") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) ;; Mode iterator to handle singularity w/ absence of V2DI and V4DI ;; modes for abs instruction on pre AVX-512 targets. From patchwork Mon Feb 18 18:36:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. 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[73.93.86.59]) by smtp.gmail.com with ESMTPSA id s6sm30118343pgm.90.2019.02.18.10.44.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:09 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 2A7A1C0362; Mon, 18 Feb 2019 10:36:59 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 35/41] i386: Emulate MMX abs2 with SSE Date: Mon, 18 Feb 2019 10:36:51 -0800 Message-Id: <20190218183657.16296-36-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX abs2 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/sse.md (abs2): Add SSE emulation. --- gcc/config/i386/sse.md | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b69a467291c..97ec3795b82 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15973,16 +15973,19 @@ }) (define_insn "abs2" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,Yv") (abs:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))] - "TARGET_SSSE3" - "pabs\t{%1, %0|%0, %1}"; - [(set_attr "type" "sselog1") + (match_operand:MMXMODEI 1 "register_mmxmem_operand" "ym,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" + "@ + pabs\t{%1, %0|%0, %1} + %vpabs\t{%1, %0|%0, %1}" + [(set_attr "mmx_isa" "native,x64") + (set_attr "type" "sselog1") (set_attr "prefix_rep" "0") (set_attr "prefix_extra" "1") (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; From patchwork Mon Feb 18 18:36:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044261 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496553-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="LVzUHI2t"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="qwhq++a6"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CVx69cCz9rxp for ; Tue, 19 Feb 2019 05:46:01 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; q=dns; s= default; b=nquX/GT62m9/7E7des8TIN5F8NPCaIrbEnMczxwQHWwn3uG9SUUh1 CfgY1TQe7tFOdSAWpEaWLYGdwMjMsNtv3RtEgqLBKy3j6mS/xlF1xrWa/Bmp5gT1 JWBGM1e3Eqk2qqomqLeMgFpmMiOIGSsaiAFH0j6fq6BUYJgR93IB30= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=default; bh=0f2unGROnAF3mQCjp2yxSkhsniI=; b=LVzUHI2tB+96I50iAuaAysqufBB5 JTBpzXbCarFV1Lu7s+OBUEs+9D3LusivnrX/p3QvJ2jsiNG9tECBMuzz4AEfu5LM 6/1qYDUR7mad76LKjJ4MiSpExlq2Kd64VoJqfRLsMxvBncnSTRLo6t4BZDaGCOgN wa0UvZqRb8IMBpc= Received: (qmail 91283 invoked by alias); 18 Feb 2019 18:44:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91195 invoked by uid 89); 18 Feb 2019 18:44:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=*1 X-HELO: mail-pg1-f175.google.com Received: from mail-pg1-f175.google.com (HELO mail-pg1-f175.google.com) (209.85.215.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:18 +0000 Received: by mail-pg1-f175.google.com with SMTP id i130so8905128pgd.1 for ; Mon, 18 Feb 2019 10:44:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zDKGKwd56ZDTBsNi+1h7BoVN0X3VZF62pRnk+fPApjs=; b=qwhq++a6Rx3ZP/0BAZRHWeYtlZgdYDAhVczUk+JDVlSLjvnprUJYYeDJF4+b77waOq dnAGqzd9P9lUeWRKS2zcHCJRmjTl39BqpIupsMFJhxjnsFAvW6bpD7RKb0s4FdwOoWUi nHeiT03FLOCHSLsnkK3pPXsBJWiLyfXpwUtL34rpJdcdBHTsZNAKQU3wsKPvuHP9CR1M 6FocEk6c2CI66XSBNDyBGgb8HtbkMUlAVhFBLol0jEnNTaqBoUp/wN3vlinlfD+VLMEv DixBxxtemQ9UEBQcQo4l4XLWsCXauIBHj26Nd+UQZGeS6EJfLUrlu91d9THNZCaHyOPZ Ztlg== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id g185sm20985026pfc.174.2019.02.18.10.44.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:13 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 36DF4C0363; Mon, 18 Feb 2019 10:36:59 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 36/41] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE Date: Mon, 18 Feb 2019 10:36:52 -0800 Message-Id: <20190218183657.16296-37-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes From: Uros Bizjak 2019-02-18 Uroš Bizjak PR target/89021 * config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute. * config/i386/sse.md (sse2_cvtpi2pd): Ditto. (sse2_cvtpd2pi): Ditto. (sse2_cvttpd2pi): Ditto. (*vec_concatv2sf_sse4_1): Ditto. (*vec_concatv2sf_sse): Ditto. (*vec_concatv2si_sse4_1): Ditto. (*vec_concatv2si): Ditto. (*vec_concatv4si_0): Ditto. (*vec_concatv2di_0): Ditto. --- gcc/config/i386/i386.md | 4 ++++ gcc/config/i386/sse.md | 25 ++++++++++++++++++++----- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 04ec0eeaa57..4cbbd4cf685 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3683,6 +3683,10 @@ (const_string "avx512bw") ] (const_string "*"))) + (set (attr "mmx_isa") + (if_then_else (eq_attr "alternative" "5,6") + (const_string "native") + (const_string "*"))) (set (attr "type") (cond [(eq_attr "alternative" "0,1,2,4") (const_string "multi") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 97ec3795b82..96d4e5001d8 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4971,7 +4971,8 @@ "@ %vcvtdq2pd\t{%1, %0|%0, %1} cvtpi2pd\t{%1, %0|%0, %1}" - [(set_attr "type" "ssecvt") + [(set_attr "mmx_isa" "*,native") + (set_attr "type" "ssecvt") (set_attr "unit" "*,mmx") (set_attr "prefix_data16" "*,1") (set_attr "prefix" "maybe_vex,*") @@ -4985,7 +4986,8 @@ "@ * return TARGET_AVX ? \"vcvtpd2dq{x}\t{%1, %0|%0, %1}\" : \"cvtpd2dq\t{%1, %0|%0, %1}\"; cvtpd2pi\t{%1, %0|%0, %1}" - [(set_attr "type" "ssecvt") + [(set_attr "mmx_isa" "*,native") + (set_attr "type" "ssecvt") (set_attr "unit" "*,mmx") (set_attr "amdfam10_decode" "double") (set_attr "athlon_decode" "vector") @@ -5001,7 +5003,8 @@ "@ * return TARGET_AVX ? \"vcvttpd2dq{x}\t{%1, %0|%0, %1}\" : \"cvttpd2dq\t{%1, %0|%0, %1}\"; cvttpd2pi\t{%1, %0|%0, %1}" - [(set_attr "type" "ssecvt") + [(set_attr "mmx_isa" "*,native") + (set_attr "type" "ssecvt") (set_attr "unit" "*,mmx") (set_attr "amdfam10_decode" "double") (set_attr "athlon_decode" "vector") @@ -7209,6 +7212,10 @@ (const_string "mmxmov") ] (const_string "sselog"))) + (set (attr "mmx_isa") + (if_then_else (eq_attr "alternative" "7,8") + (const_string "native") + (const_string "*"))) (set (attr "prefix_data16") (if_then_else (eq_attr "alternative" "3,4") (const_string "1") @@ -7244,7 +7251,8 @@ movss\t{%1, %0|%0, %1} punpckldq\t{%2, %0|%0, %2} movd\t{%1, %0|%0, %1}" - [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov") + [(set_attr "mmx_isa" "*,*,native,native") + (set_attr "type" "sselog,ssemov,mmxcvt,mmxmov") (set_attr "mode" "V4SF,SF,DI,DI")]) (define_insn "*vec_concatv4sf" @@ -14520,6 +14528,10 @@ punpckldq\t{%2, %0|%0, %2} movd\t{%1, %0|%0, %1}" [(set_attr "isa" "noavx,noavx,avx,avx512dq,noavx,noavx,avx,*,*,*") + (set (attr "mmx_isa") + (if_then_else (eq_attr "alternative" "8,9") + (const_string "native") + (const_string "*"))) (set (attr "type") (cond [(eq_attr "alternative" "7") (const_string "ssemov") @@ -14557,6 +14569,7 @@ punpckldq\t{%2, %0|%0, %2} movd\t{%1, %0|%0, %1}" [(set_attr "isa" "sse2,sse2,*,*,*,*") + (set_attr "mmx_isa" "*,*,*,*,native,native") (set_attr "type" "sselog,ssemov,sselog,ssemov,mmxcvt,mmxmov") (set_attr "mode" "TI,TI,V4SF,SF,DI,DI")]) @@ -14586,7 +14599,8 @@ "@ %vmovq\t{%1, %0|%0, %1} movq2dq\t{%1, %0|%0, %1}" - [(set_attr "type" "ssemov") + [(set_attr "mmx_isa" "*,native") + (set_attr "type" "ssemov") (set_attr "prefix" "maybe_vex,orig") (set_attr "mode" "TI")]) @@ -14661,6 +14675,7 @@ %vmovq\t{%1, %0|%0, %1} movq2dq\t{%1, %0|%0, %1}" [(set_attr "isa" "x64,*,*") + (set_attr "mmx_isa" "*,*,native") (set_attr "type" "ssemov") (set_attr "prefix_rex" "1,*,*") (set_attr "prefix" "maybe_vex,maybe_vex,orig") From patchwork Mon Feb 18 18:36:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044271 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496563-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="XYpMqd4G"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="uPAbAASK"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CYP21xjz9s1l for ; Tue, 19 Feb 2019 05:48:09 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=AZj F7+8uXvFWPbhS3corESMVl6+fOy3XtsPYOw6gmLqsb70dzAA9VL4yOS2IL1vogxM NIyG63I/50WdSXNlKOqU3amPLng6Ruw9F5kx636JsRTSvqzk7iBeNh/3rUtfz0vI v6dWnwiQCg5z6B5OXeM/Cx/PYgOJrxanynlEawJU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=gfq2REH/1 2xLrVdkJbvDcHmHEMo=; b=XYpMqd4GVTyvu58JiHUSz+t74rcO+u5SRCWdplNzD RiZyWUU7Jj77otnkRT7k/uTmGfCn1wQ1VcicE4fV0LKzwyx0Z0dTd01W0B7P6bIe HGOeD7bLr4OHiiKwrQ7AyewiIxUBOYLpXdBBrfBL9ZVs3PvEx+Mf5DxaqEo8Ef13 Gs= Received: (qmail 94656 invoked by alias); 18 Feb 2019 18:44:46 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91962 invoked by uid 89); 18 Feb 2019 18:44:26 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=ym, HContent-Transfer-Encoding:8bit X-HELO: mail-pl1-f170.google.com Received: from mail-pl1-f170.google.com (HELO mail-pl1-f170.google.com) (209.85.214.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:24 +0000 Received: by mail-pl1-f170.google.com with SMTP id g9so9162989plo.3 for ; Mon, 18 Feb 2019 10:44:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VGStokMiO6ckgh65OGGy6XHu94J8/amfgQRi66R3GEg=; b=uPAbAASKuZYMyLUF5H5m1ddMF2g+40yx1X60t9soFB63cNVNe1980FM26j638agq6J vR44aerQJBYAYiSL9qzODezUQDCvE+KwPVpzv0Jg592D0+mN7WxRTtCRLxCqoXRpjgTv pQVUanI/qyKIByWVPkit8+MGWE8W6VZsSEpDMfRxsPPUnONf8MB3v2cLQHR3QglLZWpe Miv5JRsXOKQmxrSsQITIRpq6PtS+o1Rel3DKBNiILDJchYgMgbltY6PW4dfzCV/tiQSZ Cx2UYVTT5MjpHfoTn7G+obC/Ao5fnwNVAf4mZYujBMuQ8kE4q3t7eHZmy27Pgc9LgeN8 QaYQ== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id m9sm11923386pfi.31.2019.02.18.10.44.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:19 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 43511C0364; Mon, 18 Feb 2019 10:36:59 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 37/41] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE Date: Mon, 18 Feb 2019 10:36:53 -0800 Message-Id: <20190218183657.16296-38-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes PR target/89021 * config/i386/mmx.md (MMXMODE:mov): Also allow TARGET_MMX_WITH_SSE. (MMXMODE:*mov_internal): Likewise. (MMXMODE:movmisalign): Likewise. --- gcc/config/i386/mmx.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index c48d42c7d59..b230dee521f 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -70,7 +70,7 @@ (define_expand "mov" [(set (match_operand:MMXMODE 0 "nonimmediate_operand") (match_operand:MMXMODE 1 "nonimmediate_operand"))] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" { ix86_expand_vector_move (mode, operands); DONE; @@ -81,7 +81,7 @@ "=r ,o ,r,r ,m ,?!y,!y,?!y,m ,r ,?!y,v,v,v,m,r,v,!y,*x") (match_operand:MMXMODE 1 "nonimm_or_0_operand" "rCo,rC,C,rm,rC,C ,!y,m ,?!y,?!y,r ,C,v,m,v,v,r,*x,!y"))] - "TARGET_MMX + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && !(MEM_P (operands[0]) && MEM_P (operands[1]))" { switch (get_attr_type (insn)) @@ -207,7 +207,7 @@ (define_expand "movmisalign" [(set (match_operand:MMXMODE 0 "nonimmediate_operand") (match_operand:MMXMODE 1 "nonimmediate_operand"))] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" { ix86_expand_vector_move (mode, operands); DONE; From patchwork Mon Feb 18 18:36:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044263 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496555-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="wuy0aUzl"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gVLLqt/v"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CWP6VMHz9s1l for ; Tue, 19 Feb 2019 05:46:25 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=m77 Jpbc6QHAIck2+YzfDEb40l2SU/Rd1n3ZQ9Bc8OiX3G7JmK+76a/lpHOz4PYt/Lyi aPPcWlAGzA4+UZYtq+78KJsMgXHVlyOxVOsyMe4JVJC10MDFd8uUPfJuiLjODEHd VhwglgOoz+wchocDXYKeHFqVWwaGO1KVkvL7do0E= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=NiqhG1pbd U3oaQKkZVQ8vEO9Ys0=; b=wuy0aUzlEz+1W4Hz8RsXNhG411WqLXznDnUJSMJat nAEPikWCsHavVRACES2S4vfpLaPZ5mZA/wVzgSJoj0R/eWYS9++sXTuZL6WI9Y6t Krrhd//fp4E7MsVH6/OLvGc2EOCMmQ5LSNcAjC4kMJnyJR5qjuX1KmIypI1B0xDs P8= Received: (qmail 91392 invoked by alias); 18 Feb 2019 18:44:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91258 invoked by uid 89); 18 Feb 2019 18:44:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pf1-f181.google.com Received: from mail-pf1-f181.google.com (HELO mail-pf1-f181.google.com) (209.85.210.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:17 +0000 Received: by mail-pf1-f181.google.com with SMTP id f132so9006503pfa.6 for ; Mon, 18 Feb 2019 10:44:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Atnb5z1mSDUB6ruaoZFYzAnKvKaiSEHkYidODQZBLeE=; b=gVLLqt/vcbDnC0O0u/OVu98BJcjNwmZ8dXG6ZWeUxWMbjjH+jtvWHmt3rAy4v9VbAf gnNNcQUBWecPLSeHgkPqnrZQG8EzCgDiYoeFr1ta4ifCShXcDmSfbQ7sZphuKHpKAupl 8wWn7VKDzYUYVqxLlRYdOi6sJVZR1g5e77ipee5honcdqBZx+94yJmGnDlGLTCUDLbuA 1BhY9/6kIylkUBq73anpVRiPgRHIjjHkq3vULULkBK+uOoZ/shx7Jku5qodmDEUO+lWQ FZ+hvVfssqNF7NaqVyAm6WsXvIZQ675OGU7HvxMe+3tt1T6AdXLC97oIxF+AExeKzbh2 PSyg== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id n10sm26032606pfj.14.2019.02.18.10.44.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:13 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 502E9C0365; Mon, 18 Feb 2019 10:36:59 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 38/41] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE Date: Mon, 18 Feb 2019 10:36:54 -0800 Message-Id: <20190218183657.16296-39-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes PR target/89021 * config/i386/mmx.md (*vec_dupv2sf): Changed to define_insn_and_split to support SSE emulation. (*vec_extractv2sf_0): Likewise. (*vec_extractv2sf_1): Likewise. (*vec_extractv2si_0): Likewise. (*vec_extractv2si_1): Likewise. (*vec_extractv2si_zext_mem): Likewise. (vec_setv2sf): Also allow TARGET_MMX_WITH_SSE. (vec_extractv2sf_1 splitter): Likewise. (vec_extractv2sfsf): Likewise. (vec_setv2si): Likewise. (vec_extractv2si_1 splitter): Likewise. (vec_extractv2sisi): Likewise. (vec_setv4hi): Likewise. (vec_extractv4hihi): Likewise. (vec_setv8qi): Likewise. (vec_extractv8qiqi): Likewise. (vec_extractv2sfsf): Also allow TARGET_MMX_WITH_SSE. Pass TARGET_MMX_WITH_SSE ix86_expand_vector_extract. (vec_extractv2sisi): Likewise. (vec_extractv4hihi): Likewise. (vec_extractv8qiqi): Likewise. (vec_initv2sfsf): Also allow TARGET_MMX_WITH_SSE. Pass TARGET_MMX_WITH_SSE to ix86_expand_vector_init. (vec_initv2sisi): Likewise. (vec_initv4hihi): Likewise. (vec_initv8qiqi): Likewise. (vec_setv2si): Also allow TARGET_MMX_WITH_SSE. Pass TARGET_MMX_WITH_SSE to ix86_expand_vector_set. (vec_setv4hi): Likewise. (vec_setv8qi): Likewise. --- gcc/config/i386/mmx.md | 110 ++++++++++++++++++++++++----------------- 1 file changed, 66 insertions(+), 44 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index b230dee521f..479568aa322 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -555,14 +555,23 @@ (set_attr "prefix_extra" "1") (set_attr "mode" "V2SF")]) -(define_insn "*vec_dupv2sf" - [(set (match_operand:V2SF 0 "register_operand" "=y") +(define_insn_and_split "*vec_dupv2sf" + [(set (match_operand:V2SF 0 "register_operand" "=y,x,Yv") (vec_duplicate:V2SF - (match_operand:SF 1 "register_operand" "0")))] - "TARGET_MMX" - "punpckldq\t%0, %0" - [(set_attr "type" "mmxcvt") - (set_attr "mode" "DI")]) + (match_operand:SF 1 "register_operand" "0,0,Yv")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + punpckldq\t%0, %0 + # + #" + "TARGET_MMX_WITH_SSE && reload_completed" + [(set (match_dup 0) + (vec_duplicate:V4SF (match_dup 1)))] + "operands[0] = lowpart_subreg (V4SFmode, operands[0], + GET_MODE (operands[0]));" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcvt,ssemov,ssemov") + (set_attr "mode" "DI,TI,TI")]) (define_insn "*mmx_concatv2sf" [(set (match_operand:V2SF 0 "register_operand" "=y,y") @@ -580,9 +589,9 @@ [(match_operand:V2SF 0 "register_operand") (match_operand:SF 1 "register_operand") (match_operand 2 "const_int_operand")] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" { - ix86_expand_vector_set (false, operands[0], operands[1], + ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1], INTVAL (operands[2])); DONE; }) @@ -594,11 +603,13 @@ (vec_select:SF (match_operand:V2SF 1 "nonimmediate_operand" " xm,x,ym,y,m,m") (parallel [(const_int 0)])))] - "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 1))] - "operands[1] = gen_lowpart (SFmode, operands[1]);") + "operands[1] = gen_lowpart (SFmode, operands[1]);" + [(set_attr "mmx_isa" "*,*,native,native,*,*")]) ;; Avoid combining registers from different units in a single alternative, ;; see comment above inline_secondary_memory_needed function in i386.c @@ -607,7 +618,8 @@ (vec_select:SF (match_operand:V2SF 1 "nonimmediate_operand" " 0,x,x,o,o,o,o") (parallel [(const_int 1)])))] - "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ punpckhdq\t%0, %0 %vmovshdup\t{%1, %0|%0, %1} @@ -617,6 +629,7 @@ # #" [(set_attr "isa" "*,sse3,noavx,*,*,*,*") + (set_attr "mmx_isa" "native,*,*,native,*,*,*") (set_attr "type" "mmxcvt,sse,sseshuf1,mmxmov,ssemov,fmov,imov") (set (attr "length_immediate") (if_then_else (eq_attr "alternative" "2") @@ -634,7 +647,7 @@ (vec_select:SF (match_operand:V2SF 1 "memory_operand") (parallel [(const_int 1)])))] - "TARGET_MMX && reload_completed" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed" [(set (match_dup 0) (match_dup 1))] "operands[1] = adjust_address (operands[1], SFmode, 4);") @@ -642,19 +655,20 @@ [(match_operand:SF 0 "register_operand") (match_operand:V2SF 1 "register_operand") (match_operand 2 "const_int_operand")] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" { - ix86_expand_vector_extract (false, operands[0], operands[1], - INTVAL (operands[2])); + ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0], + operands[1], INTVAL (operands[2])); DONE; }) (define_expand "vec_initv2sfsf" [(match_operand:V2SF 0 "register_operand") (match_operand 1)] - "TARGET_SSE" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE" { - ix86_expand_vector_init (false, operands[0], operands[1]); + ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0], + operands[1]); DONE; }) @@ -1526,9 +1540,9 @@ [(match_operand:V2SI 0 "register_operand") (match_operand:SI 1 "register_operand") (match_operand 2 "const_int_operand")] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" { - ix86_expand_vector_set (false, operands[0], operands[1], + ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1], INTVAL (operands[2])); DONE; }) @@ -1540,11 +1554,13 @@ (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "xm,x,ym,y,m") (parallel [(const_int 0)])))] - "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 1))] - "operands[1] = gen_lowpart (SImode, operands[1]);") + "operands[1] = gen_lowpart (SImode, operands[1]);" + [(set_attr "mmx_isa" "*,*,native,native,*")]) ;; Avoid combining registers from different units in a single alternative, ;; see comment above inline_secondary_memory_needed function in i386.c @@ -1553,7 +1569,8 @@ (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" " 0,x,x,o,o,o") (parallel [(const_int 1)])))] - "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ punpckhdq\t%0, %0 %vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5} @@ -1562,6 +1579,7 @@ # #" [(set_attr "isa" "*,sse2,noavx,*,*,*") + (set_attr "mmx_isa" "native,*,*,native,*,*") (set_attr "type" "mmxcvt,sseshuf1,sseshuf1,mmxmov,ssemov,imov") (set (attr "length_immediate") (if_then_else (eq_attr "alternative" "1,2") @@ -1575,7 +1593,7 @@ (vec_select:SI (match_operand:V2SI 1 "memory_operand") (parallel [(const_int 1)])))] - "TARGET_MMX && reload_completed" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && reload_completed" [(set (match_dup 0) (match_dup 1))] "operands[1] = adjust_address (operands[1], SImode, 4);") @@ -1592,25 +1610,27 @@ { operands[1] = adjust_address (operands[1], SImode, INTVAL (operands[2]) * 4); } - [(set_attr "isa" "*,sse2,*")]) + [(set_attr "isa" "*,sse2,*") + (set_attr "mmx_isa" "native,*,*")]) (define_expand "vec_extractv2sisi" [(match_operand:SI 0 "register_operand") (match_operand:V2SI 1 "register_operand") (match_operand 2 "const_int_operand")] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" { - ix86_expand_vector_extract (false, operands[0], operands[1], - INTVAL (operands[2])); + ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0], + operands[1], INTVAL (operands[2])); DONE; }) (define_expand "vec_initv2sisi" [(match_operand:V2SI 0 "register_operand") (match_operand 1)] - "TARGET_SSE" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE" { - ix86_expand_vector_init (false, operands[0], operands[1]); + ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0], + operands[1]); DONE; }) @@ -1618,9 +1638,9 @@ [(match_operand:V4HI 0 "register_operand") (match_operand:HI 1 "register_operand") (match_operand 2 "const_int_operand")] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" { - ix86_expand_vector_set (false, operands[0], operands[1], + ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1], INTVAL (operands[2])); DONE; }) @@ -1629,19 +1649,20 @@ [(match_operand:HI 0 "register_operand") (match_operand:V4HI 1 "register_operand") (match_operand 2 "const_int_operand")] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" { - ix86_expand_vector_extract (false, operands[0], operands[1], - INTVAL (operands[2])); + ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0], + operands[1], INTVAL (operands[2])); DONE; }) (define_expand "vec_initv4hihi" [(match_operand:V4HI 0 "register_operand") (match_operand 1)] - "TARGET_SSE" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE" { - ix86_expand_vector_init (false, operands[0], operands[1]); + ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0], + operands[1]); DONE; }) @@ -1649,9 +1670,9 @@ [(match_operand:V8QI 0 "register_operand") (match_operand:QI 1 "register_operand") (match_operand 2 "const_int_operand")] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" { - ix86_expand_vector_set (false, operands[0], operands[1], + ix86_expand_vector_set (TARGET_MMX_WITH_SSE, operands[0], operands[1], INTVAL (operands[2])); DONE; }) @@ -1660,19 +1681,20 @@ [(match_operand:QI 0 "register_operand") (match_operand:V8QI 1 "register_operand") (match_operand 2 "const_int_operand")] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" { - ix86_expand_vector_extract (false, operands[0], operands[1], - INTVAL (operands[2])); + ix86_expand_vector_extract (TARGET_MMX_WITH_SSE, operands[0], + operands[1], INTVAL (operands[2])); DONE; }) (define_expand "vec_initv8qiqi" [(match_operand:V8QI 0 "register_operand") (match_operand 1)] - "TARGET_SSE" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE" { - ix86_expand_vector_init (false, operands[0], operands[1]); + ix86_expand_vector_init (TARGET_MMX_WITH_SSE, operands[0], + operands[1]); DONE; }) From patchwork Mon Feb 18 18:36:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. 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[73.93.86.59]) by smtp.gmail.com with ESMTPSA id h79sm20914287pfj.186.2019.02.18.10.37.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:15 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 5C8B2C0366; Mon, 18 Feb 2019 10:36:59 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 39/41] i386: Allow MMX intrinsic emulation with SSE Date: Mon, 18 Feb 2019 10:36:55 -0800 Message-Id: <20190218183657.16296-40-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA by default with TARGET_MMX_WITH_SSE. For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit mode since MMX intrinsics can be emulated wit SSE. gcc/ PR target/89021 * config/i386/i386-builtin.def: Enable MMX intrinsics with SSE/SSE2/SSSE3. * config/i386/i386.c (ix86_init_mmx_sse_builtins): Likewise. (ix86_expand_builtin): Allow SSE/SSE2/SSSE3 to emulate MMX intrinsics with TARGET_MMX_WITH_SSE. * config/i386/mmintrin.h: Only require SSE2 if __MMX_WITH_SSE__ is defined. gcc/testsuite/ PR target/89021 * gcc.target/i386/pr82483-1.c: Error only on ia32. * gcc.target/i386/pr82483-2.c: Likewise. --- gcc/config/i386/i386-builtin.def | 126 +++++++++++----------- gcc/config/i386/i386.c | 29 ++++- gcc/config/i386/mmintrin.h | 12 ++- gcc/testsuite/gcc.target/i386/pr82483-1.c | 2 +- gcc/testsuite/gcc.target/i386/pr82483-2.c | 2 +- 5 files changed, 101 insertions(+), 70 deletions(-) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 88005f4687f..10a9d631f29 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -100,7 +100,7 @@ BDESC (0, 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKN BDESC (0, 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID) /* MMX */ -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID) /* 3DNow! */ BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID) @@ -442,68 +442,68 @@ BDESC (0, 0, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNO BDESC (0, 0, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT) /* MMX */ -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) - -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) - -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) - -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) - -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) - -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) - -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI) - -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI) - -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT) - -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT) - -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT) -BDESC (OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) + +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) + +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) + +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) + +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) + +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI) + +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI) + +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI) + +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT) + +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT) + +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT) +BDESC (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT) /* 3DNow! */ BDESC (OPTION_MASK_ISA_3DNOW, 0, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 3db41555462..93769003a4a 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -31777,14 +31777,17 @@ ix86_init_mmx_sse_builtins (void) VOID_FTYPE_UNSIGNED, IX86_BUILTIN_XABORT); /* MMX access to the vec_init patterns. */ - def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v2si", + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, + "__builtin_ia32_vec_init_v2si", V2SI_FTYPE_INT_INT, IX86_BUILTIN_VEC_INIT_V2SI); - def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v4hi", + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, + "__builtin_ia32_vec_init_v4hi", V4HI_FTYPE_HI_HI_HI_HI, IX86_BUILTIN_VEC_INIT_V4HI); - def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_init_v8qi", + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, + "__builtin_ia32_vec_init_v8qi", V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI, IX86_BUILTIN_VEC_INIT_V8QI); @@ -31806,7 +31809,8 @@ ix86_init_mmx_sse_builtins (void) "__builtin_ia32_vec_ext_v4hi", HI_FTYPE_V4HI_INT, IX86_BUILTIN_VEC_EXT_V4HI); - def_builtin_const (OPTION_MASK_ISA_MMX, 0, "__builtin_ia32_vec_ext_v2si", + def_builtin_const (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, + "__builtin_ia32_vec_ext_v2si", SI_FTYPE_V2SI_INT, IX86_BUILTIN_VEC_EXT_V2SI); def_builtin_const (OPTION_MASK_ISA_SSE2, 0, "__builtin_ia32_vec_ext_v16qi", @@ -36939,6 +36943,23 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, == (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) && (isa & (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4)) != 0) isa |= (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4); + /* Use SSE/SSE2/SSSE3 to emulate MMX intrinsics in 64-bit mode when + MMX is disabled. */ + if (TARGET_MMX_WITH_SSE) + { + if (((bisa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) + == (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) + && (isa & (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX)) != 0) + isa |= (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX); + if (((bisa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX)) + == (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX)) + && (isa & (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX)) != 0) + isa |= (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX); + if (((bisa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX)) + == (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX)) + && (isa & (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX)) != 0) + isa |= (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX); + } if ((bisa & isa) != bisa || (bisa2 & isa2) != bisa2) { char *opts = ix86_target_string (bisa, bisa2, 0, 0, NULL, NULL, diff --git a/gcc/config/i386/mmintrin.h b/gcc/config/i386/mmintrin.h index 238b3df3121..c4b2e0c7b25 100644 --- a/gcc/config/i386/mmintrin.h +++ b/gcc/config/i386/mmintrin.h @@ -29,7 +29,9 @@ #if defined __x86_64__ && !defined __SSE__ || !defined __MMX__ #pragma GCC push_options -#ifdef __x86_64__ +#ifdef __MMX_WITH_SSE__ +#pragma GCC target("sse2") +#elif defined __x86_64__ #pragma GCC target("sse,mmx") #else #pragma GCC target("mmx") @@ -315,7 +317,11 @@ _m_paddd (__m64 __m1, __m64 __m2) /* Add the 64-bit values in M1 to the 64-bit values in M2. */ #ifndef __SSE2__ #pragma GCC push_options +#ifdef __MMX_WITH_SSE__ +#pragma GCC target("sse2") +#else #pragma GCC target("sse2,mmx") +#endif #define __DISABLE_SSE2__ #endif /* __SSE2__ */ @@ -427,7 +433,11 @@ _m_psubd (__m64 __m1, __m64 __m2) /* Add the 64-bit values in M1 to the 64-bit values in M2. */ #ifndef __SSE2__ #pragma GCC push_options +#ifdef __MMX_WITH_SSE__ +#pragma GCC target("sse2") +#else #pragma GCC target("sse2,mmx") +#endif #define __DISABLE_SSE2__ #endif /* __SSE2__ */ diff --git a/gcc/testsuite/gcc.target/i386/pr82483-1.c b/gcc/testsuite/gcc.target/i386/pr82483-1.c index 59a59dc8dfe..b2028d8dc5e 100644 --- a/gcc/testsuite/gcc.target/i386/pr82483-1.c +++ b/gcc/testsuite/gcc.target/i386/pr82483-1.c @@ -1,7 +1,7 @@ /* PR target/82483 */ /* { dg-do compile } */ /* { dg-options "-mssse3 -mno-mmx -Wno-psabi" } */ -/* { dg-error "needs isa option" "" { target *-*-* } 0 } */ +/* { dg-error "needs isa option" "" { target ia32 } 0 } */ #include diff --git a/gcc/testsuite/gcc.target/i386/pr82483-2.c b/gcc/testsuite/gcc.target/i386/pr82483-2.c index 305ddbd6c64..c92de405cb3 100644 --- a/gcc/testsuite/gcc.target/i386/pr82483-2.c +++ b/gcc/testsuite/gcc.target/i386/pr82483-2.c @@ -1,7 +1,7 @@ /* PR target/82483 */ /* { dg-do compile } */ /* { dg-options "-mssse3 -mno-mmx -Wno-psabi" } */ -/* { dg-error "needs isa option" "" { target *-*-* } 0 } */ +/* { dg-error "needs isa option" "" { target ia32 } 0 } */ #include From patchwork Mon Feb 18 18:36:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044269 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496561-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="KOWXe7rA"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XWJa4fp5"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CXv2z8Tz9s1l for ; Tue, 19 Feb 2019 05:47:43 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=SaJ RSxyZLz2KgruUZn2RQ9UW/EH/tSSiQGgjch+xvJ0lF6HSkQkMYEjzu/McE0/3Rm4 gnDyUptUnrGdrZrmL25j4nW6FoMJM+dCgUpn1HVeJ/hum1cUqp77g6YiZHbjVwQ8 nCfBBfUZwYeiq1UgPKe+a6lk0zk0XRXJgqY37n00= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=ozUM7qufq PmrWlIea8XFJXDp8Ww=; b=KOWXe7rAeJ3my0x34d3zDiGBF4kW5DKO9HBA4oQkH +mbV/Mg4e0IV/J4Er8+2pL2dluMeDRBl/cWerC+z7YqL7Vt6RsNY9A9oeMB/9P3/ cp2+X/fEwTcvdFyGg0jvznXNx81pSEgIbWjCX4BbSDiprz0LM7MoAee2UVuJJADc dg= Received: (qmail 94352 invoked by alias); 18 Feb 2019 18:44:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 92315 invoked by uid 89); 18 Feb 2019 18:44:29 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.4 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_PASS, UPPERCASE_50_75 autolearn=ham version=3.3.2 spammy=HX-Received:2bc9, H*RU:209.85.214.196, Hx-spam-relays-external:209.85.214.196, HContent-Transfer-Encoding:8bit X-HELO: mail-pl1-f196.google.com Received: from mail-pl1-f196.google.com (HELO mail-pl1-f196.google.com) (209.85.214.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:25 +0000 Received: by mail-pl1-f196.google.com with SMTP id p8so9158699plo.2 for ; Mon, 18 Feb 2019 10:44:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T83nOY+Oy4Vk7mWumLaXBoXGMxVZuI0d7QB0v7tWk2I=; b=XWJa4fp5rydZ19ErQJM3Q3ifrM/kgIIfjjVFkNQbO8S90VsSjOclXIL2heb9ygi1Fx zKFqFWQyWHUjlCv4yo2Qk4di32J0MEUlFavo5DqGn71jjRaDkbT6HJezVxuEGm+D8Waf Gbml2LB039ur1XVUrGL28EdEVa3NgNFesUNofAhLAWuJ8NYpnwiqiu5r/qwu+6DKGJxv xPp5THzrGp/W9//y18XWD1f5mTqKR8HVgBwqbpmniJAyuIdYaNqIzoC7zqx66CKId267 RI7of/d6d2pTTqbo8EmR8D4eDMZq5BcFCQj2ZTPqEbfvs70mmbIQ4gIqK+3/T1N6Vyr9 5Rrg== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id i8sm27858869pfj.18.2019.02.18.10.44.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:18 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 68F3FC0367; Mon, 18 Feb 2019 10:36:59 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 40/41] i386: Enable TM MMX intrinsics with SSE2 Date: Mon, 18 Feb 2019 10:36:56 -0800 Message-Id: <20190218183657.16296-41-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes This pach enables TM MMX intrinsics with SSE2 when MMX is disabled. PR target/89021 * config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with SSE2. --- gcc/config/i386/i386.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 93769003a4a..a28a3f04129 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -31078,13 +31078,13 @@ static const struct builtin_description bdesc_##kind[] = \ we're lazy. Add casts to make them fit. */ static const struct builtin_description bdesc_tm[] = { - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI }, - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI }, - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI }, - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI }, - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI }, - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI }, - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI }, + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI }, + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI }, + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI }, + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI }, + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI }, + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI }, + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI }, { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF }, { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF }, @@ -31102,7 +31102,7 @@ static const struct builtin_description bdesc_tm[] = { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF }, { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF }, - { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID }, + { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID }, { OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID }, { OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID }, }; From patchwork Mon Feb 18 18:36:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1044272 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-496564-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Bj8OqsF4"; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="TLHzR6mw"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 443CZ34SYQz9s3l for ; Tue, 19 Feb 2019 05:48:43 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=Uhv CuKzYgFdU11Nj1I6WSxWlOZbV6neqJbFAtCZpDyIR2LdgP0l8nYklAaSS5OnRXF1 fGdjBFOM8MAKxJt2UUjBzW/9GZpTth3bNdzwsVx2Kd1mVXmjp3Wspzt/EkWxRflR TA7nVgOKbeL7j4i4V5sY4AdeePQnmb+Ts4wkIRd4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=RdbOLlg1Y IbSBFbZHryxjZJJ7UQ=; b=Bj8OqsF4mMfkX50YQlngpuKIUKUig4YHzmWinKNkz 8W6x63HN+PkyTNPrP/auDLlfQSlSemx9rtf5KszpWRFH2nyMi2GcSopkk/Qe+qvP 8/uGPv9QCIY5q5xS5lPYCY6hGdCrQ08dW0jMRkTDxuVQP2LekvNc1VeSoJkXuUOi Dw= Received: (qmail 94853 invoked by alias); 18 Feb 2019 18:44:48 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 92909 invoked by uid 89); 18 Feb 2019 18:44:33 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS, TIME_LIMIT_EXCEEDED autolearn=unavailable version=3.3.2 spammy=1105 X-HELO: mail-pg1-f171.google.com Received: from mail-pg1-f171.google.com (HELO mail-pg1-f171.google.com) (209.85.215.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:22 +0000 Received: by mail-pg1-f171.google.com with SMTP id h11so6530565pgl.0 for ; Mon, 18 Feb 2019 10:44:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oquRWD86eYuGehLPnvU6zKTMn1VTkHJ/iOKD1zHl5AM=; b=TLHzR6mw49806tnU1R/0rqZqNzXNnIrl0nwaGxs326TWBSXwqMyBw+IHCC7jmO6fzo 0IcB+QC7ei7Mi8JHvW9WdbI8Ll8PsPLTp+wvVHriu+neUUBN6PGZ1kBzFqG7IqvoajC+ 4+bytHBh7iXfWZjog2cq4p0XuiACLUuo+BqdWxlu0Tpc3IJtquNSdkeCxR2CeIexYOHn jeQo2k51+YsQxRM2VtucjnlFiVrvdx/6lCT9/MsBcHjlCMok2mm+f2tSPRFix5RFbwBz bH7I/mkLfoOzKdXpcprs/w5FWHk82COzoqWJD1+IXMKfugKCNbWEkLtUW9h2Ym3llGeb 3dkw== Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id t65sm33107876pfi.117.2019.02.18.10.44.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:13 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 7D1B8C0368; Mon, 18 Feb 2019 10:36:59 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 41/41] i386: Add tests for MMX intrinsic emulations with SSE Date: Mon, 18 Feb 2019 10:36:57 -0800 Message-Id: <20190218183657.16296-42-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Test MMX intrinsics with -msse2 in 32-bit mode and -msse2 -mno-mmx in 64-bit mode. PR target/89021 * gcc.target/i386/mmx-vals.h: New file. * gcc.target/i386/sse2-mmx-2.c: Likewise. * gcc.target/i386/sse2-mmx-3.c: Likewise. * gcc.target/i386/sse2-mmx-4.c: Likewise. * gcc.target/i386/sse2-mmx-5.c: Likewise. * gcc.target/i386/sse2-mmx-6.c: Likewise. * gcc.target/i386/sse2-mmx-7.c: Likewise. * gcc.target/i386/sse2-mmx-8.c: Likewise. * gcc.target/i386/sse2-mmx-9.c: Likewise. * gcc.target/i386/sse2-mmx-10.c: Likewise. * gcc.target/i386/sse2-mmx-11.c: Likewise. * gcc.target/i386/sse2-mmx-12.c: Likewise. * gcc.target/i386/sse2-mmx-13.c: Likewise. * gcc.target/i386/sse2-mmx-14.c: Likewise. * gcc.target/i386/sse2-mmx-15.c: Likewise. * gcc.target/i386/sse2-mmx-16.c: Likewise. * gcc.target/i386/sse2-mmx-17.c: Likewise. * gcc.target/i386/sse2-mmx-18a.c: Likewise. * gcc.target/i386/sse2-mmx-18b.c: Likewise. * gcc.target/i386/sse2-mmx-18c.c: Likewise. * gcc.target/i386/sse2-mmx-19a.c: Likewise. * gcc.target/i386/sse2-mmx-18b.c: Likewise. * gcc.target/i386/sse2-mmx-19c.c: Likewise. * gcc.target/i386/sse2-mmx-19d.c: Likewise. * gcc.target/i386/sse2-mmx-19e.c: Likewise. * gcc.target/i386/sse2-mmx-20.c: Likewise. * gcc.target/i386/sse2-mmx-21.c: Likewise. * gcc.target/i386/sse2-mmx-22.c: Likewise. * gcc.target/i386/sse2-mmx-cvtpi2ps.c: Likewise. * gcc.target/i386/sse2-mmx-cvtps2pi.c: Likewise. * gcc.target/i386/sse2-mmx-cvttps2pi.c: Likewise. * gcc.target/i386/sse2-mmx-maskmovq.c: Likewise. * gcc.target/i386/sse2-mmx-packssdw.c: Likewise. * gcc.target/i386/sse2-mmx-packsswb.c: Likewise. * gcc.target/i386/sse2-mmx-packuswb.c: Likewise. * gcc.target/i386/sse2-mmx-paddb.c: Likewise. * gcc.target/i386/sse2-mmx-paddd.c: Likewise. * gcc.target/i386/sse2-mmx-paddq.c: Likewise. * gcc.target/i386/sse2-mmx-paddsb.c: Likewise. * gcc.target/i386/sse2-mmx-paddsw.c: Likewise. * gcc.target/i386/sse2-mmx-paddusb.c: Likewise. * gcc.target/i386/sse2-mmx-paddusw.c: Likewise. * gcc.target/i386/sse2-mmx-paddw.c: Likewise. * gcc.target/i386/sse2-mmx-pand.c: Likewise. * gcc.target/i386/sse2-mmx-pandn.c: Likewise. * gcc.target/i386/sse2-mmx-pavgb.c: Likewise. * gcc.target/i386/sse2-mmx-pavgw.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpeqb.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpeqd.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpeqw.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpgtb.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpgtd.c: Likewise. * gcc.target/i386/sse2-mmx-pcmpgtw.c: Likewise. * gcc.target/i386/sse2-mmx-pextrw.c: Likewise. * gcc.target/i386/sse2-mmx-pinsrw.c: Likewise. * gcc.target/i386/sse2-mmx-pmaddwd.c: Likewise. * gcc.target/i386/sse2-mmx-pmaxsw.c: Likewise. * gcc.target/i386/sse2-mmx-pmaxub.c: Likewise. * gcc.target/i386/sse2-mmx-pminsw.c: Likewise. * gcc.target/i386/sse2-mmx-pminub.c: Likewise. * gcc.target/i386/sse2-mmx-pmovmskb.c: Likewise. * gcc.target/i386/sse2-mmx-pmulhuw.c: Likewise. * gcc.target/i386/sse2-mmx-pmulhw.c: Likewise. * gcc.target/i386/sse2-mmx-pmullw.c: Likewise. * gcc.target/i386/sse2-mmx-pmuludq.c: Likewise. * gcc.target/i386/sse2-mmx-por.c: Likewise. * gcc.target/i386/sse2-mmx-psadbw.c: Likewise. * gcc.target/i386/sse2-mmx-pshufw.c: Likewise. * gcc.target/i386/sse2-mmx-pslld.c: Likewise. * gcc.target/i386/sse2-mmx-pslldi.c: Likewise. * gcc.target/i386/sse2-mmx-psllq.c: Likewise. * gcc.target/i386/sse2-mmx-psllqi.c: Likewise. * gcc.target/i386/sse2-mmx-psllw.c: Likewise. * gcc.target/i386/sse2-mmx-psllwi.c: Likewise. * gcc.target/i386/sse2-mmx-psrad.c: Likewise. * gcc.target/i386/sse2-mmx-psradi.c: Likewise. * gcc.target/i386/sse2-mmx-psraw.c: Likewise. * gcc.target/i386/sse2-mmx-psrawi.c: Likewise. * gcc.target/i386/sse2-mmx-psrld.c: Likewise. * gcc.target/i386/sse2-mmx-psrldi.c: Likewise. * gcc.target/i386/sse2-mmx-psrlq.c: Likewise. * gcc.target/i386/sse2-mmx-psrlqi.c: Likewise. * gcc.target/i386/sse2-mmx-psrlw.c: Likewise. * gcc.target/i386/sse2-mmx-psrlwi.c: Likewise. * gcc.target/i386/sse2-mmx-psubb.c: Likewise. * gcc.target/i386/sse2-mmx-psubd.c: Likewise. * gcc.target/i386/sse2-mmx-psubq.c: Likewise. * gcc.target/i386/sse2-mmx-psubusb.c: Likewise. * gcc.target/i386/sse2-mmx-psubusw.c: Likewise. * gcc.target/i386/sse2-mmx-psubw.c: Likewise. * gcc.target/i386/sse2-mmx-punpckhbw.c: Likewise. * gcc.target/i386/sse2-mmx-punpckhdq.c: Likewise. * gcc.target/i386/sse2-mmx-punpckhwd.c: Likewise. * gcc.target/i386/sse2-mmx-punpcklbw.c: Likewise. * gcc.target/i386/sse2-mmx-punpckldq.c: Likewise. * gcc.target/i386/sse2-mmx-punpcklwd.c: Likewise. * gcc.target/i386/sse2-mmx-pxor.c: Likewise. --- gcc/testsuite/gcc.target/i386/mmx-vals.h | 77 ++++++ gcc/testsuite/gcc.target/i386/sse2-mmx-10.c | 43 +++ gcc/testsuite/gcc.target/i386/sse2-mmx-11.c | 39 +++ gcc/testsuite/gcc.target/i386/sse2-mmx-12.c | 42 +++ gcc/testsuite/gcc.target/i386/sse2-mmx-13.c | 40 +++ gcc/testsuite/gcc.target/i386/sse2-mmx-14.c | 31 +++ gcc/testsuite/gcc.target/i386/sse2-mmx-15.c | 36 +++ gcc/testsuite/gcc.target/i386/sse2-mmx-16.c | 40 +++ gcc/testsuite/gcc.target/i386/sse2-mmx-17.c | 51 ++++ gcc/testsuite/gcc.target/i386/sse2-mmx-18a.c | 14 + gcc/testsuite/gcc.target/i386/sse2-mmx-18b.c | 7 + gcc/testsuite/gcc.target/i386/sse2-mmx-18c.c | 7 + gcc/testsuite/gcc.target/i386/sse2-mmx-19a.c | 14 + gcc/testsuite/gcc.target/i386/sse2-mmx-19b.c | 7 + gcc/testsuite/gcc.target/i386/sse2-mmx-19c.c | 7 + gcc/testsuite/gcc.target/i386/sse2-mmx-19d.c | 7 + gcc/testsuite/gcc.target/i386/sse2-mmx-19e.c | 7 + gcc/testsuite/gcc.target/i386/sse2-mmx-2.c | 12 + gcc/testsuite/gcc.target/i386/sse2-mmx-20.c | 12 + gcc/testsuite/gcc.target/i386/sse2-mmx-21.c | 13 + gcc/testsuite/gcc.target/i386/sse2-mmx-22.c | 14 + gcc/testsuite/gcc.target/i386/sse2-mmx-3.c | 13 + gcc/testsuite/gcc.target/i386/sse2-mmx-4.c | 4 + gcc/testsuite/gcc.target/i386/sse2-mmx-5.c | 11 + gcc/testsuite/gcc.target/i386/sse2-mmx-6.c | 11 + gcc/testsuite/gcc.target/i386/sse2-mmx-7.c | 13 + gcc/testsuite/gcc.target/i386/sse2-mmx-8.c | 4 + gcc/testsuite/gcc.target/i386/sse2-mmx-9.c | 79 ++++++ .../gcc.target/i386/sse2-mmx-cvtpi2ps.c | 43 +++ .../gcc.target/i386/sse2-mmx-cvtps2pi.c | 36 +++ .../gcc.target/i386/sse2-mmx-cvttps2pi.c | 36 +++ .../gcc.target/i386/sse2-mmx-maskmovq.c | 99 +++++++ .../gcc.target/i386/sse2-mmx-packssdw.c | 52 ++++ .../gcc.target/i386/sse2-mmx-packsswb.c | 52 ++++ .../gcc.target/i386/sse2-mmx-packuswb.c | 52 ++++ .../gcc.target/i386/sse2-mmx-paddb.c | 48 ++++ .../gcc.target/i386/sse2-mmx-paddd.c | 48 ++++ .../gcc.target/i386/sse2-mmx-paddq.c | 43 +++ .../gcc.target/i386/sse2-mmx-paddsb.c | 48 ++++ .../gcc.target/i386/sse2-mmx-paddsw.c | 48 ++++ .../gcc.target/i386/sse2-mmx-paddusb.c | 48 ++++ .../gcc.target/i386/sse2-mmx-paddusw.c | 48 ++++ .../gcc.target/i386/sse2-mmx-paddw.c | 48 ++++ gcc/testsuite/gcc.target/i386/sse2-mmx-pand.c | 44 ++++ .../gcc.target/i386/sse2-mmx-pandn.c | 44 ++++ .../gcc.target/i386/sse2-mmx-pavgb.c | 52 ++++ .../gcc.target/i386/sse2-mmx-pavgw.c | 52 ++++ .../gcc.target/i386/sse2-mmx-pcmpeqb.c | 48 ++++ .../gcc.target/i386/sse2-mmx-pcmpeqd.c | 48 ++++ .../gcc.target/i386/sse2-mmx-pcmpeqw.c | 48 ++++ .../gcc.target/i386/sse2-mmx-pcmpgtb.c | 48 ++++ .../gcc.target/i386/sse2-mmx-pcmpgtd.c | 48 ++++ .../gcc.target/i386/sse2-mmx-pcmpgtw.c | 48 ++++ .../gcc.target/i386/sse2-mmx-pextrw.c | 59 +++++ .../gcc.target/i386/sse2-mmx-pinsrw.c | 61 +++++ .../gcc.target/i386/sse2-mmx-pmaddwd.c | 47 ++++ .../gcc.target/i386/sse2-mmx-pmaxsw.c | 48 ++++ .../gcc.target/i386/sse2-mmx-pmaxub.c | 48 ++++ .../gcc.target/i386/sse2-mmx-pminsw.c | 48 ++++ .../gcc.target/i386/sse2-mmx-pminub.c | 48 ++++ .../gcc.target/i386/sse2-mmx-pmovmskb.c | 46 ++++ .../gcc.target/i386/sse2-mmx-pmulhuw.c | 51 ++++ .../gcc.target/i386/sse2-mmx-pmulhw.c | 53 ++++ .../gcc.target/i386/sse2-mmx-pmullw.c | 52 ++++ .../gcc.target/i386/sse2-mmx-pmuludq.c | 47 ++++ gcc/testsuite/gcc.target/i386/sse2-mmx-por.c | 44 ++++ .../gcc.target/i386/sse2-mmx-psadbw.c | 58 ++++ .../gcc.target/i386/sse2-mmx-pshufw.c | 248 ++++++++++++++++++ .../gcc.target/i386/sse2-mmx-pslld.c | 52 ++++ .../gcc.target/i386/sse2-mmx-pslldi.c | 153 +++++++++++ .../gcc.target/i386/sse2-mmx-psllq.c | 47 ++++ .../gcc.target/i386/sse2-mmx-psllqi.c | 245 +++++++++++++++++ .../gcc.target/i386/sse2-mmx-psllw.c | 52 ++++ .../gcc.target/i386/sse2-mmx-psllwi.c | 105 ++++++++ .../gcc.target/i386/sse2-mmx-psrad.c | 52 ++++ .../gcc.target/i386/sse2-mmx-psradi.c | 153 +++++++++++ .../gcc.target/i386/sse2-mmx-psraw.c | 52 ++++ .../gcc.target/i386/sse2-mmx-psrawi.c | 105 ++++++++ .../gcc.target/i386/sse2-mmx-psrld.c | 52 ++++ .../gcc.target/i386/sse2-mmx-psrldi.c | 153 +++++++++++ .../gcc.target/i386/sse2-mmx-psrlq.c | 47 ++++ .../gcc.target/i386/sse2-mmx-psrlqi.c | 245 +++++++++++++++++ .../gcc.target/i386/sse2-mmx-psrlw.c | 52 ++++ .../gcc.target/i386/sse2-mmx-psrlwi.c | 105 ++++++++ .../gcc.target/i386/sse2-mmx-psubb.c | 48 ++++ .../gcc.target/i386/sse2-mmx-psubd.c | 48 ++++ .../gcc.target/i386/sse2-mmx-psubq.c | 43 +++ .../gcc.target/i386/sse2-mmx-psubusb.c | 48 ++++ .../gcc.target/i386/sse2-mmx-psubusw.c | 48 ++++ .../gcc.target/i386/sse2-mmx-psubw.c | 48 ++++ .../gcc.target/i386/sse2-mmx-punpckhbw.c | 53 ++++ .../gcc.target/i386/sse2-mmx-punpckhdq.c | 47 ++++ .../gcc.target/i386/sse2-mmx-punpckhwd.c | 49 ++++ .../gcc.target/i386/sse2-mmx-punpcklbw.c | 53 ++++ .../gcc.target/i386/sse2-mmx-punpckldq.c | 47 ++++ .../gcc.target/i386/sse2-mmx-punpcklwd.c | 49 ++++ gcc/testsuite/gcc.target/i386/sse2-mmx-pxor.c | 44 ++++ gcc/testsuite/gcc.target/i386/sse2-mmx.c | 1 - 98 files changed, 5137 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/mmx-vals.h create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-10.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-11.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-12.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-13.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-14.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-15.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-16.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-17.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-18a.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-18b.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-18c.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-19a.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-19b.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-19c.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-19d.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-19e.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-2.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-20.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-21.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-22.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-3.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-4.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-5.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-6.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-7.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-8.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-9.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-cvtpi2ps.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-cvtps2pi.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-cvttps2pi.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-maskmovq.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-packssdw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-packsswb.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-packuswb.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-paddb.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-paddd.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-paddq.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-paddsb.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-paddsw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-paddusb.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-paddusw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-paddw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pand.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pandn.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pavgb.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pavgw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqb.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqd.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtb.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtd.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pextrw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pinsrw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pmaddwd.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pmaxsw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pmaxub.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pminsw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pminub.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pmovmskb.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pmulhuw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pmulhw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pmullw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pmuludq.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-por.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psadbw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pshufw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pslld.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pslldi.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psllq.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psllqi.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psllw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psllwi.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psrad.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psradi.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psraw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psrawi.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psrld.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psrldi.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psrlq.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psrlqi.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psrlw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psrlwi.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psubb.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psubd.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psubq.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psubusb.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psubusw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-psubw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhbw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhdq.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhwd.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-punpcklbw.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-punpckldq.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-punpcklwd.c create mode 100644 gcc/testsuite/gcc.target/i386/sse2-mmx-pxor.c diff --git a/gcc/testsuite/gcc.target/i386/mmx-vals.h b/gcc/testsuite/gcc.target/i386/mmx-vals.h new file mode 100644 index 00000000000..62d0c1cb514 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mmx-vals.h @@ -0,0 +1,77 @@ +/* Routine to check correctness of the results */ + +__attribute__((unused)) +static int +saturate_b (int i) +{ + if (i > 127) + i = 127; + else if (i < -128) + i = -128; + return i; +} + +__attribute__((unused)) +static int +saturate_w (int i) +{ + if (i > 32767) + i = 32767; + else if (i < -32768) + i = -32768; + return i; +} + +__attribute__((unused)) +static int +saturate_ub (int i) +{ + if (i > 255) + i = 255; + else if (i < 0) + i = 0; + return i; +} + +__attribute__((unused)) +static int +saturate_uw (int i) +{ + if (i > 65535) + i = 65535; + else if (i < 0) + i = 0; + return i; +} + +static long long MMXops[] = +{ + 0x3467512347612976LL, 0x000000000000000eLL, + 0x3467512347612976LL, 0x0000000000000014LL, + 0x3467512347612976LL, 0x000000000000003cLL, + 0x0000000000000000LL, 0xFFFFFFFFFFFFFFFFLL, + 0xFFFFFFFFFFFFFFFFLL, 0x0000000000000000LL, + 0x0000000000000001LL, 0x1000000000000000LL, + 0x1000000000000000LL, 0x0000000000000001LL, + 0xFF00FF00FF00FF00LL, 0x00FF00FF00FF00FFLL, + 0xFFFFFFFFFFFFFFFFLL, 0x0101010101010101LL, + 0x0101010101010101LL, 0xFFFFFFFFFFFFFFFFLL, + 0x0123456789ABCDEFLL, 0x0123456789ABCDEFLL, + 0x3467512347612976LL, 0x1839876340879234LL, + 0x0000000000000000LL, 0x0000000000000000LL, + 0xFFFFFFFFFFFFFFFFLL, 0xFFFFFFFFFFFFFFFFLL, + 0x7F7F7F7F7F7F7F7FLL, 0x7F7F7F7F7F7F7F7FLL, + 0x7F7F7F7F7F7F7F7FLL, 0x0101010101010101LL, + 0x7F7F7F7F7F7F7F7FLL, 0x4782082349761237LL, + 0x0000000000000000LL, 0x7F7F7F7F7F7F7F7FLL, + 0x8080808080808080LL, 0x8080808080808080LL, + 0x0101010101010101LL, 0x8080808080808080LL, + 0x8080808080808080LL, 0x0000000000000000LL, + 0x2372347120982458LL, 0x8080808080808080LL, + 0xFFFFFFFFFFFFFFFFLL, 0x8080808080808080LL, + 0x7F7F7F7F7F7F7F7FLL, 0xFFFFFFFFFFFFFFFFLL, + 0x8080808080808080LL, 0x7F7F7F7F7F7F7F7FLL, + 0xFFFFFFFFFFFFFFFFLL, 0x7F7F7F7F7F7F7F7FLL +}; + +#define MMX_num_ops (sizeof (MMXops) / sizeof (MMXops[0])) diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-10.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-10.c new file mode 100644 index 00000000000..4da7ed3a3e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-10.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_from_int (long long *ll1, long long *r) +{ + int i1 = *(int *) ll1; + *(__m64 *) r = _m_from_int (i1); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *ll1, long long *r) +{ + int *res = (int *) r; + res[0] = *(int *) ll1; + res[1] = 0; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + test_from_int (&MMXops[i], &r); + compute_correct_result (&MMXops[i], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-11.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-11.c new file mode 100644 index 00000000000..6737ec5f2d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-11.c @@ -0,0 +1,39 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2 -mno-mmx" } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_from_long_long (long long *ll1, long long *r) +{ + *(__m64 *) r = _mm_cvtsi64_m64 (*ll1); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *ll1, long long *r) +{ + *r = *ll1; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + test_from_long_long (&MMXops[i], &r); + compute_correct_result (&MMXops[i], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-12.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-12.c new file mode 100644 index 00000000000..b626daa0aab --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-12.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_to_int (long long *ll1, long long *r) +{ + __m64 m = *(__m64 *) ll1; + *(int *) r = _m_to_int (m); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *ll1, long long *r) +{ + int *i1 = (int *) ll1; + *(int *) r = *i1; +} + +static void +sse2_test (void) +{ + int i; + long long r = 0, ck = 0; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + test_to_int (&MMXops[i], &r); + compute_correct_result (&MMXops[i], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-13.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-13.c new file mode 100644 index 00000000000..fd1eed66daa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-13.c @@ -0,0 +1,40 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2 -mno-mmx" } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_to_long_long (long long *ll1, long long *r) +{ + __m64 m = *(__m64 *) ll1; + *r = _mm_cvtm64_si64 (m); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *ll1, long long *r) +{ + *r = *ll1; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + test_to_long_long (&MMXops[i], &r); + compute_correct_result (&MMXops[i], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-14.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-14.c new file mode 100644 index 00000000000..bc21ba711da --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-14.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" + +__attribute__((noinline, noclone)) +static void +test_setzero (long long *r) +{ + *(__m64 *) r = _mm_setzero_si64 (); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *r) +{ + *r = 0x0LL; +} + +static void +sse2_test (void) +{ + long long r, ck; + + /* Run the MMX tests */ + test_setzero (&r); + compute_correct_result (&ck); + if (ck != r) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-15.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-15.c new file mode 100644 index 00000000000..ab8451b591d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-15.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" + +__attribute__((noinline, noclone)) +static void +test_set (int x, int y, long long *r) +{ + *(__m64 *) r = _mm_set_pi32 (x, y); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int x, int y, long long *res_p) +{ + int *res = (int *) res_p; + res[0] = y; + res[1] = x; +} + +static void +sse2_test (void) +{ + int x, y; + long long r, ck; + + /* Run the MMX tests */ + x = 0x0badbeef; + y = 0x0badfeed; + test_set (x, y, &r); + compute_correct_result (x, y, &ck); + if (ck != r) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-16.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-16.c new file mode 100644 index 00000000000..b348b9f1c64 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-16.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" + +__attribute__((noinline, noclone)) +static void +test_set (int i0, int i1, int i2, int i3, long long *r) +{ + *(__m64 *) r = _mm_set_pi16 (i0, i1, i2, i3); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (int i0, int i1, int i2, int i3, long long *res_p) +{ + short *res = (short *) res_p; + res[0] = i3; + res[1] = i2; + res[2] = i1; + res[3] = i0; +} + +static void +sse2_test (void) +{ + short i0, i1, i2, i3; + long long r, ck; + + /* Run the MMX tests */ + i0 = 0x0bad; + i1 = 0xbeef; + i2 = 0x0bad; + i3 = 0xfeed; + test_set (i0, i1, i2, i3, &r); + compute_correct_result (i0, i1, i2, i3, &ck); + if (ck != r) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-17.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-17.c new file mode 100644 index 00000000000..756cbeb33da --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-17.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" + +__attribute__((noinline, noclone)) +static void +test_set (char i0, char i1, char i2, char i3, + char i4, char i5, char i6, char i7, long long *r) +{ + *(__m64 *) r = _mm_set_pi8 (i0, i1, i2, i3, i4, i5, i6, i7); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (char i0, char i1, char i2, char i3, + char i4, char i5, char i6, char i7, + long long *res_p) +{ + char *res = (char *) res_p; + res[0] = i7; + res[1] = i6; + res[2] = i5; + res[3] = i4; + res[4] = i3; + res[5] = i2; + res[6] = i1; + res[7] = i0; +} + +static void +sse2_test (void) +{ + char i0, i1, i2, i3, i4, i5, i6, i7; + long long r, ck; + + /* Run the MMX tests */ + i0 = 0x12; + i1 = 0x34; + i2 = 0x56; + i3 = 0x78; + i4 = 0x90; + i5 = 0xab; + i6 = 0xcd; + i7 = 0xef; + test_set (i0, i1, i2, i3, i4, i5, i6, i7, &r); + compute_correct_result (i0, i1, i2, i3, i4, i5, i6, i7, &ck); + if (ck != r) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-18a.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-18a.c new file mode 100644 index 00000000000..3505a5c0cf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-18a.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx -mno-avx512vl" } */ +/* { dg-final { scan-assembler-times "pshufd" 1 } } */ +/* { dg-final { scan-assembler-times "movd" 1 } } */ +/* { dg-final { scan-assembler-not "movl" } } */ + +#include + +__m64 +foo (int i) +{ + __v2si x = { i, i }; + return (__m64) x; +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-18b.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-18b.c new file mode 100644 index 00000000000..9b267b17346 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-18b.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mno-mmx -mavx512bw -mavx512vl" } */ +/* { dg-final { scan-assembler-times "pbroadcastd" 1 } } */ +/* { dg-final { scan-assembler-not "movd" } } */ +/* { dg-final { scan-assembler-not "movl" } } */ + +#include "sse2-mmx-18a.c" diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-18c.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-18c.c new file mode 100644 index 00000000000..394f05b6b49 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-18c.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mno-mmx -mavx512bw -mno-avx512vl" } */ +/* { dg-final { scan-assembler-times "pshufd" 1 } } */ +/* { dg-final { scan-assembler-times "movd" 1 } } */ +/* { dg-final { scan-assembler-not "movl" } } */ + +#include "sse2-mmx-18a.c" diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-19a.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-19a.c new file mode 100644 index 00000000000..9715ace241f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-19a.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx -mno-avx -mtune=intel" } */ +/* { dg-final { scan-assembler-times "pshuflw" 1 } } */ +/* { dg-final { scan-assembler-times "movd" 1 } } */ +/* { dg-final { scan-assembler-not "movl" } } */ + +#include + +__m64 +foo (short i) +{ + __v4hi x = { i, i, i, i }; + return (__m64) x; +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-19b.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-19b.c new file mode 100644 index 00000000000..a6d42313336 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-19b.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mno-mmx -mavx512bw -mavx512vl" } */ +/* { dg-final { scan-assembler-times "pbroadcastw" 1 } } */ +/* { dg-final { scan-assembler-not "movd" } } */ +/* { dg-final { scan-assembler-not "movl" } } */ + +#include "sse2-mmx-19a.c" diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-19c.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-19c.c new file mode 100644 index 00000000000..b02dc8c2ffd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-19c.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mno-mmx -mavx -mno-avx2 -mtune=intel" } */ +/* { dg-final { scan-assembler-times "pshuflw" 1 } } */ +/* { dg-final { scan-assembler-times "movd" 1 } } */ +/* { dg-final { scan-assembler-not "movl" } } */ + +#include "sse2-mmx-19a.c" diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-19d.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-19d.c new file mode 100644 index 00000000000..54691883c9c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-19d.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mno-mmx -mavx512bw -mno-avx512vl -mtune=intel" } */ +/* { dg-final { scan-assembler-times "pbroadcastw" 1 } } */ +/* { dg-final { scan-assembler-times "movd" 1 } } */ +/* { dg-final { scan-assembler-not "movl" } } */ + +#include "sse2-mmx-19a.c" diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-19e.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-19e.c new file mode 100644 index 00000000000..8be973cc4fc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-19e.c @@ -0,0 +1,7 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mno-mmx -mavx2 -mno-avx512f -mtune=intel" } */ +/* { dg-final { scan-assembler-times "pbroadcastw" 1 } } */ +/* { dg-final { scan-assembler-times "movd" 1 } } */ +/* { dg-final { scan-assembler-not "movl" } } */ + +#include "sse2-mmx-19a.c" diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-2.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-2.c new file mode 100644 index 00000000000..e4cee2da83e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx" } */ +/* { dg-final { scan-assembler-not "%xmm" } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ + +#include + +float +foo (__m64 x) +{ + return ((__v2sf) x)[0]; +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-20.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-20.c new file mode 100644 index 00000000000..173fa154d40 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-20.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx" } */ +/* { dg-final { scan-assembler-times "movd" 1 } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ + +#include + +int +foo (__m64 x) +{ + return ((__v2si) x)[0]; +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-21.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-21.c new file mode 100644 index 00000000000..8f5341e2de6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-21.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx" } */ +/* { dg-final { scan-assembler-times "pshufd" 1 } } */ +/* { dg-final { scan-assembler-times "movd" 1 } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ + +#include + +int +foo (__m64 x) +{ + return ((__v2si) x)[1]; +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-22.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-22.c new file mode 100644 index 00000000000..94fa5874365 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-22.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include + +void +foo (void) +{ + _mm_empty (); +} + +/* { dg-final { scan-assembler-times "emms" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-not "emms" { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-3.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-3.c new file mode 100644 index 00000000000..77f518b6c5f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx" } */ +/* { dg-final { scan-assembler "cvtdq2ps" } } */ +/* { dg-final { scan-assembler-not "cvtpi2ps" } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ + +#include + +__m128 +foo (__m128 i1, __m64 i2) +{ + return _mm_cvtpi32_ps (i1, i2); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-4.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-4.c new file mode 100644 index 00000000000..d923724fc1c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-4.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx" } */ + +#include "mmx-4.c" diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-5.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-5.c new file mode 100644 index 00000000000..1953dc89bb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-5.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx" } */ +/* { dg-final { scan-assembler-not "%mm" } } */ + +#include + +int +foo (__m64 i) +{ + return _m_pextrw (i, 2); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-6.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-6.c new file mode 100644 index 00000000000..f73444f493b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-6.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx" } */ +/* { dg-final { scan-assembler-not "%mm" } } */ + +#include + +__m64 +foo (__m64 i, int w) +{ + return _m_pinsrw (i, w, 2); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-7.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-7.c new file mode 100644 index 00000000000..6ea491d2715 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-7.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx" } */ +/* { dg-final { scan-assembler "movnti" } } */ +/* { dg-final { scan-assembler-not "movntq" } } */ +/* { dg-final { scan-assembler-not "%mm" } } */ + +#include + +void +foo (__m64 *p, __m64 i) +{ + _mm_stream_pi (p, i); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-8.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-8.c new file mode 100644 index 00000000000..342c2fa4f25 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-8.c @@ -0,0 +1,4 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx" } */ + +#include "mmx-8.c" diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-9.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-9.c new file mode 100644 index 00000000000..f0bf7256c0e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-9.c @@ -0,0 +1,79 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mno-mmx" } */ +/* { dg-require-effective-target sse2 } */ + +#include "sse2-check.h" + +#include + +#define FLOAT_X 2.3456 +#define FLOAT_Y -4.5987 + +static float expected_x = FLOAT_X; +static float expected_y = FLOAT_Y; +static __v2sf expected1 = { FLOAT_X, FLOAT_Y }; +static __v2sf expected2 = { FLOAT_X, 0 }; +static __v2sf expected3 = { FLOAT_X, FLOAT_X }; + +float +__attribute__((noinline, noclone)) +foo1 (__m64 x) +{ + return ((__v2sf) x)[0]; +} + +float +__attribute__((noinline, noclone)) +foo2 (__m64 x) +{ + return ((__v2sf) x)[1]; +} + +__m64 +__attribute__((noinline, noclone)) +foo3 (float x) +{ + return __extension__ (__m64) (__v2sf) { x, 0 }; +} + +__m64 +__attribute__((noinline, noclone)) +foo4 (float x) +{ + return __extension__ (__m64) (__v2sf) { x, x }; +} + +__m64 +__attribute__((noinline, noclone)) +foo5 (float x, float y) +{ + return __extension__ (__m64) (__v2sf) { x, y }; +} + +void +__attribute__((noinline)) +sse2_test (void) +{ + __m64 res; + float x; + + x = foo1 ((__m64) expected1); + if (x != expected_x) + abort (); + + x = foo2 ((__m64) expected1); + if (x != expected_y) + abort (); + + res = foo3 (FLOAT_X); + if (memcmp (&res, &expected2, sizeof (res))) + abort (); + + res = foo4 (FLOAT_X); + if (memcmp (&res, &expected3, sizeof (res))) + abort (); + + res = foo5 (FLOAT_X, FLOAT_Y); + if (memcmp (&res, &expected1, sizeof (res))) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-cvtpi2ps.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-cvtpi2ps.c new file mode 100644 index 00000000000..4ab38d6f015 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-cvtpi2ps.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include +#include "sse2-check.h" + +__attribute__((noinline, noclone)) +static void +test_cvtpi32_ps (__m128 *i1, __m64 *i2, __m128 *r) +{ + *(__m128 *) r = _mm_cvtpi32_ps (*i1, *i2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (__m128 *dst_p, __m64 *src_p, __m128 *res_p) +{ + int *src = (int *) src_p; + float *res = (float *) res_p; + *res_p = *dst_p; + int i; + __m128 r; + for (i = 0; i < 2; i++) + { + r = _mm_cvt_si2ss (*dst_p, src[i]); + res[i] = ((__v4sf) r)[0]; + } +} + +static void +sse2_test (void) +{ + __m128 r, ck; + __v4sf x = { 1.99f, -3.9f, -4.9f, 3.8f }; + __v2si y = { 30, -39 }; + + /* Run the MMX tests */ + test_cvtpi32_ps ((__m128 *) &x, (__m64 *) &y, &r); + compute_correct_result ((__m128 *) &x, (__m64 *) &y, &ck); + if (memcmp (&ck, &r, sizeof (r))) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-cvtps2pi.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-cvtps2pi.c new file mode 100644 index 00000000000..6084c9ff3d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-cvtps2pi.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" + +__attribute__((noinline, noclone)) +static void +test_cvtps_pi32 (__m128 *src_p, long long *r) +{ + *(__m64 *) r = _mm_cvtps_pi32 (*src_p); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (__m128 *src_p, long long *res_p) +{ + __v4sf *src = (__v4sf *) src_p; + int *res = (int *) res_p; + int i; + for (i = 0; i < 2; i++) + res[i] = _mm_cvt_ss2si (_mm_set_ss ((*src)[i])); +} + +static void +sse2_test (void) +{ + long long r, ck; + __v4sf x = { 1.99f, -3.9f, -4.9f, 3.8f }; + + /* Run the MMX tests */ + test_cvtps_pi32 ((__m128 *) &x, &r); + compute_correct_result ((__m128 *) &x, &ck); + if (ck != r) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-cvttps2pi.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-cvttps2pi.c new file mode 100644 index 00000000000..6f12b2f064f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-cvttps2pi.c @@ -0,0 +1,36 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" + +__attribute__((noinline, noclone)) +static void +test_cvttps_pi32 (__m128 *src_p, long long *r) +{ + *(__m64 *) r = _mm_cvttps_pi32 (*src_p); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (__m128 *src_p, long long *res_p) +{ + __v4sf *src = (__v4sf *) src_p; + int *res = (int *) res_p; + int i; + for (i = 0; i < 2; i++) + res[i] = _mm_cvtt_ss2si (_mm_set_ss ((*src)[i])); +} + +static void +sse2_test (void) +{ + long long r, ck; + __v4sf x = { 1.99f, -3.9f, -4.9f, 3.8f }; + + /* Run the MMX tests */ + test_cvttps_pi32 ((__m128 *) &x, &r); + compute_correct_result ((__m128 *) &x, &ck); + if (ck != r) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-maskmovq.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-maskmovq.c new file mode 100644 index 00000000000..29fab1914f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-maskmovq.c @@ -0,0 +1,99 @@ +/* { dg-do run { target { *-*-linux* } } } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include +#include +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_maskmovq (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + _m_maskmovq (t1, t2, (char *) r); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + char *dst = (char *) dst_p; + char *src = (char *) src_p; + char *res = (char *) res_p; + int i; + for (i = 0; i < 8; i++) + if ((src[i] & 0x80) != 0) + res[i] = dst[i]; +} + +static void +do_maskmovq_test (long long *r) +{ + int i; + long long ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + r[0] = -1LL; + ck = -1LL; + test_maskmovq (&MMXops[i], &MMXops[i], r); + compute_correct_result (&MMXops[i], &MMXops[i], &ck); + if (*r != ck) + fail++; + } + + if (fail != 0) + abort (); +} + +static void +sse2_test (void) +{ + char *buf; + long long *r; + size_t page_size = sysconf(_SC_PAGESIZE); + + buf = mmap (0, 3 * page_size, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANON, -1, 0); + if (buf == MAP_FAILED) + { + perror ("mmap"); + abort (); + } + + if (mprotect (buf, page_size, PROT_NONE)) + { + perror ("mprotect"); + abort (); + } + + if (mprotect (buf + 2 * page_size, page_size, PROT_NONE)) + { + perror ("mprotect"); + abort (); + } + + r = (long long *) (buf + page_size); + do_maskmovq_test (r); + + r = (long long *) (buf + page_size + 3); + do_maskmovq_test (r); + + r = (long long *) (buf + page_size + 11); + do_maskmovq_test (r); + + r = (long long *) (buf + 2 * page_size - 16); + do_maskmovq_test (r); + + r = (long long *) (buf + 2 * page_size - 16 + 3); + do_maskmovq_test (r); + + r = (long long *) (buf + 2 * page_size - 16 + 8); + do_maskmovq_test (r); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-packssdw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-packssdw.c new file mode 100644 index 00000000000..ef5fded4568 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-packssdw.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_packssdw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_packssdw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + int *dst = (int *) dst_p; + int *src = (int *) src_p; + short *res = (short *) res_p; + int i; + + for (i = 0; i < 2; i++) + { + res[i] = saturate_w (dst[i]); + res[i + 2] = saturate_w (src[i]); + } +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_packssdw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-packsswb.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-packsswb.c new file mode 100644 index 00000000000..bcc34040b2b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-packsswb.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_packsswb (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_packsswb (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + char *res = (char *) res_p; + int i; + + for (i = 0; i < 4; i++) + { + res[i] = saturate_b (dst[i]); + res[i + 4] = saturate_b (src[i]); + } +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_packsswb (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-packuswb.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-packuswb.c new file mode 100644 index 00000000000..ac2da068d64 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-packuswb.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_packuswb (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_packuswb (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + unsigned char *res = (unsigned char *) res_p; + int i; + + for (i = 0; i < 4; i++) + { + res[i] = saturate_ub (dst[i]); + res[i + 4] = saturate_ub (src[i]); + } +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_packuswb (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-paddb.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddb.c new file mode 100644 index 00000000000..b12534908ec --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddb.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_paddb (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_paddb (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + char *dst = (char *) dst_p; + char *src = (char *) src_p; + char *res = (char *) res_p; + int i; + for (i = 0; i < 8; i++) + res[i] = dst[i] + src[i]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_paddb (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-paddd.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddd.c new file mode 100644 index 00000000000..d71b21713a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddd.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_paddd (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_paddd (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + int *dst = (int *) dst_p; + int *src = (int *) src_p; + int *res = (int *) res_p; + int i; + for (i = 0; i < 2; i++) + res[i] = dst[i] + src[i]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_paddd (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-paddq.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddq.c new file mode 100644 index 00000000000..b015393cf03 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddq.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_paddq (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _mm_add_si64 (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + res_p[0] = dst_p[0] + src_p[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_paddq (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-paddsb.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddsb.c new file mode 100644 index 00000000000..f8236beef32 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddsb.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_paddsb (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_paddsb (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + char *dst = (char *) dst_p; + char *src = (char *) src_p; + char *res = (char *) res_p; + int i; + for (i = 0; i < 8; i++) + res[i] = saturate_b (dst[i] + src[i]); +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_paddsb (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-paddsw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddsw.c new file mode 100644 index 00000000000..cc52fe65e66 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddsw.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_paddsw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_paddsw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + short *res = (short *) res_p; + int i; + for (i = 0; i < 4; i++) + res[i] = saturate_w (dst[i] + src[i]); +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_paddsw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-paddusb.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddusb.c new file mode 100644 index 00000000000..c802bcf4d10 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddusb.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_paddusb (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_paddusb (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned char *dst = (unsigned char *) dst_p; + unsigned char *src = (unsigned char *) src_p; + unsigned char *res = (unsigned char *) res_p; + int i; + for (i = 0; i < 8; i++) + res[i] = saturate_ub (dst[i] + src[i]); +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_paddusb (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-paddusw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddusw.c new file mode 100644 index 00000000000..c0f3c8601fb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddusw.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_paddusw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_paddusw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned short *dst = (unsigned short *) dst_p; + unsigned short *src = (unsigned short *) src_p; + unsigned short *res = (unsigned short *) res_p; + int i; + for (i = 0; i < 4; i++) + res[i] = saturate_uw (dst[i] + src[i]); +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_paddusw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-paddw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddw.c new file mode 100644 index 00000000000..6921ae8da3c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-paddw.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_paddw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_paddw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + short *res = (short *) res_p; + int i; + for (i = 0; i < 4; i++) + res[i] = dst[i] + src[i]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_paddw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pand.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pand.c new file mode 100644 index 00000000000..0047a7e4d93 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pand.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pand (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pand (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (unsigned long long *dst, + unsigned long long *src, + unsigned long long *res) +{ + res[0] = dst[0] & src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pand (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pandn.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pandn.c new file mode 100644 index 00000000000..a0cce55a4ea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pandn.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pandn (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pandn (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (unsigned long long *dst, + unsigned long long *src, + unsigned long long *res) +{ + res[0] = ~dst[0] & src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pandn (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pavgb.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pavgb.c new file mode 100644 index 00000000000..fbb586e1d21 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pavgb.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pavgb (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pavgb (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned char *dst = (unsigned char *) dst_p; + unsigned char *src = (unsigned char *) src_p; + unsigned char *res = (unsigned char *) res_p; + int i; + unsigned int tmp; + for (i = 0; i < 8; i++) + { + tmp = dst[i] + src[i] + 1; + res[i] = tmp >> 1; + } +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pavgb (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pavgw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pavgw.c new file mode 100644 index 00000000000..81cdc213541 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pavgw.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pavgw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pavgw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned short *dst = (unsigned short *) dst_p; + unsigned short *src = (unsigned short *) src_p; + unsigned short *res = (unsigned short *) res_p; + int i; + unsigned int tmp; + for (i = 0; i < 4; i++) + { + tmp = dst[i] + src[i] + 1; + res[i] = tmp >> 1; + } +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pavgw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqb.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqb.c new file mode 100644 index 00000000000..d355ba0a757 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqb.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pcmpeqb (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pcmpeqb (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + char *dst = (char *) dst_p; + char *src = (char *) src_p; + char *res = (char *) res_p; + int i; + for (i = 0; i < 8; i++) + res[i] = dst[i] == src[i] ? -1 : 0; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pcmpeqb (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqd.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqd.c new file mode 100644 index 00000000000..bd896249212 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqd.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pcmpeqd (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pcmpeqd (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + int *dst = (int *) dst_p; + int *src = (int *) src_p; + int *res = (int *) res_p; + int i; + for (i = 0; i < 2; i++) + res[i] = dst[i] == src[i] ? -1 : 0; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pcmpeqd (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqw.c new file mode 100644 index 00000000000..ae15437f1cb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpeqw.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pcmpeqw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pcmpeqw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + short *res = (short *) res_p; + int i; + for (i = 0; i < 4; i++) + res[i] = dst[i] == src[i] ? -1 : 0; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pcmpeqw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtb.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtb.c new file mode 100644 index 00000000000..f175c698803 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtb.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pcmpgtb (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pcmpgtb (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + char *dst = (char *) dst_p; + char *src = (char *) src_p; + char *res = (char *) res_p; + int i; + for (i = 0; i < 8; i++) + res[i] = dst[i] > src[i] ? -1 : 0; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pcmpgtb (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtd.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtd.c new file mode 100644 index 00000000000..451afb54c3d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtd.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pcmpgtd (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pcmpgtd (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + int *dst = (int *) dst_p; + int *src = (int *) src_p; + int *res = (int *) res_p; + int i; + for (i = 0; i < 2; i++) + res[i] = dst[i] > src[i] ? -1 : 0; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pcmpgtd (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtw.c new file mode 100644 index 00000000000..f3ebe8eedb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pcmpgtw.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pcmpgtw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pcmpgtw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + short *res = (short *) res_p; + int i; + for (i = 0; i < 4; i++) + res[i] = dst[i] > src[i] ? -1 : 0; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pcmpgtw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pextrw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pextrw.c new file mode 100644 index 00000000000..bb48740a7ca --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pextrw.c @@ -0,0 +1,59 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include +#include "sse2-check.h" + +__attribute__((noinline, noclone)) +static void +test_pextrw (__m64 *i, unsigned int imm, int *r) +{ + switch (imm) + { + case 0: + *r = _m_pextrw (*i, 0); + break; + case 1: + *r = _m_pextrw (*i, 1); + break; + case 2: + *r = _m_pextrw (*i, 2); + break; + case 3: + *r = _m_pextrw (*i, 3); + break; + default: + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (__m64 *src_p, unsigned int imm, int *res_p) +{ + short *src = (short *) src_p; + if (imm < 4) + *res_p = src[imm]; +} + +static void +sse2_test (void) +{ + int r, ck; + int i; + int failed = 0; + __v4hi y = { 3320, -3339, 48, 4392 }; + + /* Run the MMX tests */ + for (i = 0; i < 4; i++) + { + test_pextrw ((__m64 *) &y, i, &r); + compute_correct_result ((__m64 *) &y, i, &ck); + if (r != ck) + failed++; + } + + if (failed) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pinsrw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pinsrw.c new file mode 100644 index 00000000000..c25ddd96daa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pinsrw.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include +#include "sse2-check.h" + +__attribute__((noinline, noclone)) +static void +test_pinsrw (__m64 *i, int val, unsigned int imm, int *r) +{ + switch (imm) + { + case 0: + *(__m64 *) r = _m_pinsrw (*i, val, 0); + break; + case 1: + *(__m64 *) r = _m_pinsrw (*i, val, 1); + break; + case 2: + *(__m64 *) r = _m_pinsrw (*i, val, 2); + break; + case 3: + *(__m64 *) r = _m_pinsrw (*i, val, 3); + break; + default: + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (__m64 *src_p, int val, unsigned int imm, + int *res_p) +{ + short *res = (short *) res_p; + *(__m64 *) res_p = *src_p; + if (imm < 4) + res[imm] = val; +} + +static void +sse2_test (void) +{ + int r, ck; + int i; + int failed = 0; + __v4hi y = { 3320, -3339, 48, 4392 }; + + /* Run the MMX tests */ + for (i = 0; i < 4; i++) + { + test_pinsrw ((__m64 *) &y, 0x1234, i, &r); + compute_correct_result ((__m64 *) &y, 0x1234, i, &ck); + if (r != ck) + failed++; + } + + if (failed) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pmaddwd.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmaddwd.c new file mode 100644 index 00000000000..1eace62088a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmaddwd.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pmaddwd (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pmaddwd (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + int *res = (int *) res_p; + res[0] = dst[0] * src[0] + dst[1] * src[1]; + res[1] = dst[2] * src[2] + dst[3] * src[3]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pmaddwd (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pmaxsw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmaxsw.c new file mode 100644 index 00000000000..ec3b68f09d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmaxsw.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pmaxsw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pmaxsw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + short *res = (short *) res_p; + int i; + for (i = 0; i < 4; i++) + res[i] = dst[i] > src[i] ? dst[i] : src[i]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pmaxsw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pmaxub.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmaxub.c new file mode 100644 index 00000000000..085d6a0eaf5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmaxub.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pmaxub (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pmaxub (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned char *dst = (unsigned char *) dst_p; + unsigned char *src = (unsigned char *) src_p; + unsigned char *res = (unsigned char *) res_p; + int i; + for (i = 0; i < 8; i++) + res[i] = dst[i] > src[i] ? dst[i] : src[i]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pmaxub (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pminsw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pminsw.c new file mode 100644 index 00000000000..f64d9b2e2b7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pminsw.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pminsw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pminsw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + short *res = (short *) res_p; + int i; + for (i = 0; i < 4; i++) + res[i] = dst[i] < src[i] ? dst[i] : src[i]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pminsw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pminub.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pminub.c new file mode 100644 index 00000000000..372e5ef8764 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pminub.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pminub (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pminub (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned char *dst = (unsigned char *) dst_p; + unsigned char *src = (unsigned char *) src_p; + unsigned char *res = (unsigned char *) res_p; + int i; + for (i = 0; i < 8; i++) + res[i] = dst[i] < src[i] ? dst[i] : src[i]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pminub (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pmovmskb.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmovmskb.c new file mode 100644 index 00000000000..46b18d20558 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmovmskb.c @@ -0,0 +1,46 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pmovmskb (long long *ll1, int *r) +{ + __m64 t1 = *(__m64 *) ll1; + *r = _m_pmovmskb (t1); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *src_p, int *res_p) +{ + char *src = (char *) src_p; + int i; + int res = 0; + for (i = 0; i < 8; i++) + res |= ((src[i] & 0x80) >> 7) << i; + *res_p = res; +} + +static void +sse2_test (void) +{ + int i; + int r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + test_pmovmskb (&MMXops[i], &r); + compute_correct_result (&MMXops[i], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pmulhuw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmulhuw.c new file mode 100644 index 00000000000..0f8fcbe02b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmulhuw.c @@ -0,0 +1,51 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pmulhuw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pmulhuw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned short *dst = (unsigned short *) dst_p; + unsigned short *src = (unsigned short *) src_p; + unsigned short *res = (unsigned short *) res_p; + int i; + for (i = 0; i < 4; i++) + { + unsigned int t = dst[i] * src[i]; + res[i] = t >> 16; + } +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pmulhuw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pmulhw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmulhw.c new file mode 100644 index 00000000000..b89c58f3b6d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmulhw.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pmulhw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pmulhw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + short *res = (short *) res_p; + int tmp; + int i; + for (i = 0; i < 4; i++) + { + tmp = dst[i] * src[i]; + tmp >>= 16; + res[i] = tmp; + } +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pmulhw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pmullw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmullw.c new file mode 100644 index 00000000000..13b89622560 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmullw.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pmullw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pmullw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + short *res = (short *) res_p; + int tmp; + int i; + for (i = 0; i < 4; i++) + { + tmp = dst[i] * src[i]; + res[i] = tmp; + } +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pmullw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pmuludq.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmuludq.c new file mode 100644 index 00000000000..819e0e13c03 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pmuludq.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pmuludq (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _mm_mul_su32 (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned int *dst = (unsigned int*) dst_p; + unsigned int *src = (unsigned int *) src_p; + unsigned long long *res = (unsigned long long *) res_p; + res[0] = dst[0]; + res[0] *= src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pmuludq (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-por.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-por.c new file mode 100644 index 00000000000..9dc6072fffa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-por.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_por (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_por (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (unsigned long long *dst, + unsigned long long *src, + unsigned long long *res) +{ + res[0] = dst[0] | src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_por (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psadbw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psadbw.c new file mode 100644 index 00000000000..223d3b280bd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psadbw.c @@ -0,0 +1,58 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psadbw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psadbw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned char *dst = (unsigned char *) dst_p; + unsigned char *src = (unsigned char *) src_p; + unsigned short *res = (unsigned short *) res_p; + int i; + int tmp; + unsigned int sum = 0; + for (i = 0; i < 8; i++) + { + tmp = dst[i] - src[i]; + if (tmp < 0) + tmp = -tmp; + sum += tmp; + } + res[0] = sum; + for (i = 1; i < 4; i++) + res[i] = 0; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psadbw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pshufw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pshufw.c new file mode 100644 index 00000000000..b7236586216 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pshufw.c @@ -0,0 +1,248 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pshufw (long long *ll1, unsigned int imm, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + switch (imm) + { + case 0: + *(__m64 *) r = _m_pshufw (t1, 0); + break; + case 1: + *(__m64 *) r = _m_pshufw (t1, 1); + break; + case 2: + *(__m64 *) r = _m_pshufw (t1, 2); + break; + case 3: + *(__m64 *) r = _m_pshufw (t1, 3); + break; + case 4: + *(__m64 *) r = _m_pshufw (t1, 4); + break; + case 5: + *(__m64 *) r = _m_pshufw (t1, 5); + break; + case 6: + *(__m64 *) r = _m_pshufw (t1, 6); + break; + case 7: + *(__m64 *) r = _m_pshufw (t1, 7); + break; + case 8: + *(__m64 *) r = _m_pshufw (t1, 8); + break; + case 9: + *(__m64 *) r = _m_pshufw (t1, 9); + break; + case 10: + *(__m64 *) r = _m_pshufw (t1, 10); + break; + case 11: + *(__m64 *) r = _m_pshufw (t1, 11); + break; + case 12: + *(__m64 *) r = _m_pshufw (t1, 12); + break; + case 13: + *(__m64 *) r = _m_pshufw (t1, 13); + break; + case 14: + *(__m64 *) r = _m_pshufw (t1, 14); + break; + case 15: + *(__m64 *) r = _m_pshufw (t1, 15); + break; + case 16: + *(__m64 *) r = _m_pshufw (t1, 16); + break; + case 17: + *(__m64 *) r = _m_pshufw (t1, 17); + break; + case 18: + *(__m64 *) r = _m_pshufw (t1, 18); + break; + case 19: + *(__m64 *) r = _m_pshufw (t1, 19); + break; + case 20: + *(__m64 *) r = _m_pshufw (t1, 20); + break; + case 21: + *(__m64 *) r = _m_pshufw (t1, 21); + break; + case 22: + *(__m64 *) r = _m_pshufw (t1, 22); + break; + case 23: + *(__m64 *) r = _m_pshufw (t1, 23); + break; + case 24: + *(__m64 *) r = _m_pshufw (t1, 24); + break; + case 25: + *(__m64 *) r = _m_pshufw (t1, 25); + break; + case 26: + *(__m64 *) r = _m_pshufw (t1, 26); + break; + case 27: + *(__m64 *) r = _m_pshufw (t1, 27); + break; + case 28: + *(__m64 *) r = _m_pshufw (t1, 28); + break; + case 29: + *(__m64 *) r = _m_pshufw (t1, 29); + break; + case 30: + *(__m64 *) r = _m_pshufw (t1, 30); + break; + case 31: + *(__m64 *) r = _m_pshufw (t1, 31); + break; + case 32: + *(__m64 *) r = _m_pshufw (t1, 32); + break; + case 33: + *(__m64 *) r = _m_pshufw (t1, 33); + break; + case 34: + *(__m64 *) r = _m_pshufw (t1, 34); + break; + case 35: + *(__m64 *) r = _m_pshufw (t1, 35); + break; + case 36: + *(__m64 *) r = _m_pshufw (t1, 36); + break; + case 37: + *(__m64 *) r = _m_pshufw (t1, 37); + break; + case 38: + *(__m64 *) r = _m_pshufw (t1, 38); + break; + case 39: + *(__m64 *) r = _m_pshufw (t1, 39); + break; + case 40: + *(__m64 *) r = _m_pshufw (t1, 40); + break; + case 41: + *(__m64 *) r = _m_pshufw (t1, 41); + break; + case 42: + *(__m64 *) r = _m_pshufw (t1, 42); + break; + case 43: + *(__m64 *) r = _m_pshufw (t1, 43); + break; + case 44: + *(__m64 *) r = _m_pshufw (t1, 44); + break; + case 45: + *(__m64 *) r = _m_pshufw (t1, 45); + break; + case 46: + *(__m64 *) r = _m_pshufw (t1, 46); + break; + case 47: + *(__m64 *) r = _m_pshufw (t1, 47); + break; + case 48: + *(__m64 *) r = _m_pshufw (t1, 48); + break; + case 49: + *(__m64 *) r = _m_pshufw (t1, 49); + break; + case 50: + *(__m64 *) r = _m_pshufw (t1, 50); + break; + case 51: + *(__m64 *) r = _m_pshufw (t1, 51); + break; + case 52: + *(__m64 *) r = _m_pshufw (t1, 52); + break; + case 53: + *(__m64 *) r = _m_pshufw (t1, 53); + break; + case 54: + *(__m64 *) r = _m_pshufw (t1, 54); + break; + case 55: + *(__m64 *) r = _m_pshufw (t1, 55); + break; + case 56: + *(__m64 *) r = _m_pshufw (t1, 56); + break; + case 57: + *(__m64 *) r = _m_pshufw (t1, 57); + break; + case 58: + *(__m64 *) r = _m_pshufw (t1, 58); + break; + case 59: + *(__m64 *) r = _m_pshufw (t1, 59); + break; + case 60: + *(__m64 *) r = _m_pshufw (t1, 60); + break; + case 61: + *(__m64 *) r = _m_pshufw (t1, 61); + break; + case 62: + *(__m64 *) r = _m_pshufw (t1, 62); + break; + case 63: + *(__m64 *) r = _m_pshufw (t1, 63); + break; + default: + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *src_p, unsigned int imm, + long long *res_p) +{ + unsigned long long src = *(unsigned long long *) src_p; + unsigned short *res = (unsigned short *) res_p; + int i; + unsigned int shift; + for (i = 0; i < 4; i++) + { + shift = ((imm >> (2 * i)) & 0x3) * 16; + res[i] = (src >> shift) & 0xffff; + } +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + if (i > 63) + break; + test_pshufw (&MMXops[i], i, &r); + compute_correct_result (&MMXops[i], i, &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pslld.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pslld.c new file mode 100644 index 00000000000..86983c0b848 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pslld.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pslld (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pslld (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned int *dst = (unsigned int *) dst_p; + unsigned int *src = (unsigned int *) src_p; + unsigned int *res = (unsigned int *) res_p; + int i; + if (src[1] || src[0] > 31) + for (i = 0; i < 2; i++) + res[i] = 0; + else + for (i = 0; i < 2; i++) + res[i] = dst[i] << src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pslld (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pslldi.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pslldi.c new file mode 100644 index 00000000000..07f0ae9d83c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pslldi.c @@ -0,0 +1,153 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psllwi (long long *ll1, unsigned int imm, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + switch (imm) + { + case 0: + *(__m64 *) r = _m_pslldi (t1, 0); + break; + case 1: + *(__m64 *) r = _m_pslldi (t1, 1); + break; + case 2: + *(__m64 *) r = _m_pslldi (t1, 2); + break; + case 3: + *(__m64 *) r = _m_pslldi (t1, 3); + break; + case 4: + *(__m64 *) r = _m_pslldi (t1, 4); + break; + case 5: + *(__m64 *) r = _m_pslldi (t1, 5); + break; + case 6: + *(__m64 *) r = _m_pslldi (t1, 6); + break; + case 7: + *(__m64 *) r = _m_pslldi (t1, 7); + break; + case 8: + *(__m64 *) r = _m_pslldi (t1, 8); + break; + case 9: + *(__m64 *) r = _m_pslldi (t1, 9); + break; + case 10: + *(__m64 *) r = _m_pslldi (t1, 10); + break; + case 11: + *(__m64 *) r = _m_pslldi (t1, 11); + break; + case 12: + *(__m64 *) r = _m_pslldi (t1, 12); + break; + case 13: + *(__m64 *) r = _m_pslldi (t1, 13); + break; + case 14: + *(__m64 *) r = _m_pslldi (t1, 14); + break; + case 15: + *(__m64 *) r = _m_pslldi (t1, 15); + break; + case 16: + *(__m64 *) r = _m_pslldi (t1, 16); + break; + case 17: + *(__m64 *) r = _m_pslldi (t1, 17); + break; + case 18: + *(__m64 *) r = _m_pslldi (t1, 18); + break; + case 19: + *(__m64 *) r = _m_pslldi (t1, 19); + break; + case 20: + *(__m64 *) r = _m_pslldi (t1, 20); + break; + case 21: + *(__m64 *) r = _m_pslldi (t1, 21); + break; + case 22: + *(__m64 *) r = _m_pslldi (t1, 22); + break; + case 23: + *(__m64 *) r = _m_pslldi (t1, 23); + break; + case 24: + *(__m64 *) r = _m_pslldi (t1, 24); + break; + case 25: + *(__m64 *) r = _m_pslldi (t1, 25); + break; + case 26: + *(__m64 *) r = _m_pslldi (t1, 26); + break; + case 27: + *(__m64 *) r = _m_pslldi (t1, 27); + break; + case 28: + *(__m64 *) r = _m_pslldi (t1, 28); + break; + case 29: + *(__m64 *) r = _m_pslldi (t1, 29); + break; + case 30: + *(__m64 *) r = _m_pslldi (t1, 30); + break; + case 31: + *(__m64 *) r = _m_pslldi (t1, 31); + break; + default: + *(__m64 *) r = _m_pslldi (t1, 32); + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *src_p, unsigned int imm, + long long *res_p) +{ + unsigned int *src = (unsigned int *) src_p; + unsigned int *res = (unsigned int *) res_p; + int i; + if (imm > 31) + for (i = 0; i < 2; i++) + res[i] = 0; + else + for (i = 0; i < 2; i++) + res[i] = src[i] << imm; +} + +static void +sse2_test (void) +{ + int i; + unsigned int count; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + count = MMXops[i]; + test_psllwi (&MMXops[i], count, &r); + compute_correct_result (&MMXops[i], count, &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psllq.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psllq.c new file mode 100644 index 00000000000..37d2e0b22cc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psllq.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psllq (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psllq (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (unsigned long long *dst, + unsigned long long *src, + unsigned long long *res) +{ + if (src[0] > 63) + res[0] = 0; + else + res[0] = dst[0] << src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psllq (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psllqi.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psllqi.c new file mode 100644 index 00000000000..655b369e04f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psllqi.c @@ -0,0 +1,245 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psllwi (long long *ll1, unsigned int imm, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + switch (imm) + { + case 0: + *(__m64 *) r = _m_psllqi (t1, 0); + break; + case 1: + *(__m64 *) r = _m_psllqi (t1, 1); + break; + case 2: + *(__m64 *) r = _m_psllqi (t1, 2); + break; + case 3: + *(__m64 *) r = _m_psllqi (t1, 3); + break; + case 4: + *(__m64 *) r = _m_psllqi (t1, 4); + break; + case 5: + *(__m64 *) r = _m_psllqi (t1, 5); + break; + case 6: + *(__m64 *) r = _m_psllqi (t1, 6); + break; + case 7: + *(__m64 *) r = _m_psllqi (t1, 7); + break; + case 8: + *(__m64 *) r = _m_psllqi (t1, 8); + break; + case 9: + *(__m64 *) r = _m_psllqi (t1, 9); + break; + case 10: + *(__m64 *) r = _m_psllqi (t1, 10); + break; + case 11: + *(__m64 *) r = _m_psllqi (t1, 11); + break; + case 12: + *(__m64 *) r = _m_psllqi (t1, 12); + break; + case 13: + *(__m64 *) r = _m_psllqi (t1, 13); + break; + case 14: + *(__m64 *) r = _m_psllqi (t1, 14); + break; + case 15: + *(__m64 *) r = _m_psllqi (t1, 15); + break; + case 16: + *(__m64 *) r = _m_psllqi (t1, 16); + break; + case 17: + *(__m64 *) r = _m_psllqi (t1, 17); + break; + case 18: + *(__m64 *) r = _m_psllqi (t1, 18); + break; + case 19: + *(__m64 *) r = _m_psllqi (t1, 19); + break; + case 20: + *(__m64 *) r = _m_psllqi (t1, 20); + break; + case 21: + *(__m64 *) r = _m_psllqi (t1, 21); + break; + case 22: + *(__m64 *) r = _m_psllqi (t1, 22); + break; + case 23: + *(__m64 *) r = _m_psllqi (t1, 23); + break; + case 24: + *(__m64 *) r = _m_psllqi (t1, 24); + break; + case 25: + *(__m64 *) r = _m_psllqi (t1, 25); + break; + case 26: + *(__m64 *) r = _m_psllqi (t1, 26); + break; + case 27: + *(__m64 *) r = _m_psllqi (t1, 27); + break; + case 28: + *(__m64 *) r = _m_psllqi (t1, 28); + break; + case 29: + *(__m64 *) r = _m_psllqi (t1, 29); + break; + case 30: + *(__m64 *) r = _m_psllqi (t1, 30); + break; + case 31: + *(__m64 *) r = _m_psllqi (t1, 31); + break; + case 32: + *(__m64 *) r = _m_psllqi (t1, 32); + break; + case 33: + *(__m64 *) r = _m_psllqi (t1, 33); + break; + case 34: + *(__m64 *) r = _m_psllqi (t1, 34); + break; + case 35: + *(__m64 *) r = _m_psllqi (t1, 35); + break; + case 36: + *(__m64 *) r = _m_psllqi (t1, 36); + break; + case 37: + *(__m64 *) r = _m_psllqi (t1, 37); + break; + case 38: + *(__m64 *) r = _m_psllqi (t1, 38); + break; + case 39: + *(__m64 *) r = _m_psllqi (t1, 39); + break; + case 40: + *(__m64 *) r = _m_psllqi (t1, 40); + break; + case 41: + *(__m64 *) r = _m_psllqi (t1, 41); + break; + case 42: + *(__m64 *) r = _m_psllqi (t1, 42); + break; + case 43: + *(__m64 *) r = _m_psllqi (t1, 43); + break; + case 44: + *(__m64 *) r = _m_psllqi (t1, 44); + break; + case 45: + *(__m64 *) r = _m_psllqi (t1, 45); + break; + case 46: + *(__m64 *) r = _m_psllqi (t1, 46); + break; + case 47: + *(__m64 *) r = _m_psllqi (t1, 47); + break; + case 48: + *(__m64 *) r = _m_psllqi (t1, 48); + break; + case 49: + *(__m64 *) r = _m_psllqi (t1, 49); + break; + case 50: + *(__m64 *) r = _m_psllqi (t1, 50); + break; + case 51: + *(__m64 *) r = _m_psllqi (t1, 51); + break; + case 52: + *(__m64 *) r = _m_psllqi (t1, 52); + break; + case 53: + *(__m64 *) r = _m_psllqi (t1, 53); + break; + case 54: + *(__m64 *) r = _m_psllqi (t1, 54); + break; + case 55: + *(__m64 *) r = _m_psllqi (t1, 55); + break; + case 56: + *(__m64 *) r = _m_psllqi (t1, 56); + break; + case 57: + *(__m64 *) r = _m_psllqi (t1, 57); + break; + case 58: + *(__m64 *) r = _m_psllqi (t1, 58); + break; + case 59: + *(__m64 *) r = _m_psllqi (t1, 59); + break; + case 60: + *(__m64 *) r = _m_psllqi (t1, 60); + break; + case 61: + *(__m64 *) r = _m_psllqi (t1, 61); + break; + case 62: + *(__m64 *) r = _m_psllqi (t1, 62); + break; + case 63: + *(__m64 *) r = _m_psllqi (t1, 63); + break; + default: + *(__m64 *) r = _m_psllqi (t1, 64); + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (unsigned long long *src, unsigned int imm, + unsigned long long *res) +{ + int i; + if (imm > 63) + res[0] = 0; + else + res[0] = src[0] << imm; +} + +static void +sse2_test (void) +{ + int i; + unsigned int count; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + count = MMXops[i]; + test_psllwi (&MMXops[i], count, &r); + compute_correct_result (&MMXops[i], count, &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psllw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psllw.c new file mode 100644 index 00000000000..7c27d144185 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psllw.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psllw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psllw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned short *dst = (unsigned short *) dst_p; + unsigned int *src = (unsigned int *) src_p; + unsigned short *res = (unsigned short *) res_p; + int i; + if (src[1] || src[0] > 15) + for (i = 0; i < 4; i++) + res[i] = 0; + else + for (i = 0; i < 4; i++) + res[i] = dst[i] << src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psllw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psllwi.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psllwi.c new file mode 100644 index 00000000000..458463b2073 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psllwi.c @@ -0,0 +1,105 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psllwi (long long *ll1, unsigned int imm, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + switch (imm) + { + case 0: + *(__m64 *) r = _m_psllwi (t1, 0); + break; + case 1: + *(__m64 *) r = _m_psllwi (t1, 1); + break; + case 2: + *(__m64 *) r = _m_psllwi (t1, 2); + break; + case 3: + *(__m64 *) r = _m_psllwi (t1, 3); + break; + case 4: + *(__m64 *) r = _m_psllwi (t1, 4); + break; + case 5: + *(__m64 *) r = _m_psllwi (t1, 5); + break; + case 6: + *(__m64 *) r = _m_psllwi (t1, 6); + break; + case 7: + *(__m64 *) r = _m_psllwi (t1, 7); + break; + case 8: + *(__m64 *) r = _m_psllwi (t1, 8); + break; + case 9: + *(__m64 *) r = _m_psllwi (t1, 9); + break; + case 10: + *(__m64 *) r = _m_psllwi (t1, 10); + break; + case 11: + *(__m64 *) r = _m_psllwi (t1, 11); + break; + case 12: + *(__m64 *) r = _m_psllwi (t1, 12); + break; + case 13: + *(__m64 *) r = _m_psllwi (t1, 13); + break; + case 14: + *(__m64 *) r = _m_psllwi (t1, 14); + break; + case 15: + *(__m64 *) r = _m_psllwi (t1, 15); + break; + default: + *(__m64 *) r = _m_psllwi (t1, 16); + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *src_p, unsigned int imm, + long long *res_p) +{ + unsigned short *src = (unsigned short *) src_p; + unsigned short *res = (unsigned short *) res_p; + int i; + if (imm > 15) + for (i = 0; i < 4; i++) + res[i] = 0; + else + for (i = 0; i < 4; i++) + res[i] = src[i] << imm; +} + +static void +sse2_test (void) +{ + int i; + unsigned int count; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + count = MMXops[i]; + test_psllwi (&MMXops[i], count, &r); + compute_correct_result (&MMXops[i], count, &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psrad.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrad.c new file mode 100644 index 00000000000..494bcb4ccbd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrad.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psrad (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psrad (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + int *dst = (int *) dst_p; + unsigned int *src = (unsigned int *) src_p; + int *res = (int *) res_p; + int i; + if (src[1] || src[0] > 31) + for (i = 0; i < 2; i++) + res[i] = dst[i] < 0 ? -1 : 0; + else + for (i = 0; i < 2; i++) + res[i] = dst[i] >> src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psrad (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psradi.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psradi.c new file mode 100644 index 00000000000..4ae2ac848bc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psradi.c @@ -0,0 +1,153 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psradi (long long *ll1, unsigned int imm, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + switch (imm) + { + case 0: + *(__m64 *) r = _m_psradi (t1, 0); + break; + case 1: + *(__m64 *) r = _m_psradi (t1, 1); + break; + case 2: + *(__m64 *) r = _m_psradi (t1, 2); + break; + case 3: + *(__m64 *) r = _m_psradi (t1, 3); + break; + case 4: + *(__m64 *) r = _m_psradi (t1, 4); + break; + case 5: + *(__m64 *) r = _m_psradi (t1, 5); + break; + case 6: + *(__m64 *) r = _m_psradi (t1, 6); + break; + case 7: + *(__m64 *) r = _m_psradi (t1, 7); + break; + case 8: + *(__m64 *) r = _m_psradi (t1, 8); + break; + case 9: + *(__m64 *) r = _m_psradi (t1, 9); + break; + case 10: + *(__m64 *) r = _m_psradi (t1, 10); + break; + case 11: + *(__m64 *) r = _m_psradi (t1, 11); + break; + case 12: + *(__m64 *) r = _m_psradi (t1, 12); + break; + case 13: + *(__m64 *) r = _m_psradi (t1, 13); + break; + case 14: + *(__m64 *) r = _m_psradi (t1, 14); + break; + case 15: + *(__m64 *) r = _m_psradi (t1, 15); + break; + case 16: + *(__m64 *) r = _m_psradi (t1, 16); + break; + case 17: + *(__m64 *) r = _m_psradi (t1, 17); + break; + case 18: + *(__m64 *) r = _m_psradi (t1, 18); + break; + case 19: + *(__m64 *) r = _m_psradi (t1, 19); + break; + case 20: + *(__m64 *) r = _m_psradi (t1, 20); + break; + case 21: + *(__m64 *) r = _m_psradi (t1, 21); + break; + case 22: + *(__m64 *) r = _m_psradi (t1, 22); + break; + case 23: + *(__m64 *) r = _m_psradi (t1, 23); + break; + case 24: + *(__m64 *) r = _m_psradi (t1, 24); + break; + case 25: + *(__m64 *) r = _m_psradi (t1, 25); + break; + case 26: + *(__m64 *) r = _m_psradi (t1, 26); + break; + case 27: + *(__m64 *) r = _m_psradi (t1, 27); + break; + case 28: + *(__m64 *) r = _m_psradi (t1, 28); + break; + case 29: + *(__m64 *) r = _m_psradi (t1, 29); + break; + case 30: + *(__m64 *) r = _m_psradi (t1, 30); + break; + case 31: + *(__m64 *) r = _m_psradi (t1, 31); + break; + default: + *(__m64 *) r = _m_psradi (t1, 32); + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *src_p, unsigned int imm, + long long *res_p) +{ + int *src = (int *) src_p; + int *res = (int *) res_p; + int i; + if (imm > 31) + for (i = 0; i < 2; i++) + res[i] = src[i] < 0 ? -1 : 0; + else + for (i = 0; i < 2; i++) + res[i] = src[i] >> imm; +} + +static void +sse2_test (void) +{ + int i; + unsigned int count; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + count = MMXops[i]; + test_psradi (&MMXops[i], count, &r); + compute_correct_result (&MMXops[i], count, &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psraw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psraw.c new file mode 100644 index 00000000000..dd097f2e16b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psraw.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psraw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psraw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + unsigned int *src = (unsigned int *) src_p; + short *res = (short *) res_p; + int i; + if (src[1] || src[0] > 15) + for (i = 0; i < 4; i++) + res[i] = dst[i] < 0 ? -1 : 0; + else + for (i = 0; i < 4; i++) + res[i] = dst[i] >> src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psraw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psrawi.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrawi.c new file mode 100644 index 00000000000..30a2d8bd08b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrawi.c @@ -0,0 +1,105 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psrawi (long long *ll1, unsigned int imm, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + switch (imm) + { + case 0: + *(__m64 *) r = _m_psrawi (t1, 0); + break; + case 1: + *(__m64 *) r = _m_psrawi (t1, 1); + break; + case 2: + *(__m64 *) r = _m_psrawi (t1, 2); + break; + case 3: + *(__m64 *) r = _m_psrawi (t1, 3); + break; + case 4: + *(__m64 *) r = _m_psrawi (t1, 4); + break; + case 5: + *(__m64 *) r = _m_psrawi (t1, 5); + break; + case 6: + *(__m64 *) r = _m_psrawi (t1, 6); + break; + case 7: + *(__m64 *) r = _m_psrawi (t1, 7); + break; + case 8: + *(__m64 *) r = _m_psrawi (t1, 8); + break; + case 9: + *(__m64 *) r = _m_psrawi (t1, 9); + break; + case 10: + *(__m64 *) r = _m_psrawi (t1, 10); + break; + case 11: + *(__m64 *) r = _m_psrawi (t1, 11); + break; + case 12: + *(__m64 *) r = _m_psrawi (t1, 12); + break; + case 13: + *(__m64 *) r = _m_psrawi (t1, 13); + break; + case 14: + *(__m64 *) r = _m_psrawi (t1, 14); + break; + case 15: + *(__m64 *) r = _m_psrawi (t1, 15); + break; + default: + *(__m64 *) r = _m_psrawi (t1, 16); + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *src_p, unsigned int imm, + long long *res_p) +{ + short *src = (short *) src_p; + short *res = (short *) res_p; + int i; + if (imm > 15) + for (i = 0; i < 4; i++) + res[i] = src[i] < 0 ? -1 : 0; + else + for (i = 0; i < 4; i++) + res[i] = src[i] >> imm; +} + +static void +sse2_test (void) +{ + int i; + unsigned int count; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + count = MMXops[i]; + test_psrawi (&MMXops[i], count, &r); + compute_correct_result (&MMXops[i], count, &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psrld.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrld.c new file mode 100644 index 00000000000..3858be180a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrld.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psrld (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psrld (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + int *dst = (int *) dst_p; + unsigned int *src = (unsigned int *) src_p; + int *res = (int *) res_p; + int i; + if (src[1] || src[0] > 31) + for (i = 0; i < 2; i++) + res[i] = 0; + else + for (i = 0; i < 2; i++) + res[i] = dst[i] >> src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psrld (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psrldi.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrldi.c new file mode 100644 index 00000000000..9315b6f0137 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrldi.c @@ -0,0 +1,153 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psrldi (long long *ll1, unsigned int imm, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + switch (imm) + { + case 0: + *(__m64 *) r = _m_psrldi (t1, 0); + break; + case 1: + *(__m64 *) r = _m_psrldi (t1, 1); + break; + case 2: + *(__m64 *) r = _m_psrldi (t1, 2); + break; + case 3: + *(__m64 *) r = _m_psrldi (t1, 3); + break; + case 4: + *(__m64 *) r = _m_psrldi (t1, 4); + break; + case 5: + *(__m64 *) r = _m_psrldi (t1, 5); + break; + case 6: + *(__m64 *) r = _m_psrldi (t1, 6); + break; + case 7: + *(__m64 *) r = _m_psrldi (t1, 7); + break; + case 8: + *(__m64 *) r = _m_psrldi (t1, 8); + break; + case 9: + *(__m64 *) r = _m_psrldi (t1, 9); + break; + case 10: + *(__m64 *) r = _m_psrldi (t1, 10); + break; + case 11: + *(__m64 *) r = _m_psrldi (t1, 11); + break; + case 12: + *(__m64 *) r = _m_psrldi (t1, 12); + break; + case 13: + *(__m64 *) r = _m_psrldi (t1, 13); + break; + case 14: + *(__m64 *) r = _m_psrldi (t1, 14); + break; + case 15: + *(__m64 *) r = _m_psrldi (t1, 15); + break; + case 16: + *(__m64 *) r = _m_psrldi (t1, 16); + break; + case 17: + *(__m64 *) r = _m_psrldi (t1, 17); + break; + case 18: + *(__m64 *) r = _m_psrldi (t1, 18); + break; + case 19: + *(__m64 *) r = _m_psrldi (t1, 19); + break; + case 20: + *(__m64 *) r = _m_psrldi (t1, 20); + break; + case 21: + *(__m64 *) r = _m_psrldi (t1, 21); + break; + case 22: + *(__m64 *) r = _m_psrldi (t1, 22); + break; + case 23: + *(__m64 *) r = _m_psrldi (t1, 23); + break; + case 24: + *(__m64 *) r = _m_psrldi (t1, 24); + break; + case 25: + *(__m64 *) r = _m_psrldi (t1, 25); + break; + case 26: + *(__m64 *) r = _m_psrldi (t1, 26); + break; + case 27: + *(__m64 *) r = _m_psrldi (t1, 27); + break; + case 28: + *(__m64 *) r = _m_psrldi (t1, 28); + break; + case 29: + *(__m64 *) r = _m_psrldi (t1, 29); + break; + case 30: + *(__m64 *) r = _m_psrldi (t1, 30); + break; + case 31: + *(__m64 *) r = _m_psrldi (t1, 31); + break; + default: + *(__m64 *) r = _m_psrldi (t1, 32); + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *src_p, unsigned int imm, + long long *res_p) +{ + int *src = (int *) src_p; + int *res = (int *) res_p; + int i; + if (imm > 31) + for (i = 0; i < 2; i++) + res[i] = 0; + else + for (i = 0; i < 2; i++) + res[i] = src[i] >> imm; +} + +static void +sse2_test (void) +{ + int i; + unsigned int count; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + count = MMXops[i]; + test_psrldi (&MMXops[i], count, &r); + compute_correct_result (&MMXops[i], count, &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlq.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlq.c new file mode 100644 index 00000000000..064fb4aab7e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlq.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psrlq (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psrlq (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (unsigned long long *dst, + unsigned long long *src, + unsigned long long *res) +{ + if (src[0] > 63) + res[0] = 0; + else + res[0] = dst[0] >> src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psrlq (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlqi.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlqi.c new file mode 100644 index 00000000000..35de178efea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlqi.c @@ -0,0 +1,245 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psllwi (long long *ll1, unsigned int imm, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + switch (imm) + { + case 0: + *(__m64 *) r = _m_psrlqi (t1, 0); + break; + case 1: + *(__m64 *) r = _m_psrlqi (t1, 1); + break; + case 2: + *(__m64 *) r = _m_psrlqi (t1, 2); + break; + case 3: + *(__m64 *) r = _m_psrlqi (t1, 3); + break; + case 4: + *(__m64 *) r = _m_psrlqi (t1, 4); + break; + case 5: + *(__m64 *) r = _m_psrlqi (t1, 5); + break; + case 6: + *(__m64 *) r = _m_psrlqi (t1, 6); + break; + case 7: + *(__m64 *) r = _m_psrlqi (t1, 7); + break; + case 8: + *(__m64 *) r = _m_psrlqi (t1, 8); + break; + case 9: + *(__m64 *) r = _m_psrlqi (t1, 9); + break; + case 10: + *(__m64 *) r = _m_psrlqi (t1, 10); + break; + case 11: + *(__m64 *) r = _m_psrlqi (t1, 11); + break; + case 12: + *(__m64 *) r = _m_psrlqi (t1, 12); + break; + case 13: + *(__m64 *) r = _m_psrlqi (t1, 13); + break; + case 14: + *(__m64 *) r = _m_psrlqi (t1, 14); + break; + case 15: + *(__m64 *) r = _m_psrlqi (t1, 15); + break; + case 16: + *(__m64 *) r = _m_psrlqi (t1, 16); + break; + case 17: + *(__m64 *) r = _m_psrlqi (t1, 17); + break; + case 18: + *(__m64 *) r = _m_psrlqi (t1, 18); + break; + case 19: + *(__m64 *) r = _m_psrlqi (t1, 19); + break; + case 20: + *(__m64 *) r = _m_psrlqi (t1, 20); + break; + case 21: + *(__m64 *) r = _m_psrlqi (t1, 21); + break; + case 22: + *(__m64 *) r = _m_psrlqi (t1, 22); + break; + case 23: + *(__m64 *) r = _m_psrlqi (t1, 23); + break; + case 24: + *(__m64 *) r = _m_psrlqi (t1, 24); + break; + case 25: + *(__m64 *) r = _m_psrlqi (t1, 25); + break; + case 26: + *(__m64 *) r = _m_psrlqi (t1, 26); + break; + case 27: + *(__m64 *) r = _m_psrlqi (t1, 27); + break; + case 28: + *(__m64 *) r = _m_psrlqi (t1, 28); + break; + case 29: + *(__m64 *) r = _m_psrlqi (t1, 29); + break; + case 30: + *(__m64 *) r = _m_psrlqi (t1, 30); + break; + case 31: + *(__m64 *) r = _m_psrlqi (t1, 31); + break; + case 32: + *(__m64 *) r = _m_psrlqi (t1, 32); + break; + case 33: + *(__m64 *) r = _m_psrlqi (t1, 33); + break; + case 34: + *(__m64 *) r = _m_psrlqi (t1, 34); + break; + case 35: + *(__m64 *) r = _m_psrlqi (t1, 35); + break; + case 36: + *(__m64 *) r = _m_psrlqi (t1, 36); + break; + case 37: + *(__m64 *) r = _m_psrlqi (t1, 37); + break; + case 38: + *(__m64 *) r = _m_psrlqi (t1, 38); + break; + case 39: + *(__m64 *) r = _m_psrlqi (t1, 39); + break; + case 40: + *(__m64 *) r = _m_psrlqi (t1, 40); + break; + case 41: + *(__m64 *) r = _m_psrlqi (t1, 41); + break; + case 42: + *(__m64 *) r = _m_psrlqi (t1, 42); + break; + case 43: + *(__m64 *) r = _m_psrlqi (t1, 43); + break; + case 44: + *(__m64 *) r = _m_psrlqi (t1, 44); + break; + case 45: + *(__m64 *) r = _m_psrlqi (t1, 45); + break; + case 46: + *(__m64 *) r = _m_psrlqi (t1, 46); + break; + case 47: + *(__m64 *) r = _m_psrlqi (t1, 47); + break; + case 48: + *(__m64 *) r = _m_psrlqi (t1, 48); + break; + case 49: + *(__m64 *) r = _m_psrlqi (t1, 49); + break; + case 50: + *(__m64 *) r = _m_psrlqi (t1, 50); + break; + case 51: + *(__m64 *) r = _m_psrlqi (t1, 51); + break; + case 52: + *(__m64 *) r = _m_psrlqi (t1, 52); + break; + case 53: + *(__m64 *) r = _m_psrlqi (t1, 53); + break; + case 54: + *(__m64 *) r = _m_psrlqi (t1, 54); + break; + case 55: + *(__m64 *) r = _m_psrlqi (t1, 55); + break; + case 56: + *(__m64 *) r = _m_psrlqi (t1, 56); + break; + case 57: + *(__m64 *) r = _m_psrlqi (t1, 57); + break; + case 58: + *(__m64 *) r = _m_psrlqi (t1, 58); + break; + case 59: + *(__m64 *) r = _m_psrlqi (t1, 59); + break; + case 60: + *(__m64 *) r = _m_psrlqi (t1, 60); + break; + case 61: + *(__m64 *) r = _m_psrlqi (t1, 61); + break; + case 62: + *(__m64 *) r = _m_psrlqi (t1, 62); + break; + case 63: + *(__m64 *) r = _m_psrlqi (t1, 63); + break; + default: + *(__m64 *) r = _m_psrlqi (t1, 64); + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (unsigned long long *src, unsigned int imm, + unsigned long long *res) +{ + int i; + if (imm > 63) + res[0] = 0; + else + res[0] = src[0] >> imm; +} + +static void +sse2_test (void) +{ + int i; + unsigned int count; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + count = MMXops[i]; + test_psllwi (&MMXops[i], count, &r); + compute_correct_result (&MMXops[i], count, &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlw.c new file mode 100644 index 00000000000..d2c1680ba5d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlw.c @@ -0,0 +1,52 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psrlw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psrlw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + unsigned int *src = (unsigned int *) src_p; + short *res = (short *) res_p; + int i; + if (src[1] || src[0] > 15) + for (i = 0; i < 4; i++) + res[i] = 0; + else + for (i = 0; i < 4; i++) + res[i] = dst[i] >> src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psrlw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlwi.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlwi.c new file mode 100644 index 00000000000..0dbffa56299 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psrlwi.c @@ -0,0 +1,105 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psrlwi (long long *ll1, unsigned int imm, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + switch (imm) + { + case 0: + *(__m64 *) r = _m_psrlwi (t1, 0); + break; + case 1: + *(__m64 *) r = _m_psrlwi (t1, 1); + break; + case 2: + *(__m64 *) r = _m_psrlwi (t1, 2); + break; + case 3: + *(__m64 *) r = _m_psrlwi (t1, 3); + break; + case 4: + *(__m64 *) r = _m_psrlwi (t1, 4); + break; + case 5: + *(__m64 *) r = _m_psrlwi (t1, 5); + break; + case 6: + *(__m64 *) r = _m_psrlwi (t1, 6); + break; + case 7: + *(__m64 *) r = _m_psrlwi (t1, 7); + break; + case 8: + *(__m64 *) r = _m_psrlwi (t1, 8); + break; + case 9: + *(__m64 *) r = _m_psrlwi (t1, 9); + break; + case 10: + *(__m64 *) r = _m_psrlwi (t1, 10); + break; + case 11: + *(__m64 *) r = _m_psrlwi (t1, 11); + break; + case 12: + *(__m64 *) r = _m_psrlwi (t1, 12); + break; + case 13: + *(__m64 *) r = _m_psrlwi (t1, 13); + break; + case 14: + *(__m64 *) r = _m_psrlwi (t1, 14); + break; + case 15: + *(__m64 *) r = _m_psrlwi (t1, 15); + break; + default: + *(__m64 *) r = _m_psrlwi (t1, 16); + break; + } +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *src_p, unsigned int imm, + long long *res_p) +{ + short *src = (short *) src_p; + short *res = (short *) res_p; + int i; + if (imm > 15) + for (i = 0; i < 4; i++) + res[i] = 0; + else + for (i = 0; i < 4; i++) + res[i] = src[i] >> imm; +} + +static void +sse2_test (void) +{ + int i; + unsigned int count; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i++) + { + count = MMXops[i]; + test_psrlwi (&MMXops[i], count, &r); + compute_correct_result (&MMXops[i], count, &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psubb.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubb.c new file mode 100644 index 00000000000..de0076a1654 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubb.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psubb (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psubb (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + char *dst = (char *) dst_p; + char *src = (char *) src_p; + char *res = (char *) res_p; + int i; + for (i = 0; i < 8; i++) + res[i] = dst[i] - src[i]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psubb (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psubd.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubd.c new file mode 100644 index 00000000000..344f632b6d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubd.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psubd (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psubd (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + int *dst = (int *) dst_p; + int *src = (int *) src_p; + int *res = (int *) res_p; + int i; + for (i = 0; i < 2; i++) + res[i] = dst[i] - src[i]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psubd (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psubq.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubq.c new file mode 100644 index 00000000000..613f302bf6a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubq.c @@ -0,0 +1,43 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psubq (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _mm_sub_si64 (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + res_p[0] = dst_p[0] - src_p[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psubq (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psubusb.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubusb.c new file mode 100644 index 00000000000..ad6112a5d33 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubusb.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psubusb (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psubusb (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned char *dst = (unsigned char *) dst_p; + unsigned char *src = (unsigned char *) src_p; + unsigned char *res = (unsigned char *) res_p; + int i; + for (i = 0; i < 8; i++) + res[i] = saturate_ub (dst[i] - src[i]); +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psubusb (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psubusw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubusw.c new file mode 100644 index 00000000000..8a8a9c0fb4d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubusw.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psubusw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psubusw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + unsigned short *dst = (unsigned short *) dst_p; + unsigned short *src = (unsigned short *) src_p; + unsigned short *res = (unsigned short *) res_p; + int i; + for (i = 0; i < 4; i++) + res[i] = saturate_uw (dst[i] - src[i]); +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psubusw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-psubw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubw.c new file mode 100644 index 00000000000..4d53c8c419a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-psubw.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_psubw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_psubw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + short *res = (short *) res_p; + int i; + for (i = 0; i < 4; i++) + res[i] = dst[i] - src[i]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_psubw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhbw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhbw.c new file mode 100644 index 00000000000..07281f2c3a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhbw.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_punpckhbw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_punpckhbw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + char *dst = (char *) dst_p; + char *src = (char *) src_p; + char *res = (char *) res_p; + res[0] = dst[4]; + res[1] = src[4]; + res[2] = dst[5]; + res[3] = src[5]; + res[4] = dst[6]; + res[5] = src[6]; + res[6] = dst[7]; + res[7] = src[7]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_punpckhbw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhdq.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhdq.c new file mode 100644 index 00000000000..6c67af92b19 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhdq.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_punpckhdq (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_punpckhdq (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + int *dst = (int *) dst_p; + int *src = (int *) src_p; + int *res = (int *) res_p; + res[0] = dst[1]; + res[1] = src[1]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_punpckhdq (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhwd.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhwd.c new file mode 100644 index 00000000000..b6c348323ea --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckhwd.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_punpckhwd (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_punpckhwd (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + short *res = (short *) res_p; + res[0] = dst[2]; + res[1] = src[2]; + res[2] = dst[3]; + res[3] = src[3]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_punpckhwd (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-punpcklbw.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpcklbw.c new file mode 100644 index 00000000000..dcf6d3f25bb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpcklbw.c @@ -0,0 +1,53 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_punpcklbw (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_punpcklbw (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + char *dst = (char *) dst_p; + char *src = (char *) src_p; + char *res = (char *) res_p; + res[0] = dst[0]; + res[1] = src[0]; + res[2] = dst[1]; + res[3] = src[1]; + res[4] = dst[2]; + res[5] = src[2]; + res[6] = dst[3]; + res[7] = src[3]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_punpcklbw (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckldq.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckldq.c new file mode 100644 index 00000000000..463c6d2c989 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpckldq.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_punpckldq (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_punpckldq (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + int *dst = (int *) dst_p; + int *src = (int *) src_p; + int *res = (int *) res_p; + res[0] = dst[0]; + res[1] = src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_punpckldq (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-punpcklwd.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpcklwd.c new file mode 100644 index 00000000000..acd62f5bd74 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-punpcklwd.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_punpcklwd (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_punpcklwd (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (long long *dst_p, long long *src_p, + long long *res_p) +{ + short *dst = (short *) dst_p; + short *src = (short *) src_p; + short *res = (short *) res_p; + res[0] = dst[0]; + res[1] = src[0]; + res[2] = dst[1]; + res[3] = src[1]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_punpcklwd (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx-pxor.c b/gcc/testsuite/gcc.target/i386/sse2-mmx-pxor.c new file mode 100644 index 00000000000..be632989c35 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx-pxor.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */ +/* { dg-additional-options "-mno-mmx" { target { ! ia32 } } } */ + +#include "sse2-check.h" +#include "mmx-vals.h" + +__attribute__((noinline, noclone)) +static void +test_pxor (long long *ll1, long long *ll2, long long *r) +{ + __m64 t1 = *(__m64 *) ll1; + __m64 t2 = *(__m64 *) ll2; + *(__m64 *) r = _m_pxor (t1, t2); +} + +/* Routine to manually compute the results */ +static void +compute_correct_result (unsigned long long *dst, + unsigned long long *src, + unsigned long long *res) +{ + res[0] = dst[0] ^ src[0]; +} + +static void +sse2_test (void) +{ + int i; + long long r, ck; + int fail = 0; + + /* Run the MMX tests */ + for (i = 0; i < MMX_num_ops; i += 2) + { + test_pxor (&MMXops[i], &MMXops[i + 1], &r); + compute_correct_result (&MMXops[i], &MMXops[i + 1], &ck); + if (ck != r) + fail++; + } + + if (fail != 0) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse2-mmx.c b/gcc/testsuite/gcc.target/i386/sse2-mmx.c index fb226a8e8f3..338cb9da289 100644 --- a/gcc/testsuite/gcc.target/i386/sse2-mmx.c +++ b/gcc/testsuite/gcc.target/i386/sse2-mmx.c @@ -4,7 +4,6 @@ #include "sse2-check.h" -#include #define N 4