From patchwork Wed Feb 13 14:18:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1041294 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4401ql0Qjcz9s5c for ; Thu, 14 Feb 2019 01:19:31 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C1FE7C21F90; Wed, 13 Feb 2019 14:19:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 95CB2C21FC6; Wed, 13 Feb 2019 14:18:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B2778C21F7F; Wed, 13 Feb 2019 14:18:47 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id 7C8C9C21F90 for ; Wed, 13 Feb 2019 14:18:46 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2019 06:18:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,365,1544515200"; d="scan'208";a="114609784" Received: from pg-iccf0436.altera.com ([10.104.2.187]) by orsmga007.jf.intel.com with ESMTP; 13 Feb 2019 06:18:43 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 13 Feb 2019 22:18:31 +0800 Message-Id: <1550067518-2542-2-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> References: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH v8 1/8] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee This patch adds description on properties about file name used for both peripheral bitstream and core bitstream. Signed-off-by: Tien Fong Chee --- changes for v8 - Removed explanation about support for altr,bitstream-core changes for v7 - Provided example of setting FPGA FIT image for both early IO release and full release FPGA configuration. --- .../fpga/altera-socfpga-a10-fpga-mgr.txt | 26 +++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt index 2fd8e7a..da210bf 100644 --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt @@ -7,8 +7,31 @@ Required properties: - The second index is for writing FPGA configuration data. - resets : Phandle and reset specifier for the device's reset. - clocks : Clocks used by the device. +- altr,bitstream : Fit image file name for both FPGA peripheral bitstream, + FPGA core bitstream and full bitstream. -Example: + Full bitstream, consist of peripheral bitstream and core + bitstream. + + FPGA peripheral bitstream is used to initialize FPGA IOs, + PLL, IO48 and DDR. This bitstream is required to get DDR up + running. + + FPGA core bitstream contains FPGA design which is used to + program FPGA CRAM and ERAM. + +Example: Bundles both peripheral bitstream and core bitstream into FIT image + called fit_spl_fpga.itb. This FIT image can be created through running + this command: tools/mkimage + -E -p 400 + -f board/altera/arria10-socdk/fit_spl_fpga.its + fit_spl_fpga.itb + + For details of describing structure and contents of the FIT image, + please refer board/altera/arria10-socdk/fit_spl_fpga.its + +- Examples for booting with full release or booting with early IO release, then + follow by entering early user mode: fpga_mgr: fpga-mgr@ffd03000 { compatible = "altr,socfpga-a10-fpga-mgr"; @@ -16,4 +39,5 @@ Example: 0xffcfe400 0x20>; clocks = <&l4_mp_clk>; resets = <&rst FPGAMGR_RESET>; + altr,bitstream = "fit_spl_fpga.itb"; }; From patchwork Wed Feb 13 14:18:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1041295 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4401rb2p3xz9s5c for ; Thu, 14 Feb 2019 01:20:15 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F1F59C21FD1; Wed, 13 Feb 2019 14:19:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 10E2BC22048; Wed, 13 Feb 2019 14:18:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 328C8C21F7E; Wed, 13 Feb 2019 14:18:49 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id 7E81BC21F7E for ; Wed, 13 Feb 2019 14:18:47 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2019 06:18:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,365,1544515200"; d="scan'208";a="114609791" Received: from pg-iccf0436.altera.com ([10.104.2.187]) by orsmga007.jf.intel.com with ESMTP; 13 Feb 2019 06:18:45 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 13 Feb 2019 22:18:32 +0800 Message-Id: <1550067518-2542-3-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> References: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH v8 2/8] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Add default fitImage file bundling FPGA bitstreams for Arria10. Signed-off-by: Tien Fong Chee --- changes for v8 - Changed the FPGA node name to fpga-core and fpga-periph for both core and periph bitstreams respectively. --- board/altera/arria10-socdk/fit_spl_fpga.its | 39 +++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its new file mode 100644 index 0000000..8ce175b --- /dev/null +++ b/board/altera/arria10-socdk/fit_spl_fpga.its @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 + /* + * Copyright (C) 2019 Intel Corporation + * + */ + +/dts-v1/; + +/ { + description = "FIT image with FPGA bistream"; + #address-cells = <1>; + + images { + fpga-core@1 { + description = "FPGA core bitstream"; + data = /incbin/("../../../ghrd_10as066n2.core.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + load = <0x400>; + }; + + fpga-periph@2 { + description = "FPGA peripheral bitstream"; + data = /incbin/("../../../ghrd_10as066n2.periph.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "Boot with FPGA early IO release config"; + fpga = "fpga-periph@2", "fpga-core@1"; + }; + }; +}; From patchwork Wed Feb 13 14:18:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1041296 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4401sW5MD9z9s5c for ; Thu, 14 Feb 2019 01:21:03 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6044BC2201E; Wed, 13 Feb 2019 14:19:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AB81EC21FB5; Wed, 13 Feb 2019 14:18:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BDC72C22096; Wed, 13 Feb 2019 14:18:54 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id A6A08C21FCE for ; Wed, 13 Feb 2019 14:18:49 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2019 06:18:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,365,1544515200"; d="scan'208";a="114609794" Received: from pg-iccf0436.altera.com ([10.104.2.187]) by orsmga007.jf.intel.com with ESMTP; 13 Feb 2019 06:18:47 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 13 Feb 2019 22:18:33 +0800 Message-Id: <1550067518-2542-4-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> References: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH v8 3/8] fit: Add function declarations to the header file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Adding some function declarations to the header file, so these functions can be referred by other C files. Signed-off-by: Tien Fong Chee --- include/image.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/image.h b/include/image.h index 83a2d41..f839443 100644 --- a/include/image.h +++ b/include/image.h @@ -1041,6 +1041,10 @@ int fit_check_format(const void *fit); int fit_conf_find_compat(const void *fit, const void *fdt); int fit_conf_get_node(const void *fit, const char *conf_uname); +int fit_conf_get_prop_node_count(const void *fit, int noffset, + const char *prop_name); +int fit_conf_get_prop_node_index(const void *fit, int noffset, + const char *prop_name, int index); /** * fit_conf_get_prop_node() - Get node refered to by a configuration From patchwork Wed Feb 13 14:18:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1041297 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4401sY2SH6z9s5c for ; Thu, 14 Feb 2019 01:21:05 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0655AC2207B; Wed, 13 Feb 2019 14:20:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 43402C21FB8; Wed, 13 Feb 2019 14:19:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A6291C21FCC; Wed, 13 Feb 2019 14:18:56 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id 10E13C2208F for ; Wed, 13 Feb 2019 14:18:51 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2019 06:18:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,365,1544515200"; d="scan'208";a="114609799" Received: from pg-iccf0436.altera.com ([10.104.2.187]) by orsmga007.jf.intel.com with ESMTP; 13 Feb 2019 06:18:49 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 13 Feb 2019 22:18:34 +0800 Message-Id: <1550067518-2542-5-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> References: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH v8 4/8] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Add FPGA driver to support program FPGA with FPGA bitstream loading from filesystem. The driver are designed based on generic firmware loader framework. The driver can handle FPGA program operation from loading FPGA bitstream in flash to memory and then to program FPGA. Signed-off-by: Tien Fong Chee --- changes for v8 - Added codes to discern bitstream type based on fpga node name. changes for v7 - Restructure the FPGA driver to support both peripheral bitstream and core bitstream bundled into FIT image. - Support loadable property for core bitstream. User can set loadable in DDR for better performance. This loading would be done in one large chunk instead of chunk by chunk loading with small memory buffer. --- arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 17 + .../include/mach/fpga_manager_arria10.h | 39 +- drivers/fpga/socfpga_arria10.c | 467 ++++++++++++++++++++- 3 files changed, 500 insertions(+), 23 deletions(-) diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts index 998d811..14f1967 100644 --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts @@ -18,6 +18,23 @@ /dts-v1/; #include "socfpga_arria10_socdk.dtsi" +/ { + chosen { + firmware-loader = &fs_loader0; + }; + + fs_loader0: fs-loader@0 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&mmc 1>; + }; +}; + +&fpga_mgr { + u-boot,dm-pre-reloc; + altr,bitstream = "fit_spl_fpga.itb"; +}; + &mmc { u-boot,dm-pre-reloc; status = "okay"; diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h index 09d13f6..5ef15bb 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h @@ -1,9 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2017 Intel Corporation + * Copyright (C) 2017-2019 Intel Corporation * All rights reserved. */ +#include +#include +#include + #ifndef _FPGA_MANAGER_ARRIA10_H_ #define _FPGA_MANAGER_ARRIA10_H_ @@ -51,6 +55,10 @@ #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d +#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001 +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001 #ifndef __ASSEMBLY__ struct socfpga_fpga_manager { @@ -88,12 +96,39 @@ struct socfpga_fpga_manager { u32 imgcfg_fifo_status; }; +enum rbf_type { + unknown, + periph_section, + core_section +}; + +enum rbf_security { + invalid, + unencrypted, + encrypted +}; + +struct rbf_info { + enum rbf_type section; + enum rbf_security security; +}; + +struct fpga_loadfs_info { + fpga_fs_info *fpga_fsinfo; + u32 remaining; + u32 offset; + struct rbf_info rbfinfo; +}; + /* Functions */ int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); int fpgamgr_program_finish(void); int is_fpgamgr_user_mode(void); int fpgamgr_wait_early_user_mode(void); - +int is_fpgamgr_early_user_mode(void); +char *get_fpga_filename(const void *fdt, int *len); +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, + u32 offset); #endif /* __ASSEMBLY__ */ #endif /* _FPGA_MANAGER_ARRIA10_H_ */ diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 114dd91..630d5a3 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -1,8 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2017 Intel Corporation + * Copyright (C) 2017-2019 Intel Corporation */ - #include #include #include @@ -10,8 +9,11 @@ #include #include #include +#include #include +#include #include +#include #include #include @@ -64,7 +66,7 @@ static int wait_for_user_mode(void) 1, FPGA_TIMEOUT_MSEC, false); } -static int is_fpgamgr_early_user_mode(void) +int is_fpgamgr_early_user_mode(void) { return (readl(&fpga_manager_base->imgcfg_stat) & ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0; @@ -92,9 +94,10 @@ int fpgamgr_wait_early_user_mode(void) sizeof(sync_data)); udelay(FPGA_TIMEOUT_MSEC); i++; + WATCHDOG_RESET(); } - debug("Additional %i sync word needed\n", i); + debug("FPGA: Additional %i sync word needed\n", i); /* restoring original CDRATIO */ fpgamgr_set_cd_ratio(cd_ratio); @@ -172,9 +175,10 @@ static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data, compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1; compress = !compress; - debug("header word %d = %08x\n", 69, rbf_data[69]); - debug("header word %d = %08x\n", 229, rbf_data[229]); - debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress); + debug("FPGA: Header word %d = %08x.\n", 69, rbf_data[69]); + debug("FPGA: Header word %d = %08x.\n", 229, rbf_data[229]); + debug("FPGA: Read from rbf header: encrypt=%d compress=%d.\n", encrypt, + compress); /* * from the register map description of cdratio in imgcfg_ctrl_02: @@ -359,6 +363,7 @@ static int fpgamgr_program_poll_cd(void) printf("nstatus == 0 while waiting for condone\n"); return -EPERM; } + WATCHDOG_RESET(); } if (i == FPGA_TIMEOUT_CNT) @@ -432,7 +437,6 @@ int fpgamgr_program_finish(void) printf("FPGA: Poll CD failed with error code %d\n", status); return -EPERM; } - WATCHDOG_RESET(); /* Ensure the FPGA entering user mode */ status = fpgamgr_program_poll_usermode(); @@ -447,27 +451,448 @@ int fpgamgr_program_finish(void) return 0; } -/* - * FPGA Manager to program the FPGA. This is the interface used by FPGA driver. - * Return 0 for sucess, non-zero for error. - */ +char *get_fpga_filename(const void *fdt, int *len) +{ + char *fpga_filename = NULL; + int node_offset; + + fdtdec_find_aliases_for_id(gd->fdt_blob, "fpga_mgr", + COMPAT_ALTERA_SOCFPGA_FPGA0, + &node_offset, 1); + + ofnode fpgamgr_node = offset_to_ofnode(node_offset); + + if (ofnode_valid(fpgamgr_node)) + fpga_filename = (char *)ofnode_read_string(fpgamgr_node, + "altr,bitstream"); + + + return fpga_filename; +} + +static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer) +{ + /* + * Magic ID starting at: + * -> 1st dword[15:0] in periph.rbf + * -> 2nd dword[15:0] in core.rbf + * Note: dword == 32 bits + */ + u32 word_reading_max = 2; + u32 i; + + for (i = 0; i < word_reading_max; i++) { + if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) { + rbf->security = unencrypted; + } else if (*(buffer + i) == FPGA_SOCFPGA_A10_RBF_ENCRYPTED) { + rbf->security = encrypted; + } else if (*(buffer + i + 1) == + FPGA_SOCFPGA_A10_RBF_UNENCRYPTED) { + rbf->security = unencrypted; + } else if (*(buffer + i + 1) == + FPGA_SOCFPGA_A10_RBF_ENCRYPTED) { + rbf->security = encrypted; + } else { + rbf->security = invalid; + continue; + } + + /* PERIPH RBF(buffer + i + 1), CORE RBF(buffer + i + 2) */ + if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_PERIPH) { + rbf->section = periph_section; + break; + } else if (*(buffer + i + 1) == FPGA_SOCFPGA_A10_RBF_CORE) { + rbf->section = core_section; + break; + } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_PERIPH) { + rbf->section = periph_section; + break; + } else if (*(buffer + i + 2) == FPGA_SOCFPGA_A10_RBF_CORE) { + rbf->section = core_section; + break; + } + + rbf->section = unknown; + break; + + WATCHDOG_RESET(); + } +} + +#ifdef CONFIG_FS_LOADER +static int first_loading_rbf_to_buffer(struct udevice *dev, + struct fpga_loadfs_info *fpga_loadfs, + u32 *buffer, size_t *buffer_bsize) +{ + u32 *buffer_p = (u32 *)*buffer; + u32 *loadable = buffer_p; + size_t buffer_size = *buffer_bsize; + size_t fit_size; + int ret, i, count; + int confs_noffset, images_noffset; + int rbf_offset; + int rbf_size; + const char *fpga_node_name = NULL; + const char *uname = NULL; + + /* Load image header into buffer */ + ret = request_firmware_into_buf(dev, + fpga_loadfs->fpga_fsinfo->filename, + buffer_p, + sizeof(struct image_header), + 0); + if (ret < 0) { + debug("FPGA: Failed to read image header from flash.\n"); + return -ENOENT; + } + + if (image_get_magic((struct image_header *)buffer_p) != FDT_MAGIC) { + debug("FPGA: No FDT magic was found.\n"); + return -EBADF; + } + + fit_size = fdt_totalsize(buffer_p); + + if (fit_size > buffer_size) { + debug("FPGA: FIT image is larger than available buffer.\n"); + debug("Please use FIT external data or increasing buffer.\n"); + return -ENOMEM; + } + + /* Load entire FIT into buffer */ + ret = request_firmware_into_buf(dev, + fpga_loadfs->fpga_fsinfo->filename, + buffer_p, + fit_size, + 0); + + if (ret < 0) + return ret; + + ret = fit_check_format(buffer_p); + if (!ret) { + debug("FPGA: No valid FIT image was found.\n"); + return -EBADF; + } + + confs_noffset = fdt_path_offset(buffer_p, FIT_CONFS_PATH); + images_noffset = fdt_path_offset(buffer_p, FIT_IMAGES_PATH); + if (confs_noffset < 0 || images_noffset < 0) { + debug("FPGA: No Configurations or images nodes were found.\n"); + return -ENOENT; + } + + /* Get default configuration unit name from default property */ + confs_noffset = fit_conf_get_node(buffer_p, NULL); + if (confs_noffset < 0) { + debug("FPGA: No default configuration was found in config.\n"); + return -ENOENT; + } + + count = fit_conf_get_prop_node_count(buffer_p, confs_noffset, + FIT_FPGA_PROP); + + if (count < 0) { + debug("FPGA: Invalid configuration format for FPGA node.\n"); + return count; + } else { + debug("FPGA: FPGA node count: %d\n", count); + } + + for (i = 0; i < count; i++) { + images_noffset = fit_conf_get_prop_node_index(buffer_p, + confs_noffset, + FIT_FPGA_PROP, i); + uname = fit_get_name(buffer_p, images_noffset, NULL); + if (uname) { + debug("FPGA: %s\n", uname); + + if (strstr(uname, "fpga-periph") && + (!is_fpgamgr_early_user_mode() || + is_fpgamgr_user_mode())) { + fpga_node_name = uname; + printf("FPGA: Start to program "); + printf("peripheral/full bitstream ...\n"); + break; + } else if (strstr(uname, "fpga-core") && + (is_fpgamgr_early_user_mode() && + !is_fpgamgr_user_mode())) { + fpga_node_name = uname; + printf("FPGA: Start to program core "); + printf("bitstream ...\n"); + break; + } + } + WATCHDOG_RESET(); + } + + if (!fpga_node_name) { + debug("FPGA: No suitable bitstream was found, count: %d.\n", i); + return 1; + } + + images_noffset = fit_image_get_node(buffer_p, fpga_node_name); + if (images_noffset < 0) { + debug("FPGA: No node '%s' was found in FIT.\n", + fpga_node_name); + return -ENOENT; + } + + ret = fit_image_get_data_position(buffer_p, images_noffset, + &rbf_offset); + if (ret < 0) { + debug("FPGA: No data position was found (err=%d).\n", ret); + return -ENOENT; + } + + ret = fit_image_get_data_size(buffer_p, images_noffset, &rbf_size); + if (ret < 0) { + debug("FPGA: No data size was found (err=%d).\n", ret); + return -ENOENT; + } + + ret = fit_image_get_load(buffer_p, images_noffset, (ulong *)loadable); + if (ret < 0) { + debug("FPGA: No loadable was found (err=%d).\n", ret); + debug("FPGA: Using default buffer and size.\n"); + } else { + buffer_p = (u32 *)*loadable; + buffer_size = rbf_size; + debug("FPGA: Found loadable address = 0x%x.\n", *loadable); + } + + debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n", + rbf_offset, rbf_size); + + fpga_loadfs->remaining = rbf_size; + + /* + * Determine buffer size vs bitstream size, and calculating number of + * chunk by chunk transfer is required due to smaller buffer size + * compare to bitstream + */ + if (rbf_size <= buffer_size) { + /* Loading whole bitstream into buffer */ + buffer_size = rbf_size; + fpga_loadfs->remaining = 0; + } else { + fpga_loadfs->remaining -= buffer_size; + } + + fpga_loadfs->offset = rbf_offset; + /* Loading bitstream into buffer */ + ret = request_firmware_into_buf(dev, + fpga_loadfs->fpga_fsinfo->filename, + buffer_p, + buffer_size, + fpga_loadfs->offset); + if (ret < 0) { + debug("FPGA: Failed to read bitstream from flash.\n"); + return -ENOENT; + } + + /* Getting info about bitstream types */ + get_rbf_image_info(&fpga_loadfs->rbfinfo, (u16 *)buffer_p); + + /* Update next reading bitstream offset */ + fpga_loadfs->offset += buffer_size; + + /* Update the final addr for bitstream */ + *buffer = (u32)buffer_p; + + /* Update the size of bitstream to be programmed into FPGA */ + *buffer_bsize = buffer_size; + + return 0; +} + +static int subsequent_loading_rbf_to_buffer(struct udevice *dev, + struct fpga_loadfs_info *fpga_loadfs, + u32 *buffer, size_t *buffer_bsize) +{ + int ret = 0; + u32 *buffer_p = (u32 *)*buffer; + + /* Read the bitstream chunk by chunk. */ + if (fpga_loadfs->remaining > *buffer_bsize) { + fpga_loadfs->remaining -= *buffer_bsize; + } else { + *buffer_bsize = fpga_loadfs->remaining; + fpga_loadfs->remaining = 0; + } + + ret = request_firmware_into_buf(dev, + fpga_loadfs->fpga_fsinfo->filename, + buffer_p, + *buffer_bsize, + fpga_loadfs->offset); + if (ret < 0) { + debug("FPGA: Failed to read bitstream from flash.\n"); + return -ENOENT; + } + + /* Update next reading bitstream offset */ + fpga_loadfs->offset += *buffer_bsize; + + return 0; +} + +int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, + u32 offset) +{ + struct fpga_loadfs_info fpga_loadfs; + int status = 0; + int ret = 0; + u32 buffer = (u32)buf; + size_t buffer_sizebytes = bsize; + size_t buffer_sizebytes_ori = bsize; + size_t total_sizeof_image = 0; + struct udevice *dev; + + ret = uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &dev); + if (ret) + return ret; + + memset(&fpga_loadfs, 0, sizeof(fpga_loadfs)); + + fpga_loadfs.fpga_fsinfo = fpga_fsinfo; + fpga_loadfs.offset = offset; + + printf("FPGA: Checking FPGA configuration setting ...\n"); + + /* + * Note: Both buffer and buffer_sizebytes values can be altered by + * function below. + */ + ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer, + &buffer_sizebytes); + if (ret == 1) { + printf("FPGA: Skipping configuration ...\n"); + return 0; + } else if (ret) { + return ret; + } + + if (fpga_loadfs.rbfinfo.section == core_section && + !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) { + debug("FPGA : Must be in Early Release mode to program "); + debug("core bitstream.\n"); + return 0; + } + + /* Disable all signals from HPS peripheral controller to FPGA */ + writel(0, &system_manager_base->fpgaintf_en_global); + + /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */ + socfpga_bridges_reset(); + + if (fpga_loadfs.rbfinfo.section == periph_section) { + /* Initialize the FPGA Manager */ + status = fpgamgr_program_init((u32 *)buffer, buffer_sizebytes); + if (status) { + debug("FPGA: Init with peripheral bitstream failed.\n"); + return -EPERM; + } + } + + /* Transfer bitstream to FPGA Manager */ + fpgamgr_program_write((void *)buffer, buffer_sizebytes); + + total_sizeof_image += buffer_sizebytes; + + while (fpga_loadfs.remaining) { + ret = subsequent_loading_rbf_to_buffer(dev, + &fpga_loadfs, + &buffer, + &buffer_sizebytes_ori); + + if (ret) + return ret; + + /* Transfer data to FPGA Manager */ + fpgamgr_program_write((void *)buffer, + buffer_sizebytes_ori); + + total_sizeof_image += buffer_sizebytes_ori; + + WATCHDOG_RESET(); + } + + if (fpga_loadfs.rbfinfo.section == periph_section) { + if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) { + config_pins(gd->fdt_blob, "shared"); + puts("FPGA: Early Release Succeeded.\n"); + } else { + debug("FPGA: Failed to see Early Release.\n"); + return -EIO; + } + + /* For monolithic bitstream */ + if (is_fpgamgr_user_mode()) { + /* Ensure the FPGA entering config done */ + status = fpgamgr_program_finish(); + if (status) + return status; + + config_pins(gd->fdt_blob, "fpga"); + puts("FPGA: Enter user mode.\n"); + } + } else if (fpga_loadfs.rbfinfo.section == core_section) { + /* Ensure the FPGA entering config done */ + status = fpgamgr_program_finish(); + if (status) + return status; + + config_pins(gd->fdt_blob, "fpga"); + puts("FPGA: Enter user mode.\n"); + } else { + debug("FPGA: Config Error: Unsupported bitstream type.\n"); + return -ENOEXEC; + } + + return (int)total_sizeof_image; +} +#endif + +/* This function is used to load the core bitstream from the OCRAM. */ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) { - int status; + unsigned long status; + struct rbf_info rbfinfo; - /* disable all signals from hps peripheral controller to fpga */ + memset(&rbfinfo, 0, sizeof(rbfinfo)); + + /* Disable all signals from hps peripheral controller to fpga */ writel(0, &system_manager_base->fpgaintf_en_global); - /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ + /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(); - /* Initialize the FPGA Manager */ - status = fpgamgr_program_init((u32 *)rbf_data, rbf_size); - if (status) - return status; + /* Getting info about bitstream types */ + get_rbf_image_info(&rbfinfo, (u16 *)rbf_data); + + if (rbfinfo.section == periph_section) { + /* Initialize the FPGA Manager */ + status = fpgamgr_program_init((u32 *)rbf_data, rbf_size); + if (status) + return status; + } + + if (rbfinfo.section == core_section && + !(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) { + debug("FPGA : Must be in early release mode to program "); + debug("core bitstream.\n"); + return 0; + } - /* Write the RBF data to FPGA Manager */ + /* Write the bitstream to FPGA Manager */ fpgamgr_program_write(rbf_data, rbf_size); - return fpgamgr_program_finish(); + status = fpgamgr_program_finish(); + if (status) { + config_pins(gd->fdt_blob, "fpga"); + puts("FPGA: Enter user mode.\n"); + } + + return status; } From patchwork Wed Feb 13 14:18:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1041301 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4401tb0fMZz9s7T for ; Thu, 14 Feb 2019 01:21:58 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id AA7DFC21FF1; Wed, 13 Feb 2019 14:21:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1B00EC22093; Wed, 13 Feb 2019 14:19:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 67E49C21F98; Wed, 13 Feb 2019 14:19:08 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id 7557EC2201E for ; Wed, 13 Feb 2019 14:19:03 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2019 06:18:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,365,1544515200"; d="scan'208";a="114609804" Received: from pg-iccf0436.altera.com ([10.104.2.187]) by orsmga007.jf.intel.com with ESMTP; 13 Feb 2019 06:18:51 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 13 Feb 2019 22:18:35 +0800 Message-Id: <1550067518-2542-6-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> References: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH v8 5/8] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Update the default configuration file to enable the necessary functionality to get the SoCFPGA loadfs driver support. This would enable the implementation of programming bitstream into FPGA from MMC. Signed-off-by: Tien Fong Chee --- changes for v8 - Added FIT related configs changes for v7 - Removed limit set for CONFIG_FS_FAT_MAX_CLUSTSIZE --- configs/socfpga_arria10_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 0554f1b..c870543 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -27,10 +27,18 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" # CONFIG_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_DM_MMC=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_FS_FAT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_FS_LOADER=y CONFIG_FPGA_SOCFPGA=y +CONFIG_SPL_FIT=y +CONFIG_FIT=y CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_MMC=y From patchwork Wed Feb 13 14:18:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1041302 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4401v14n73z9s7T for ; Thu, 14 Feb 2019 01:22:21 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2292AC220A3; Wed, 13 Feb 2019 14:21:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C46A9C2209E; Wed, 13 Feb 2019 14:19:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8ECABC21FF4; Wed, 13 Feb 2019 14:19:09 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id 6B0CCC2209B for ; Wed, 13 Feb 2019 14:19:04 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2019 06:18:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,365,1544515200"; d="scan'208";a="114609812" Received: from pg-iccf0436.altera.com ([10.104.2.187]) by orsmga007.jf.intel.com with ESMTP; 13 Feb 2019 06:18:53 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 13 Feb 2019 22:18:36 +0800 Message-Id: <1550067518-2542-7-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> References: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH v8 6/8] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Add support for loading FPGA bitstream to get DDR up running before U-Boot is loaded into DDR. Boot device initialization, generic firmware loader and SPL FAT support are required for this whole mechanism to work. Signed-off-by: Tien Fong Chee --- changes for v7 - Removed casting for get_fpga_filename - Removed hard coding DDR address for loading core bistream, using loadable property from FIT. - Added checking for config_pins, return if error. --- arch/arm/mach-socfpga/spl_a10.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index c97eacb..36003b1 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2019 Altera Corporation */ #include @@ -23,6 +23,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -68,11 +70,48 @@ u32 spl_boot_mode(const u32 boot_device) void spl_board_init(void) { + char buf[16 * 1024] __aligned(ARCH_DMA_MINALIGN); + /* enable console uart printing */ preloader_console_init(); WATCHDOG_RESET(); arch_early_init_r(); + + /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ + if (is_fpgamgr_user_mode()) { + int ret = config_pins(gd->fdt_blob, "shared"); + + if (ret) + return; + + ret = config_pins(gd->fdt_blob, "fpga"); + if (ret) + return; + } else if (!is_fpgamgr_early_user_mode()) { + /* Program IOSSM(early IO release) or full FPGA */ + fpga_fs_info fpga_fsinfo; + int len; + + fpga_fsinfo.filename = get_fpga_filename(gd->fdt_blob, &len); + + if (fpga_fsinfo.filename) + socfpga_loadfs(&fpga_fsinfo, buf, sizeof(buf), 0); + } + + /* If the IOSSM/full FPGA is already loaded, start DDR */ + if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) + ddr_calibration_sequence(); + + if (!is_fpgamgr_user_mode()) { + fpga_fs_info fpga_fsinfo; + int len; + + fpga_fsinfo.filename = get_fpga_filename(gd->fdt_blob, &len); + + if (fpga_fsinfo.filename) + socfpga_loadfs(&fpga_fsinfo, buf, sizeof(buf), 0); + } } void board_init_f(ulong dummy) From patchwork Wed Feb 13 14:18:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1041298 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4401sj3XVgz9s5c for ; Thu, 14 Feb 2019 01:21:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1CB81C22072; Wed, 13 Feb 2019 14:20:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=RCVD_IN_DNSWL_HI, UPPERCASE_50_75 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0A94EC2202B; Wed, 13 Feb 2019 14:19:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 00496C21F98; Wed, 13 Feb 2019 14:19:10 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id 6A37AC220A7 for ; Wed, 13 Feb 2019 14:19:05 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2019 06:18:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,365,1544515200"; d="scan'208";a="114609820" Received: from pg-iccf0436.altera.com ([10.104.2.187]) by orsmga007.jf.intel.com with ESMTP; 13 Feb 2019 06:18:55 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 13 Feb 2019 22:18:37 +0800 Message-Id: <1550067518-2542-8-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> References: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH v8 7/8] ARM: socfpga: Synchronize the configuration for A10 SoCDK X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee Update the default configuration file to enable the necessary functionality the get the kit working. Signed-off-by: Tien Fong Chee --- changes for v8 - Moved the FIT related configs to the patch of configuration for FPGA SoCFPGA A10 SoCDK. changes for v7 - Keep minimal configs. --- configs/socfpga_arria10_defconfig | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index c870543..bdbf90e 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -10,10 +10,13 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200" # CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" +CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_FPGA_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set @@ -22,9 +25,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_ENV_IS_IN_MMC=y CONFIG_SPL_ENV_SUPPORT=y @@ -32,7 +33,6 @@ CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_DM_MMC=y CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_EXT_SUPPORT=y CONFIG_SPL_FS_FAT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_FS_LOADER=y @@ -43,11 +43,14 @@ CONFIG_DM_GPIO=y CONFIG_DWAPB_GPIO=y CONFIG_DM_MMC=y CONFIG_MTD_DEVICE=y +CONFIG_MMC_DW=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y -CONFIG_USE_TINY_PRINTF=y From patchwork Wed Feb 13 14:18:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chee, Tien Fong" X-Patchwork-Id: 1041300 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4401tK15Y1z9s5c for ; Thu, 14 Feb 2019 01:21:45 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D4466C2208E; Wed, 13 Feb 2019 14:20:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E2B37C21FEF; Wed, 13 Feb 2019 14:19:13 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0E3D7C2209A; Wed, 13 Feb 2019 14:19:10 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id AC426C2207B for ; Wed, 13 Feb 2019 14:19:05 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2019 06:18:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,365,1544515200"; d="scan'208";a="114609825" Received: from pg-iccf0436.altera.com ([10.104.2.187]) by orsmga007.jf.intel.com with ESMTP; 13 Feb 2019 06:18:58 -0800 From: tien.fong.chee@intel.com To: u-boot@lists.denx.de Date: Wed, 13 Feb 2019 22:18:38 +0800 Message-Id: <1550067518-2542-9-git-send-email-tien.fong.chee@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> References: <1550067518-2542-1-git-send-email-tien.fong.chee@intel.com> Cc: Marek Vasut , Tien Fong Chee , Ching Liang See , Westergteen Dalon Subject: [U-Boot] [PATCH v8 8/8] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tien Fong Chee After some series of patches to maximise reusable of memory pool, here come to result of reasonable size required for whole SDMMC boot working on A10 SoCDK. Size required come from default max cluster(0x10000) + others(0x2000) + additional memory for headroom(0x3000). Signed-off-by: Tien Fong Chee --- changes for v7 - Added 0x3000 for memory headroom. --- include/configs/socfpga_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4551cb2..548b458 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2012 Altera Corporation + * Copyright (C) 2012-2019 Altera Corporation */ #ifndef __CONFIG_SOCFPGA_COMMON_H__ #define __CONFIG_SOCFPGA_COMMON_H__ @@ -258,7 +258,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) /* SPL memory allocation configuration, this is for FAT implementation */ #ifndef CONFIG_SYS_SPL_MALLOC_START -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ CONFIG_SYS_SPL_MALLOC_SIZE + \ CONFIG_SYS_INIT_RAM_ADDR)