From patchwork Mon Feb 11 15:17:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 1039904 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-495824-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="h40MKNaD"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.b="hQxzZCzC"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43yqD01LDrz9sPV for ; Tue, 12 Feb 2019 02:17:51 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; q=dns; s=default; b=AIMI1DENxK2/xMJhVrXwAWtxPPxiZXqs3T3IiQVYPbgfQXUbp5 /q38zMKylIkUs6PvyqwqZHK4q8kjWTZbYyV3LI2RJKb0y/mlRoHbkhfEqFJvZMSZ Yjcytpqz3bqZyelcHz2+Vu1esOhXDSZj0qDvHepS9HUUW7fRTRQsdVFO4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; s= default; bh=u0mZiG+V0L7cu1cV663BtvWQjKA=; b=h40MKNaDlig4vHcVStbX 5Kh+C+oaRxEzTSegckHr2jdqjETRSuqoS4ZHVyag+j7F2sB8LTB81B6CVQ0EHPzU ayo6EM+TLpYEHbusu8ksVH+/qgbmWPZzi/RUcgosyc+9td62gDCLEy8tk6WBEZWJ RcCTGK99cJwRGSas0xWDOhg= Received: (qmail 50962 invoked by alias); 11 Feb 2019 15:17:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 50952 invoked by uid 89); 11 Feb 2019 15:17:44 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=H*c:HHH X-HELO: EUR04-DB3-obe.outbound.protection.outlook.com Received: from mail-eopbgr60045.outbound.protection.outlook.com (HELO EUR04-DB3-obe.outbound.protection.outlook.com) (40.107.6.45) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 11 Feb 2019 15:17:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=caXebq5Q0WDqQlAMx02XMtbnGkSnTg2U61M7u969DXc=; b=hQxzZCzCx1NqaplT+pZwtmw0dolNO3XtxUmUXBHTtX+eMwV/mvWTtEHTRRkM0viQvpEA6vv7ltEsxbSYU/mVTI6POJShgUdsBpK+tyNVEcyN075MZMqczI7SPpUMvgoP4opHZwEOYBo9C9Q7CfNQygDHgpqPDX7Kl0qx6BXNFyY= Received: from DB6PR0802MB2309.eurprd08.prod.outlook.com (10.172.228.13) by DB6PR0802MB2198.eurprd08.prod.outlook.com (10.172.227.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1601.17; Mon, 11 Feb 2019 15:17:40 +0000 Received: from DB6PR0802MB2309.eurprd08.prod.outlook.com ([fe80::190c:79a7:39c6:e6dd]) by DB6PR0802MB2309.eurprd08.prod.outlook.com ([fe80::190c:79a7:39c6:e6dd%5]) with mapi id 15.20.1601.023; Mon, 11 Feb 2019 15:17:40 +0000 From: Tamar Christina To: "gcc-patches@gcc.gnu.org" CC: nd , Ramana Radhakrishnan , Richard Earnshaw , "nickc@redhat.com" , Kyrylo Tkachov Subject: [PATCH][GCC][Arm] Update tests after register allocation changes. (PR/target 88560) Date: Mon, 11 Feb 2019 15:17:39 +0000 Message-ID: <20190211151736.GA14516@arm.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tamar.Christina@arm.com; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 MIME-Version: 1.0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-IsSubscribed: yes Hi all, After the register allocator changes of r268705 we need to update a few tests with new output. In all cases the compiler is now generating the expected code, since the tests are all float16 testcases using a hard-floar abi, we expect that actual fp16 instructions are used rather than using integer loads and stores. Because of we also save on some mov.f16s that were being emitted before to move between the two. The aapcs cases now match the f32 cases in using floating point operations. Regtested on arm-none-eabi and no issues. Ok for trunk? Thanks, Tamar 2019-02-11 Tamar Christina PR middle-end/88560 * gcc.target/arm/armv8_2-fp16-move-1.c: Update assembler scans. * gcc.target/arm/fp16-aapcs-1.c: Likewise. * gcc.target/arm/fp16-aapcs-3.c: Likewise. diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c index 56d87eb6f716718595dc6acdf0744b1d9ecf4a42..2321dd38cc6d7a3635f01180ad0f235b2a183ec2 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c @@ -16,7 +16,6 @@ test_load_2 (__fp16* a, int i) return a[i]; } -/* { dg-final { scan-assembler-times {vld1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 2 } } */ void test_store_1 (__fp16* a, __fp16 b) @@ -30,7 +29,6 @@ test_store_2 (__fp16* a, int i, __fp16 b) a[i] = b; } -/* { dg-final { scan-assembler-times {vst1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 2 } } */ __fp16 test_load_store_1 (__fp16* a, int i, __fp16* b) @@ -44,8 +42,9 @@ test_load_store_2 (__fp16* a, int i, __fp16* b) a[i] = b[i + 2]; return a[i]; } -/* { dg-final { scan-assembler-times {ldrh\tr[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {strh\tr[0-9]+} 2 } } */ + +/* { dg-final { scan-assembler-times {vst1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 3 } } */ +/* { dg-final { scan-assembler-times {vld1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 3 } } */ __fp16 test_select_1 (int sel, __fp16 a, __fp16 b) @@ -102,7 +101,7 @@ test_select_8 (__fp16 a, __fp16 b, __fp16 c) /* { dg-final { scan-assembler-times {vselgt\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */ /* { dg-final { scan-assembler-times {vselge\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */ -/* { dg-final { scan-assembler-times {vmov\.f16\ts[0-9]+, r[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmov\.f16} } } */ int test_compare_1 (__fp16 a, __fp16 b) diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c index b91168d43b389675909cabc1950c750c1c5dbf24..0a0a60f3503387f96eed881645aae031275d21ff 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c +++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c @@ -16,6 +16,7 @@ F (__fp16 a, __fp16 b, __fp16 c) return c; } -/* { dg-final { scan-assembler {vmov(\.f16)?\tr[0-9]+, s[0-9]+} } } */ -/* { dg-final { scan-assembler {vmov(\.f32)?\ts1, s0} } } */ -/* { dg-final { scan-assembler {vmov(\.f16)?\ts0, r[0-9]+} } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s1} } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts1, s0} } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s2+} } } */ +/* { dg-final { scan-assembler-times {vmov\.f32\ts0, s[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c index 84fc0a0f5f06b1714a70f4703213ca10ea0b268e..56a3ae2618432a408cd9b20f9e1334106efab98b 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c +++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c @@ -16,6 +16,8 @@ F (__fp16 a, __fp16 b, __fp16 c) return c; } -/* { dg-final { scan-assembler-times {vmov\tr[0-9]+, s[0-2]} 2 } } */ -/* { dg-final { scan-assembler-times {vmov.f32\ts1, s0} 1 } } */ -/* { dg-final { scan-assembler-times {vmov\ts0, r[0-9]+} 2 } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s1} } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts1, s0} } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s2+} } } */ +/* { dg-final { scan-assembler-times {vmov\.f32\ts0, s[0-9]+} 2 } } */ +