From patchwork Mon Feb 11 06:09:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hean-Loong, Ong" X-Patchwork-Id: 1039651 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43yb3b6v1Pz9s5c for ; Mon, 11 Feb 2019 17:09:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726074AbfBKGJm (ORCPT ); Mon, 11 Feb 2019 01:09:42 -0500 Received: from mga17.intel.com ([192.55.52.151]:57411 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725931AbfBKGJm (ORCPT ); Mon, 11 Feb 2019 01:09:42 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Feb 2019 22:09:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,358,1544515200"; d="scan'208";a="115217550" Received: from helong-vb.png.intel.com ([10.226.243.17]) by orsmga006.jf.intel.com with ESMTP; 10 Feb 2019 22:09:38 -0800 From: "Hean-Loong, Ong" To: Rob Herring , Dinh Nguyen , Daniel Vetter , =?utf-8?q?Noralf_Tr=C3=B8nne?= =?utf-8?q?s?= , Rienk de Jong Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, hean.loong.ong@intel.com, yves.vandervennet@intel.com, chin.liang.see@intel.com, Ong@vger.kernel.org Subject: [PATCHv12 1/3] ARM:dt-bindings:display Intel FPGA Video and Image Processing Suite Date: Mon, 11 Feb 2019 14:09:24 +0800 Message-Id: <20190211060926.3433-2-hean.loong.ong@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190211060926.3433-1-hean.loong.ong@intel.com> References: <20190211060926.3433-1-hean.loong.ong@intel.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ong, Hean Loong Device tree binding for Intel FPGA Video and Image Processing Suite. The bindings would set the max width, max height, bits per pixel and memory port width. The device tree binding only supports the Intel Arria10 devkit and its variants. Vendor name retained as altr. V12: Wrap comments and fix commit message V11: No change V10: No change V9: Remove Display port node V8: *Add port to Display port decoder V7: *Fix OF graph for better description *Add description for encoder V6: *Description have not describe DT device in general V5: *remove bindings for bits per symbol as it has only one value which is 8 V4: *fix properties that does not describe the values V3: *OF graph not in accordance to graph.txt V2: *Remove Linux driver description V1: *Missing vendor prefix Signed-off-by: Ong, Hean Loong --- .../devicetree/bindings/display/altr,vip-fb2.txt | 63 ++++++++++++++++++++ 1 files changed, 63 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/altr,vip-fb2.txt diff --git a/Documentation/devicetree/bindings/display/altr,vip-fb2.txt b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt new file mode 100644 index 0000000..89a3b9e --- /dev/null +++ b/Documentation/devicetree/bindings/display/altr,vip-fb2.txt @@ -0,0 +1,63 @@ +Intel Video and Image Processing(VIP) Frame Buffer II bindings + +Supported hardware: Intel FPGA SoC Arria10 and above with display port IP + +The Video Frame Buffer II in Video Image Processing (VIP) suite is an IP core +that interfaces between system memory and Avalon-ST video ports. The IP core +can be configured to support the memory reader (from memory to Avalon-ST) +and/or memory writer (from Avalon-ST to memory) interfaces. + +More information the FPGA video IP component can be acquired from +https://www.altera.com/content/dam/altera-www/global/en_US/pdfs\ +/literature/ug/ug_vip.pdf + +DT-Bindings: +============= +Required properties: +---------------------------- +- compatible: "altr,vip-frame-buffer-2.0" +- reg: Physical base address and length of the framebuffer controller's + registers. +- altr,max-width: The maximum width of the framebuffer in pixels. +- altr,max-height: The maximum height of the framebuffer in pixels. +- altr,mem-port-width = the bus width of the avalon master port + on the frame reader + +Optional sub-nodes: +- ports: The connection to the encoder + +Connections between the Frame Buffer II and other video IP cores in the system +are modelled using the OF graph DT bindings. The Frame Buffer II node has up +to two OF graph ports. When the memory writer interface is enabled, port 0 +maps to the Avalon-ST Input (din) port. When the memory reader interface is +enabled, port 1 maps to the Avalon-ST Output (dout) port. + +The encoder is built into the FPGA HW design and therefore would not +be accessible from the DDR. + + Port 0 Port1 +--------------------------------------------------------- +ARRIA10 AVALON_ST (DIN) AVALON_ST (DOUT) + +Required Properties Example: +---------------------------- + +framebuffer@100000280 { + compatible = "altr,vip-frame-buffer-2.0"; + reg = <0x00000001 0x00000280 0x00000040>; + altr,max-width = <1280>; + altr,max-height = <720>; + altr,mem-port-width = <128>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + fb_output: endpoint { + remote-endpoint = <&dp_encoder_input>; + }; + }; + }; +};