From patchwork Thu Feb 7 12:54:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kejia Hu X-Patchwork-Id: 1038049 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=codethink.co.uk Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43wJRQ4K1yz9s4Z for ; Fri, 8 Feb 2019 00:04:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726748AbfBGNEB (ORCPT ); Thu, 7 Feb 2019 08:04:01 -0500 Received: from imap1.codethink.co.uk ([176.9.8.82]:33039 "EHLO imap1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726990AbfBGND7 (ORCPT ); Thu, 7 Feb 2019 08:03:59 -0500 Received: from [167.98.27.226] (helo=devhw0) by imap1.codethink.co.uk with esmtpsa (Exim 4.84_2 #1 (Debian)) id 1grjLR-0008LK-QH; Thu, 07 Feb 2019 13:03:57 +0000 Received: from terry by devhw0 with local (Exim 4.89) (envelope-from ) id 1grjBx-0002IP-KQ; Thu, 07 Feb 2019 12:54:09 +0000 From: Kejia Hu To: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Ben Dooks , Thomas Preston , Kejia Hu Subject: [PATCH 1/5] soc/tegra: initial tegra-automotive detection Date: Thu, 7 Feb 2019 12:54:04 +0000 Message-Id: <20190207125408.8776-2-kejia.hu@codethink.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190207125408.8776-1-kejia.hu@codethink.co.uk> References: <20190207125408.8776-1-kejia.hu@codethink.co.uk> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Ben Dooks Add an initial soc_is_tegra_auto() with detection via a change in the device-tree. Also print the path taken through soc_is_tegra_auto() to allow debugging. Only print when debug is enabled as this function may be be called from multiple places, resulting in duplicated messages in production. Signed-off-by: Ben Dooks Signed-off-by: Thomas Preston Signed-off-by: Kejia Hu --- drivers/soc/tegra/common.c | 23 +++++++++++++++++++++++ drivers/soc/tegra/fuse/tegra-apbmisc.c | 2 ++ include/soc/tegra/common.h | 1 + include/soc/tegra/fuse.h | 1 + 4 files changed, 27 insertions(+) diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c index 7bfb154d6fa5..a10bd26fb5df 100644 --- a/drivers/soc/tegra/common.c +++ b/drivers/soc/tegra/common.c @@ -9,6 +9,7 @@ #include #include +#include static const struct of_device_id tegra_machine_match[] = { { .compatible = "nvidia,tegra20", }, @@ -34,3 +35,25 @@ bool soc_is_tegra(void) return match != NULL; } + +static const struct of_device_id tegra_machine_match_auto[] = { + { .compatible = "nvidia,tegra20auto", }, + { .compatible = "nvidia,tegra30auto", }, + { }, +}; + +bool soc_is_tegra_auto(void) +{ + struct device_node *root; + bool id_match = false; + + root = of_find_node_by_path("/"); + + if (root && of_match_node(tegra_machine_match_auto, root)) + id_match = true; + + pr_debug("%s of_device_id match %d, tegra_sku_info.is_automotive %d\n", + __func__, id_match, tegra_sku_info.is_automotive); + + return id_match || tegra_sku_info.is_automotive; +} diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index e5a4d8f98b10..b2727afad24b 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -110,6 +110,8 @@ void __init tegra_init_revision(void) tegra_sku_info.revision = rev; + tegra_sku_info.is_automotive = false; + tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO); } diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index fc13a9a134e9..8dd178ddc6a6 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -10,5 +10,6 @@ #define __SOC_TEGRA_COMMON_H__ bool soc_is_tegra(void); +bool soc_is_tegra_auto(void); #endif /* __SOC_TEGRA_COMMON_H__ */ diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index 8fb2f8a87339..ea4caf6f0cf7 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -56,6 +56,7 @@ struct tegra_sku_info { int gpu_speedo_id; int gpu_speedo_value; enum tegra_revision revision; + bool is_automotive; }; u32 tegra_read_straps(void); From patchwork Thu Feb 7 12:54:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kejia Hu X-Patchwork-Id: 1038048 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=codethink.co.uk Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43wJRP6VCfz9s4V for ; Fri, 8 Feb 2019 00:04:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727118AbfBGND7 (ORCPT ); Thu, 7 Feb 2019 08:03:59 -0500 Received: from imap1.codethink.co.uk ([176.9.8.82]:33031 "EHLO imap1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726748AbfBGND7 (ORCPT ); Thu, 7 Feb 2019 08:03:59 -0500 Received: from [167.98.27.226] (helo=devhw0) by imap1.codethink.co.uk with esmtpsa (Exim 4.84_2 #1 (Debian)) id 1grjLR-0008LA-Dw; Thu, 07 Feb 2019 13:03:57 +0000 Received: from terry by devhw0 with local (Exim 4.89) (envelope-from ) id 1grjBx-0002IR-Nu; Thu, 07 Feb 2019 12:54:09 +0000 From: Kejia Hu To: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Ben Dooks , Kejia Hu Subject: [PATCH 2/5] soc/tegra: add is_automotive to sku and for tegra30 Date: Thu, 7 Feb 2019 12:54:05 +0000 Message-Id: <20190207125408.8776-3-kejia.hu@codethink.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190207125408.8776-1-kejia.hu@codethink.co.uk> References: <20190207125408.8776-1-kejia.hu@codethink.co.uk> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Ben Dooks Add an is_automotive flag to the tegra-sku info, and add an implementation for the tegra30 from what we know from all the autotmotive parts we've seen. Signed-off-by: Ben Dooks Signed-off-by: Kejia Hu --- drivers/soc/tegra/fuse/fuse-tegra30.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index 257e254c6137..d92025e486e0 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -106,6 +106,10 @@ static void __init tegra30_fuse_init(struct tegra_fuse *fuse) if (fuse->soc->speedo_init) fuse->soc->speedo_init(&tegra_sku_info); + if (tegra_sku_info.revision == TEGRA_REVISION_A03 && + tegra_sku_info.sku_id == 176) + tegra_sku_info.is_automotive = true; + tegra30_fuse_add_randomness(); } #endif From patchwork Thu Feb 7 12:54:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kejia Hu X-Patchwork-Id: 1038051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=codethink.co.uk Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43wJRS0XcBz9s4V for ; Fri, 8 Feb 2019 00:04:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726994AbfBGNEB (ORCPT ); Thu, 7 Feb 2019 08:04:01 -0500 Received: from imap1.codethink.co.uk ([176.9.8.82]:33054 "EHLO imap1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726949AbfBGNEB (ORCPT ); Thu, 7 Feb 2019 08:04:01 -0500 Received: from [167.98.27.226] (helo=devhw0) by imap1.codethink.co.uk with esmtpsa (Exim 4.84_2 #1 (Debian)) id 1grjLS-0008Ln-HP; Thu, 07 Feb 2019 13:03:58 +0000 Received: from terry by devhw0 with local (Exim 4.89) (envelope-from ) id 1grjBx-0002IT-RP; Thu, 07 Feb 2019 12:54:09 +0000 From: Kejia Hu To: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Ben Dooks , Thomas Preston Subject: [PATCH 3/5] clk: tegra: add tegra30 automotive init Date: Thu, 7 Feb 2019 12:54:06 +0000 Message-Id: <20190207125408.8776-4-kejia.hu@codethink.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190207125408.8776-1-kejia.hu@codethink.co.uk> References: <20190207125408.8776-1-kejia.hu@codethink.co.uk> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Ben Dooks Add intialisation for the tegra30 automotive parts which have different initialisation requirements than the tegra30. These have been copied from the 2.6 BSP supplied by nvidia for these parts. Signed-off-by: Ben Dooks Signed-off-by: Thomas Preston --- drivers/clk/tegra/clk-tegra30.c | 83 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index fa8d573ac626..c483bdb562f6 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -22,6 +22,7 @@ #include #include +#include #include #include @@ -1278,9 +1279,89 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, }; +/* Tegra30 automotive part initialisation table. + * + * These values have been derived from the Nvidia supplied BSP for their + * automotive parts. + */ +static struct tegra_clk_init_table init_table_t30a[] __initdata = { + { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 1 }, + { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 1 }, + { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 }, + { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 1 }, + { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 }, + { TEGRA30_CLK_PLL_P_OUT1, TEGRA30_CLK_CLK_MAX, 9600000, 1 }, + { TEGRA30_CLK_PLL_P_OUT2, TEGRA30_CLK_CLK_MAX, 48000000, 1 }, + { TEGRA30_CLK_PLL_P_OUT3, TEGRA30_CLK_CLK_MAX, 102000000, 1 }, + { TEGRA30_CLK_PLL_P_OUT4, TEGRA30_CLK_CLK_MAX, 102000000, 1 }, + { TEGRA30_CLK_FUSE, TEGRA30_CLK_CLK_MAX, 12000000, 1 }, + { TEGRA30_CLK_KFUSE, TEGRA30_CLK_CLK_MAX, 12000000, 1 }, + { TEGRA30_CLK_CCLK_G, TEGRA30_CLK_CLK_MAX, 900000000, 0 }, + { TEGRA30_CLK_CCLK_LP,TEGRA30_CLK_CLK_MAX, 484000000, 0 }, + { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 552960000, 1 }, + { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 24576000, 1 }, + { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 24576000, 1 }, + { TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_CLK_M, 0, 0 }, + { TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_I2S0, TEGRA30_CLK_CLK_M, 12288000, 0 }, + { TEGRA30_CLK_I2S1, TEGRA30_CLK_CLK_M, 12288000, 0 }, + { TEGRA30_CLK_I2S2, TEGRA30_CLK_CLK_M, 12288000, 0 }, + { TEGRA30_CLK_I2S3, TEGRA30_CLK_CLK_M, 12288000, 0 }, + { TEGRA30_CLK_I2S4, TEGRA30_CLK_CLK_M, 12288000, 0 }, + { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 108000000, 0 }, + { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, + { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 }, + { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 104000000, 0 }, + { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 }, + { TEGRA30_CLK_SDMMC4, TEGRA30_CLK_PLL_P, 48000000, 0 }, + { TEGRA30_CLK_NOR, TEGRA30_CLK_PLL_P, 102000000, 0 }, + { TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_PLL_M_OUT1, TEGRA30_CLK_CLK_MAX, 312500000, 1 }, + { TEGRA30_CLK_SCLK, TEGRA30_CLK_PLL_M_OUT1, 312500000, 1 }, + { TEGRA30_CLK_HCLK, TEGRA30_CLK_CLK_MAX, 312500000, 1 }, + { TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 312500000/2, 1 }, + { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 484000000, 1 }, + /* initialse PLL_D and set it up before the display code for test */ + { TEGRA30_CLK_PLL_D, TEGRA30_CLK_CLK_MAX, 257800000, 1 }, + /* set EPP clock to TEGRA30_CLK_PLL_C */ + { TEGRA30_CLK_EPP, TEGRA30_CLK_PLL_C, 484000000, 0 }, + { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_M, 15822784, 1 }, + { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_M, 100000000, 1 }, + { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_M, 100000000, 1 }, + { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_M, 100000000, 1 }, + { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_M, 100000000, 1 }, + { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_M, 100000000, 1 }, + { TEGRA30_CLK_SE, TEGRA30_CLK_PLL_M, 625000000, 1 }, + { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 242000000, 0 }, + { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 275000000, 0 }, + { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 275000000, 0 }, + { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 }, + { TEGRA30_CLK_GR2D, TEGRA30_CLK_CLK_MAX, 484000000, 0 }, + { TEGRA30_CLK_GR3D, TEGRA30_CLK_CLK_MAX, 484000000, 0 }, + { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 484000000, 0 }, + { TEGRA30_CLK_D_AUDIO, TEGRA30_CLK_PLL_A_OUT0, 24576000, 0 }, + { TEGRA30_CLK_MPE, TEGRA30_CLK_PLL_C, 484000000, 0 }, + { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 484000000, 0 }, + { TEGRA30_CLK_VI, TEGRA30_CLK_PLL_P, 470000000, 0 }, + { TEGRA30_CLK_VI_SENSOR, TEGRA30_CLK_PLL_P, 150000000, 0 }, + { TEGRA30_CLK_PWM, TEGRA30_CLK_CLK_32K, 32768, 0 }, + { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, /* This MUST be the last entry. */ +}; + static void __init tegra30_clock_apply_init_table(void) { - tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX); + struct tegra_clk_init_table *table = init_table; + + if (soc_is_tegra_auto()) { + pr_info("Initialise Tegra Automotive clocks\n"); + table = init_table_t30a; + } + + tegra_init_from_table(table, clks, TEGRA30_CLK_CLK_MAX); } /* From patchwork Thu Feb 7 12:54:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kejia Hu X-Patchwork-Id: 1038047 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=codethink.co.uk Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43wJRP1CWxz9s9G for ; Fri, 8 Feb 2019 00:04:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727070AbfBGND7 (ORCPT ); Thu, 7 Feb 2019 08:03:59 -0500 Received: from imap1.codethink.co.uk ([176.9.8.82]:33024 "EHLO imap1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726843AbfBGND6 (ORCPT ); Thu, 7 Feb 2019 08:03:58 -0500 Received: from [167.98.27.226] (helo=devhw0) by imap1.codethink.co.uk with esmtpsa (Exim 4.84_2 #1 (Debian)) id 1grjLR-0008L6-1D; Thu, 07 Feb 2019 13:03:57 +0000 Received: from terry by devhw0 with local (Exim 4.89) (envelope-from ) id 1grjBx-0002IV-UW; Thu, 07 Feb 2019 12:54:09 +0000 From: Kejia Hu To: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Thomas Preston Subject: [PATCH 4/5] soc/tegra: add is_automotive for tegra20 Date: Thu, 7 Feb 2019 12:54:07 +0000 Message-Id: <20190207125408.8776-5-kejia.hu@codethink.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190207125408.8776-1-kejia.hu@codethink.co.uk> References: <20190207125408.8776-1-kejia.hu@codethink.co.uk> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thomas Preston Add an is_automotive implementation for tegra20. Signed-off-by: Thomas Preston --- drivers/soc/tegra/fuse/fuse-tegra20.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/soc/tegra/fuse/fuse-tegra20.c b/drivers/soc/tegra/fuse/fuse-tegra20.c index 49ff017f3ded..0184c9f62f80 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra20.c +++ b/drivers/soc/tegra/fuse/fuse-tegra20.c @@ -167,6 +167,11 @@ static void __init tegra20_fuse_init(struct tegra_fuse *fuse) tegra_init_revision(); fuse->soc->speedo_init(&tegra_sku_info); + + if (tegra_sku_info.revision == TEGRA_REVISION_A04 && + tegra_sku_info.sku_id == 44) + tegra_sku_info.is_automotive = true; + tegra20_fuse_add_randomness(); } From patchwork Thu Feb 7 12:54:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kejia Hu X-Patchwork-Id: 1038050 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=codethink.co.uk Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43wJRR2NSWz9s9G for ; Fri, 8 Feb 2019 00:04:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726990AbfBGNEB (ORCPT ); Thu, 7 Feb 2019 08:04:01 -0500 Received: from imap1.codethink.co.uk ([176.9.8.82]:33045 "EHLO imap1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727045AbfBGND7 (ORCPT ); Thu, 7 Feb 2019 08:03:59 -0500 Received: from [167.98.27.226] (helo=devhw0) by imap1.codethink.co.uk with esmtpsa (Exim 4.84_2 #1 (Debian)) id 1grjLS-0008LY-5n; Thu, 07 Feb 2019 13:03:58 +0000 Received: from terry by devhw0 with local (Exim 4.89) (envelope-from ) id 1grjBy-0002IX-1O; Thu, 07 Feb 2019 12:54:10 +0000 From: Kejia Hu To: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Thomas Preston , Kejia Hu Subject: [PATCH 5/5] clk: tegra: add tegra20 automotive init Date: Thu, 7 Feb 2019 12:54:08 +0000 Message-Id: <20190207125408.8776-6-kejia.hu@codethink.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190207125408.8776-1-kejia.hu@codethink.co.uk> References: <20190207125408.8776-1-kejia.hu@codethink.co.uk> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thomas Preston Add intialisation for the tegra20 automotive parts which have different initialisation requirements than the tegra20. These have been copied from the 2.6 BSP supplied by nvidia for these parts. Signed-off-by: Thomas Preston Signed-off-by: Kejia Hu --- drivers/clk/tegra/clk-tegra20.c | 78 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 76 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index c71b61162a32..1b8c7d40fd55 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "clk.h" #include "clk-id.h" @@ -534,7 +535,7 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true }, [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true }, [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true }, - [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true }, + [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = false }, [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true }, [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true }, [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true }, @@ -1091,9 +1092,82 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, }; +/* Tegra20 automotive part initialisation table. + * + * These values have been derived from the Nvidia supplied BSP for their + * automotive parts. + */ + +static struct tegra_clk_init_table init_table_t20a[] __initdata = { + {TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1}, + {TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1}, + {TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1}, + {TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1}, + {TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 240000000, 1}, + {TEGRA20_CLK_PLL_M, TEGRA20_CLK_CLK_MAX, 666000000, 1 }, + {TEGRA20_CLK_PLL_M_OUT1, TEGRA20_CLK_CLK_MAX, 266400000, 1 }, + {TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1}, + {TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 1}, + {TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1}, + {TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1}, + {TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 120000000, 1}, + {TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1}, + {TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1}, + {TEGRA20_CLK_PLL_D, TEGRA20_CLK_CLK_MAX, 594000000, 1}, + {TEGRA20_CLK_PLL_D_OUT0, TEGRA20_CLK_CLK_MAX, 594000000/2, 1}, + {TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1}, + {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0}, + {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 216000000, 1}, + {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0}, + {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0}, + {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0}, + {TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1}, + {TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1}, + {TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 0}, + {TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0}, + {TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0}, + {TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0}, + {TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0}, + {TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0}, + {TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0}, + {TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 86500000, 0}, + {TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_C, 12000000, 0}, + {TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_C, 12000000, 0}, + {TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_C, 12000000, 0}, + {TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_C, 12000000, 0}, + {TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_M, 266400000, 1}, + {TEGRA20_CLK_CSUS, TEGRA20_CLK_CLK_MAX, 12000000, 1}, + {TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_D_OUT0, 297000000, 1, }, /* disp1 from pll_d (no div) */ + {TEGRA20_CLK_GR2D, TEGRA20_CLK_CLK_MAX, 300000000, 1}, + {TEGRA20_CLK_GR3D, TEGRA20_CLK_CLK_MAX, 300000000, 1}, + {TEGRA20_CLK_VI, TEGRA20_CLK_PLL_M, 111000000, 1 }, + {TEGRA20_CLK_VI_SENSOR, TEGRA20_CLK_PLL_M, 111000000, 1 }, + {TEGRA20_CLK_I2C1, TEGRA20_CLK_PLL_P, 3000000, 0 }, + {TEGRA20_CLK_I2C2, TEGRA20_CLK_PLL_P, 3000000, 0 }, + {TEGRA20_CLK_I2C3, TEGRA20_CLK_PLL_P, 3000000, 0 }, + {TEGRA20_CLK_DVC, TEGRA20_CLK_PLL_P, 3000000, 0 }, + {TEGRA20_CLK_PWM, TEGRA20_CLK_CLK_32K, 32768, 0 }, + {TEGRA20_CLK_EPP, TEGRA20_CLK_PLL_M, 266400000, 1 }, + {TEGRA20_CLK_MPE, TEGRA20_CLK_PLL_C, 300000000, 1}, + {TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 86500000, 1 }, + {TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, + {TEGRA20_CLK_SPDIF_IN, TEGRA20_CLK_PLL_M, 22200000, 0 }, + {TEGRA20_CLK_SPDIF_OUT, TEGRA20_CLK_PLL_A_OUT0, 5644800, 0 }, + {TEGRA20_CLK_PLL_E, TEGRA20_CLK_CLK_MAX, 1200000000, 0 }, + {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */ +}; + + static void __init tegra20_clock_apply_init_table(void) { - tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX); + struct tegra_clk_init_table *table = init_table; + + if (soc_is_tegra_auto()) { + pr_info("Initialise Tegra Automotive clocks\n"); + table = init_table_t20a; + } + + tegra_init_from_table(table, clks, TEGRA20_CLK_CLK_MAX); } /*