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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 5 Feb 2019 20:14:18 -0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x15KEHkf26607710 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 5 Feb 2019 20:14:17 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 74AAD6A054; Tue, 5 Feb 2019 20:14:17 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 481CB6A04F; Tue, 5 Feb 2019 20:14:17 +0000 (GMT) Received: from [9.10.86.154] (unknown [9.10.86.154]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 5 Feb 2019 20:14:17 +0000 (GMT) To: GCC Patches , Segher Boessenkool From: Bill Seurer Subject: [PATCH, rs6000] Fix instruction counts on powerpc64 test cases. (take 2) Date: Tue, 5 Feb 2019 14:14:16 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 x-cbid: 19020520-0012-0000-0000-000017059A67 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010543; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000279; SDB=6.01156792; UDB=6.00603456; IPR=6.00937316; MB=3.00025448; MTD=3.00000008; XFM=3.00000015; UTC=2019-02-05 20:14:19 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19020520-0013-0000-0000-00005617DD4D Message-Id: <56758a78-ac0d-e385-1da6-f41db365f13b@linux.vnet.ibm.com> X-IsSubscribed: yes [PATCH, rs6000] Fix instruction counts on powerpc64 test cases. This patch fixes the assembler instruction counts for some test cases that started failing due to changes in code generation. The targets were adjusted a bit as well to avoid generating BE/LE endian code on unsupported platforms. Bootstrapped and tested on powerpc64le-unknown-linux-gnu (power 8 and power 9) and powerpc64be-unknown-linux-gnu (power 7 and power 8) with no regressions. Is this ok for trunk? 2019-02-04 Bill Seurer * gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c: Update instruction counts and target. * gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c: Update instruction counts and target. * gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c: Update instruction counts and target. Index: gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c (revision 268524) +++ gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c (working copy) @@ -1,28 +1,20 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-do compile { target { lp64 && be } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mvsx -O2 -mcpu=power7 -dp" } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ - /* Expected instruction counts for Power 7 */ /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ /* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be }} } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 5 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 9 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 9 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 6 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 7 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 6 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 7 { target be } } } */ +/* { dg-final { scan-assembler-times "xxlnor" 5 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpeqdp\s} 1 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpeqdp\.\s} 5 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgtdp\s} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgtdp\.\s} 5 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgedp\s} 1 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgedp\.\s} 6 } } */ /* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ /* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ /* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ Index: gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c (revision 268524) +++ gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c (working copy) @@ -1,16 +1,15 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-do compile { target { lp64 } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_vsx_ok } */ /* { dg-options "-mvsx -O2 -mcpu=power8" } */ /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ - /* Expected instruction counts for Power 8. */ /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ /* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */ +/* { dg-final { scan-assembler-times "xxlnor" 6 { target le } } } */ +/* { dg-final { scan-assembler-times "xxlnor" 5 { target be } } } */ /* We generate xxlor instructions for many reasons other than or'ing vector operands or calling __builtin_vec_or(), which means we cannot rely on @@ -18,16 +17,16 @@ xxlor instruction was generated. */ /* { dg-final { scan-assembler "xxlor" } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 4 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 4 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 7 { target le } } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpeqdp\s} 1 { target le } } } */ +/* { dg-final { scan-assembler-times {\mxvcmpeqdp\.\s} 5 { target le } } } */ +/* { dg-final { scan-assembler-times {\mxvcmpeqdp\s} 1 { target be } } } */ +/* { dg-final { scan-assembler-times {\mxvcmpeqdp\.\s} 5 { target be } } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgtdp\s} 2 { target le } } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgtdp\.\s} 6 { target le } } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgtdp\s} 2 { target be } } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgtdp\.\s} 6 { target be } } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgedp\s} 2 } } */ +/* { dg-final { scan-assembler-times {\mxvcmpgedp\.\s} 4 } } */ /* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ /* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ /* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ Index: gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c (revision 268524) +++ gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c (working copy) @@ -1,4 +1,4 @@ -/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-do compile { target { lp64 && le } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-options "-mvsx -O2 -mcpu=power9" } */ @@ -8,7 +8,7 @@ /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ /* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 5 } } */ /* We generate xxlor instructions for many reasons other than or'ing vector operands or calling __builtin_vec_or(), which means we cannot rely on