From patchwork Mon Feb 4 14:22:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 1035945 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Hf1hOuZU"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43tVM86G8Nz9sMp for ; Tue, 5 Feb 2019 01:24:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729071AbfBDOX5 (ORCPT ); Mon, 4 Feb 2019 09:23:57 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:42790 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728937AbfBDOX4 (ORCPT ); Mon, 4 Feb 2019 09:23:56 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x14EMxu3023115; Mon, 4 Feb 2019 08:22:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549290179; bh=IDKOkzngvCNd5neZHySPALtiWyrf9Lcw0FeR6NFiinU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Hf1hOuZUgU/8fmU0B6HJxUthZuH+Lm5FNtpt+Mofy7+au0IG0OIE/m5bPVs9nLmCn dHzFhnREIzMyWsqVUMaf6HBhAK54+2Gwzd8TSCXKmYJl64G2hIhVc0iaMWmnHJ3S+N 2ESaMC7KbgeP+WWeom8zVGd0C56AIKRXCyRU9gj0= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x14EMxu8009717 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 4 Feb 2019 08:22:59 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 4 Feb 2019 08:22:58 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 4 Feb 2019 08:22:58 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x14EMoKZ012232; Mon, 4 Feb 2019 08:22:55 -0600 From: Roger Quadros To: , , CC: , , , , , , , , , , , , Subject: [PATCH v2 01/14] dt-bindings: remoteproc: Add TI PRUSS bindings Date: Mon, 4 Feb 2019 16:22:34 +0200 Message-ID: <1549290167-876-2-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549290167-876-1-git-send-email-rogerq@ti.com> References: <1549290167-876-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna This patch adds the bindings for the Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) present on various SoCs such as AM33xx, AM437x, AM57xx, Keystone 66AK2G SoC, etc. It is present on the Davinci based OMAPL138 SoCs and K3 architecture based AM65x SoCs as well (not covered for now). Signed-off-by: Suman Anna Signed-off-by: Roger Quadros --- .../devicetree/bindings/soc/ti/ti,pruss.txt | 212 +++++++++++++++++++++ 1 file changed, 212 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/ti,pruss.txt diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.txt b/Documentation/devicetree/bindings/soc/ti/ti,pruss.txt new file mode 100644 index 0000000..5ac76fd --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.txt @@ -0,0 +1,212 @@ +PRU-ICSS on TI SoCs +=================== + +The Programmable Real-Time Unit and Industrial Communication Subsystem +(PRU-ICSS) is present on various TI SoCs such as AM335x, AM437x, Keystone +66AK2G, etc. A PRUSS consists of dual 32-bit RISC cores (Programmable +Real-Time Units, or PRUs) with program memory and data memory. + +The programmable nature of the PRUs provide flexibility to implement +custom peripheral interfaces, fast real-time responses, or specialized +data handling. The common peripheral modules include the following, + + - Enhanced GPIO with async capture and serial support + - an Ethernet MII_RT module with two MII ports + - an MDIO port to control external Ethernet PHYs + - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial + Ethernet functions + - an Enhanced Capture Module (eCAP) + - a 16550-compatible UART to support PROFIBUS + - Interrupt controller with 64 input events and 10 Host interrupts. + +A shared Data RAM, if present, can be accessed by both the PRU cores. The +Interrupt Controller (INTC) and a CFG module are common to both the PRU +cores. + +Various sub-modules within a PRU-ICSS subsystem are represented as individual +nodes. + +PRUSS Node +============= + +This node represents the entire ICSS instance and the various modules are +contained as children. The PRUSS driver is responsible for managing the +common resources i.e. DRAM0, DRAM1, SHARED_RAM and CFG space. + +Required Properties: +-------------------- +- compatible : should be one of, + "ti,am3356-pruss" for AM335x family of SoCs + "ti,am4376-pruss" for AM437x family of SoCs + "ti,am5728-pruss" for AM57xx family of SoCs + "ti,k2g-pruss" for 66AK2G family of SoCs +- reg : base address and size for each of the Data RAMs as + mentioned in reg-names, and in the same order as the + reg-names +- reg-names : should contain a string(s) from among the following names, + each representing a specific Data RAM region. Some PRU-ICSS + instances on certain SoCs might not have Shared DRAM. + "dram0" for Data RAM0, + "dram1" for Data RAM1, + "shrdram2" for Shared Data RAM, +- #address-cells : should be 1 +- #size-cells : should be 1 +- ranges : no specific range translations required, child nodes have the + same address view as the parent, so should be mentioned without + any value for the property + +Optional Properties: +-------------------- +- no-shared-ram : Should be present if the instance doesn't have Shared RAM. + e.g. AM4376 ICSS0 instance doesn't have Shared RAM. + +The PRUSS node will have one or more of the folowing child nodes. + +PRU CORES +========= +ICSS typically has 2 PRU cores. These should be represented as remoteproc devices. + +INTC node +========= +ICSS has one INTC interrupt controller module. This should be represented as +a standard interrupt-controller node. + +CFG, IEP, MII_RT +================ +The individual sub-modules CFG, IEP and MII_RT are represented as a syscon +node each with specific node names as below: + "cfg" for CFG sub-module, + "iep" for IEP sub-module, + "mii_rt" for MII-RT sub-module, + +See Documentation/devicetree/bindings/mfd/syscon.txt for details. + +MDIO +==== +Each PRUSS has an MDIO module that can be used to control external PHYs. The +MDIO module used within the PRU-ICSS is an instance of the MDIO Controller +used in TI Davinci SoCs. Please refer to the corresponding binding document, +Documentation/devicetree/bindings/net/davinci-mdio.txt for details. + +Application/User Nodes +======================= +A PRU application/user node typically uses one or more PRU device nodes to +implement a PRU application/functionality. Each application/client node would +need a reference to at least a PRU node, and optionally pass some configuration +parameters. + +Required Properties: +-------------------- +- prus : phandles to the PRU nodes used + +Optional Properties: +-------------------- +- firmware-name : firmwares for the PRU cores, the default firmware + for the core from the PRU node will be used if not + provided. The firmware names should correspond to + the PRU cores listed in the 'prus' property +- ti,pruss-gp-mux-sel : array of values for the GP_MUX_SEL under PRUSS_GPCFG + register for a PRU. This selects the internal muxing + scheme for the PRU instance. If not provided, the + default out-of-reset value (0) for the PRU core is + used. Values should correspond to the PRU cores listed + in the 'prus' property +- ti,pru-interrupt-map : PRU interrupt mappings, containing an array of entries + with each entry consisting of 4 cell-values. First one + is an index towards the "prus" property to identify the + PRU core for the interrupt map, second is the PRU + System Event id, third is the PRU interrupt channel id + and fourth is the PRU host interrupt id. If provided, + this map will supercede any other configuration + provided through firmware + +Example: +======== +1. /* AM33xx PRU-ICSS */ + + pruss: pruss@0 { + compatible = "ti,am3356-pruss"; + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x3000>; + reg-names = "dram0", "dram1", + "shrdram2"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pruss_cfg: cfg@26000 { + compatible = "syscon"; + reg = <0x26000 0x2000>; + }; + + pruss_iep: iep@2e000 { + compatible = "syscon"; + reg = <0x2e000 0x31c>; + }; + + pruss_mii_rt: mii_rt@32000 { + compatible = "syscon"; + reg = <0x32000 0x58>; + }; + + pruss_intc: intc@20000 { + compatible = "ti,am3356-pruss-intc"; + reg = <0x20000 0x2000>; + reg-names = "intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host2", "host3", "host4", + "host5", "host6", "host7", + "host8", "host9"; + }; + + pru0: pru@34000 { + compatible = "ti,am3356-pru"; + reg = <0x34000 0x2000>, + <0x22000 0x400>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + gpcfg = <&pruss_cfg 0x8>; + firmware-name = "am335x-pru0-fw"; + interrupt-parent = <&pruss_intc>; + interrupts = <16>, <17>; + interrupt-names = "vring", "kick"; + }; + + pru1: pru@38000 { + compatible = "ti,am3356-pru"; + reg = <0x38000 0x2000>, + <0x24000 0x400>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + gpcfg = <&pruss_cfg 0xc>; + firmware-name = "am335x-pru1-fw"; + interrupt-parent = <&pruss_intc>; + interrupts = <18>, <19>; + interrupt-names = "vring", "kick"; + }; + + pruss_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x90>; + clocks = <&dpll_core_m4_ck>; + clock-names = "fck"; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + +2: /* PRU application node example */ + app_node: app_node { + prus = <&pru0>, <&pru1>; + firmware-name = "pruss-app-fw", "pruss-app-fw-2"; + ti,pruss-gp-mux-sel = <2>, <1>; + /* setup interrupts for prus: + prus[0] => pru1_0: ev=16, chnl=2, host-irq=7, + prus[1] => pru1_1: ev=19, chnl=1, host-irq=3 */ + ti,pru-interrupt-map = <0 16 2 7 >, <1 19 1 3>; + } From patchwork Mon Feb 4 14:22:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 1035947 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="VEXJ/ypB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43tVNV3rHKz9sN6 for ; Tue, 5 Feb 2019 01:25:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729783AbfBDOYY (ORCPT ); Mon, 4 Feb 2019 09:24:24 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43232 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728861AbfBDOYY (ORCPT ); Mon, 4 Feb 2019 09:24:24 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x14EN8rd031778; Mon, 4 Feb 2019 08:23:08 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549290188; bh=BybUACh2KOzPXi9WzljjTKIRZASeNQ0xo78WVaTHwO4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VEXJ/ypBN5PdLeyHE9uxiTLiFoo+dlDmCQ07qTTWIz8Z0YnwBUGkeiRRZ85PrQGej dsEQ1zgAr/HbDW3kaEPigXZBFacP1UfBSE86TkfvQMQ7PncJlBkAVKcFZCL5LCmvXL FpRgj4gXQtOYOv9zNwXvpFV2IKpfvYXpJ+U72kOk= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x14EN8df010126 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 4 Feb 2019 08:23:08 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 4 Feb 2019 08:23:07 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 4 Feb 2019 08:23:07 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x14EMoKb012232; Mon, 4 Feb 2019 08:23:03 -0600 From: Roger Quadros To: , , CC: , , , , , , , , , , , , , "Andrew F. Davis" , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring Subject: [PATCH v2 03/14] dt-binding: irqchip: Add pruss-intc-irq driver for PRUSS interrupts Date: Mon, 4 Feb 2019 16:22:36 +0200 Message-ID: <1549290167-876-4-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549290167-876-1-git-send-email-rogerq@ti.com> References: <1549290167-876-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: "Andrew F. Davis" The Programmable Real-Time Unit Subsystem (PRUSS) contains an interrupt controller (INTC) that can handle various system input events and post interrupts back to the device-level initiators. The INTC can support upto 64 input events with individual control configuration and hardware prioritization. These events are mapped onto 10 interrupt signals through two levels of many-to-one mapping support. Different interrupt signals are routed to the individual PRU cores or to the host CPU. The PRUSS INTC platform driver manages this PRUSS interrupt controller and implements an irqchip driver to provide a Linux standard way for the PRU client users to enable/disable/ack/ re-trigger a PRUSS system event. The system events to interrupt channels and host interrupts relies on the mapping configuration provided through a firmware resource table for now. This will be revisited and enhanced in the future for a better interface. The mappings will currently be programmed during the boot/shutdown of the PRU. Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Cc: Rob Herring Signed-off-by: Andrew F. Davis Signed-off-by: Roger Quadros Acked-by: Tony Lindgren --- .../interrupt-controller/ti,pruss-intc-irq.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc-irq.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc-irq.txt new file mode 100644 index 0000000..c70221c --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc-irq.txt @@ -0,0 +1,51 @@ +PRU ICSS INTC on TI SoCs +======================== + +Each PRUSS has a single interrupt controller instance that is common to both +the PRU cores. Each interrupt controller can detect 64 input events which are +then mapped to 10 possible output interrupts through two levels of mapping. The +input events can be triggered by either the PRUs and/or various other PRUSS +internal and external peripherals. The first 2 output interrupts are fed +exclusively to the internal PRU cores, with the remaining 8 connected to +external interrupt controllers including the MPU. + +Required Properties: +-------------------- +- compatible : should be one of, + "ti,am3356-pruss-intc" for AM335x family of SoCs + "ti,am4376-pruss-intc" for AM437x family of SoCs + "ti,am5728-pruss-intc" for AM57xx family of SoCs + "ti,k2g-pruss-intc" for 66AK2G family of SoCs +- reg : base address and size for the PRUSS INTC sub-module +- reg-names : should contain the string "intc" +- interrupts : all the interrupts generated towards the main host + processor in the SoC. The format depends on the + interrupt specifier for the particular SoC's MPU + parent interrupt controller +- interrupt-names: should use one of the following names for each interrupt, + the name should match the corresponding host interrupt + number, + "host2", "host3", "host4", "host5", "host6", + "host7", "host8" or "host9" + NOTE: AM437x and 66AK2G SoCs do not have "host7" interrupt + connected to MPU +- interrupt-controller : mark this node as an interrupt controller +- #interrupt-cells : should be 1. Client users shall use the PRU System + event number (the interrupt source that the client + is interested in) as the value of the interrupts + property in their node + +Example: +-------- + pruss_intc: intc@20000 { + compatible = "ti,am3356-pruss-intc"; + reg = <0x20000 0x2000>; + reg-names = "intc"; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host2", "host3", "host4", + "host5", "host6", "host7", + "host8", "host9"; + }; + From patchwork Mon Feb 4 14:22:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 1035946 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="EKro2kHF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43tVNS2gZcz9sMr for ; Tue, 5 Feb 2019 01:25:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729827AbfBDOYZ (ORCPT ); Mon, 4 Feb 2019 09:24:25 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:49884 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728937AbfBDOYY (ORCPT ); Mon, 4 Feb 2019 09:24:24 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x14ENWPV044048; Mon, 4 Feb 2019 08:23:32 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549290212; bh=wKcx2dLXaiJQ7mZWX/QUVBP1grt4i6qXcUpv+wF4XR0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EKro2kHFLLMt7Q5UZ/AAo9kFbgyf4Kn7V0IqKvKk6z+gm6HIh0IxjUVWwEzKm1rwh L9C6NFznxLL+0BAbAOe1Iv40aTBtrN2Zyix2UIZddoVmk6a8Ti7nhGx9zItgBUwvtd ESfykc6bljD64rZRd0fNEfoq4M9Iz+U+jaAPBRP4= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x14ENVTw048975 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 4 Feb 2019 08:23:31 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 4 Feb 2019 08:23:31 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 4 Feb 2019 08:23:31 -0600 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x14EMoKh012232; Mon, 4 Feb 2019 08:23:27 -0600 From: Roger Quadros To: , , CC: , , , , , , , , , , , , , Rob Herring Subject: [PATCH v2 09/14] dt-binding: remoteproc: Add binding doc for PRU Cores in the PRU-ICSS Date: Mon, 4 Feb 2019 16:22:42 +0200 Message-ID: <1549290167-876-10-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549290167-876-1-git-send-email-rogerq@ti.com> References: <1549290167-876-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Suman Anna The Programmable Real-Time Unit Subsystem (PRUSS) consists of dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs) for program execution. This patch adds a remoteproc platform driver for managing the individual PRU RISC cores life cycle. Add DT binding documentation for that. Cc: Rob Herring Signed-off-by: Suman Anna Signed-off-by: Roger Quadros Reviewed-by: Rob Herring --- .../bindings/remoteproc/ti,pru-rproc.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.txt diff --git a/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.txt b/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.txt new file mode 100644 index 0000000..02dfd0e --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/ti,pru-rproc.txt @@ -0,0 +1,56 @@ +PRU Core on TI SoCs +=================== + +Each PRUSS has dual PRU cores, each represented by a PRU child node. Each node +can optionally be rendered inactive by using the standard DT string property, +"status". + +Required Properties: +-------------------- +- compatible : should be + "ti,am3356-pru" for AM335x family of SoCs + "ti,am4376-pru" for AM437x family of SoCs + "ti,am5728-pru" for AM57xx family of SoCs + "ti,k2g-pru" for 66AK2G family of SoCs +- reg : base address and size for each of the 3 sub-module address + spaces as mentioned in reg-names, and in the same order as + the reg-names +- reg-names : should contain each of the following 3 names, the binding is + agnostic of the order of these reg-names + "iram" for Instruction RAM, + "control" for the CTRL sub-module registers, + "debug" for the Debug sub-module registers, + +- firmware-name : should contain the name of the firmware image file + located on the firmware search path. This firmware will be + used as default if the Application node or User (via sysfs) + doesn't provide a firmware-name. + +- gpcfg : pHandle to CFG module's syscon regmap and offset to PRU's + GPCFG register. + +Optional Properties: +-------------------- +The virtio based communication between the MPU and a PRU core _requires_ +either the 'mboxes' property, or the set of 'interrupt-parent', 'interrupts' +and 'interrupt-names' properties to be defined. The latter option is the +preferred choice. The 'mboxes' property is not applicable for 66AK2G and +DA850/OMAP-L138 SoCs. + +- mboxes : OMAP Mailbox specifier denoting the sub-mailbox, if using + a mailbox for IPC signalling between host and a PRU core. + The specifier format is as per the bindings, + Documentation/devicetree/bindings/mailbox/omap-mailbox.txt + This property should match with the sub-mailbox node used + in the corresponding firmware image. +- interrupt-parent : phandle to the PRUSS INTC node. Should be defined if + interrupts property is to be used. +- interrupts : array of interrupt specifiers if using PRU system events + for IPC signalling between host and a PRU core. This + property should match with the PRU system event used in + the corresponding firmware image. +- interrupt-names : should use one of the following names for each interrupt, + the name should match the corresponding PRU system event + number, + "vring" - for PRU to HOST virtqueue signalling + "kick" - for HOST to PRU virtqueue signalling