From patchwork Sun Feb 3 21:41:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1035649 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="aQVx4c9v"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43t47l0X5Dz9sDX for ; Mon, 4 Feb 2019 08:42:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727740AbfBCVml (ORCPT ); Sun, 3 Feb 2019 16:42:41 -0500 Received: from mail-lj1-f195.google.com ([209.85.208.195]:43308 "EHLO mail-lj1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727502AbfBCVml (ORCPT ); Sun, 3 Feb 2019 16:42:41 -0500 Received: by mail-lj1-f195.google.com with SMTP id q2-v6so10004782lji.10 for ; Sun, 03 Feb 2019 13:42:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B7FFvSbFEdEOlGQG13PaDC6yVK3bQrkjP/q2THoicDo=; b=aQVx4c9vEytpnRkyN0VA2Oqd/uApzi25mROXs5WT1n80W8TA5A4wUaeiK/ZFG9vmbL aTvi3txYKuvN6IpzGE/AIx49yHigNE5OsEZC0e2Gs1zvCwUEt+I/Fl/buYoQqA2WftWg QnF0AMR+tXRzgP4y9gH8YD9xXNNUnkLcxGL3Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B7FFvSbFEdEOlGQG13PaDC6yVK3bQrkjP/q2THoicDo=; b=ioosBNuhc1V3vMbalC9rWiOryz9ebnNEtLRSu+04lz4nujzRQ0R5+TmoyQM3PRM1Wr ovCzx6SVlqiaC8AhHFX7VypnqA6gHRa4w3T59doTDzILO3hqpbfCTfVBevF1FyxHlkLX 3V5LPHm2cQt0DKMb6GTmXFOpBamf8cAMf2DpHTQ/1AuzGuegD7OiUt0qru5OEtrTsIgj s9Cs4+EbHyWyN4lvd8o7BnlU+/lDtxRRKpQEsXIZo0XakQfmg4P5HnM1JOCKBuDrqCFw kFlDx2/7pAg8O6R1RjBXFlCHypOFmqr5+6xTjzzK3S4Lh9zX2oxSlXnp89I8ubJY7X2o jsNg== X-Gm-Message-State: AHQUAuZNgIlylPPYAv7Wmw4CpN8OhfMCP2aAPinTOyf+4d+oz7PqaqUJ 2XeRKUzK4dRUwoE7RAwWnChndQ== X-Google-Smtp-Source: AHgI3Ia6k0xS4ZYGOPNAbm/YdU9Y5/CErJo3uLVPqSxE7ue3hUtGLGWsFoO28XKXEVp+LcJ6UDaRjA== X-Received: by 2002:a2e:744:: with SMTP id i4-v6mr14861923ljd.140.1549230159428; Sun, 03 Feb 2019 13:42:39 -0800 (PST) Received: from linux.local (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id 85-v6sm2456868lja.16.2019.02.03.13.42.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 13:42:38 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Tim Harvey , Arnd Bergmann , Olof Johansson , Linus Walleij , Marc Zyngier , Jason Cooper , Thomas Gleixner , devicetree@vger.kernel.org Subject: [PATCH 09/17 v1] irqchip: ixp4xx: Add DT bindings Date: Sun, 3 Feb 2019 22:41:57 +0100 Message-Id: <20190203214205.13594-10-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190203214205.13594-1-linus.walleij@linaro.org> References: <20190203214205.13594-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the IXP4xx interrupt controller. It's a standard 2-cell controller. Cc: Marc Zyngier Cc: Jason Cooper Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Reviewed-by: Rob Herring --- irqchip maintainers: I am requesting an ACK for this once you're happy with the bindings, as I intend to merge all of this IXP4xx rework through ARM SoC. --- .../intel,ixp4xx-interrupt.txt | 33 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt new file mode 100644 index 000000000000..70ee93b9a6c0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt @@ -0,0 +1,33 @@ +* Intel IXP4xx XScale Networking Processors Interrupt Controller + +This interrupt controller is found in the Intel IXP4xx processors. +Some processors have 32 interrupts, some have up to 64 interrupts. +The exact number of interrupts is determined from the compatible +string. + +The distinct IXP4xx families with different interrupt controller +variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four +families were the only ones to reach the developer and consumer +market. + +Required properties: +- compatible: must be one of + "intel,ixp42x-interrupt" + "intel,ixp43x-interrupt" + "intel,ixp45x-interrupt" + "intel,ixp46x-interrupt" +- reg: The register bank for the interrupt controller. +- interrupt-controller: Identifies the node as an interrupt controller +- #interrupt-cells: The number of cells to define the interrupts. + Must be <2>. The bindings follows the standard binding for controllers + with two cells specified in + interrupt-controller/interrupts.txt + +Example: + +intcon: interrupt-controller@c8003000 { + compatible = "intel,ixp43x-interrupt"; + reg = <0xc8003000 0x100>; + interrupt-controller; + #interrupt-cells = <2>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index a2fb67b75026..ec318f09540c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1650,6 +1650,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt F: arch/arm/mach-ixp4xx/ F: drivers/clocksource/timer-ixp4xx.c F: drivers/gpio/gpio-ixp4xx.c From patchwork Sun Feb 3 21:41:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1035650 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="YNWH1F0b"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43t47q1GGvz9sLw for ; Mon, 4 Feb 2019 08:42:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727761AbfBCVmq (ORCPT ); Sun, 3 Feb 2019 16:42:46 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:36823 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727502AbfBCVmq (ORCPT ); Sun, 3 Feb 2019 16:42:46 -0500 Received: by mail-lj1-f196.google.com with SMTP id g11-v6so10077929ljk.3 for ; Sun, 03 Feb 2019 13:42:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rXBAcdvBpxh0mmOpvAIaV+ZEaPAyDpVqFL3/7RiGnT0=; b=YNWH1F0bcerghQOEpAwFgtOBt1qpM5u5Z7oqz+QoZxPZYmg//ZiU2rWWecsG7MIU9t n9bQvNl/7g0CcOC6HoARONV3u6ik+F0xgvBixGudRjV9mheQumhDtvmf+warvbiU7X3m qoHz6vulssWSb3DuNMGHJpeVdgpFcX8vg07I4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rXBAcdvBpxh0mmOpvAIaV+ZEaPAyDpVqFL3/7RiGnT0=; b=XCldHBJQ7i/moN4fyHSzi0Zvq5n3VY63IMvD58cqHdcYpUQwow+6uGZ4W8t3eteZR0 5L28LSHM38twrXqvhPheGfPu+bIZQH+41WGmc5B3mbyz0sKetbMT/65x5rsvAmU+a/HB hnOvkVue1AdejrEecwva8IzzEIjI+VEYP+Q8FzIKsNg2O1Gdw+9KGjCn03ug+DOZCg// J96iDn+R3tahAkROot/UoPTR8EbUdgaM2vqcxuk8SvsxJmyApCg2lP8GuPHTT+YRTpf/ MgeeLDHW1piXq4ILdO8LsUCFz5vuCWxE1j0crYqgwPbVNDxfQ5H0SZXrD+ukom4IVpMk 07dQ== X-Gm-Message-State: AJcUukfkt/Ug++iJDzSguN5wtJdUy8n16U9pZacPF7e6LOrODwNRw28s g5r98wmijOiVRZmh1yzBAT08tw== X-Google-Smtp-Source: ALg8bN6oKqai3hIVgB7Fw+5r/Nxbc12aOemB0+pV+eO2Yw7f6yCtBdw+UGBz3ATXOPAzschIYDuNwQ== X-Received: by 2002:a2e:568d:: with SMTP id k13-v6mr40431229lje.105.1549230164446; Sun, 03 Feb 2019 13:42:44 -0800 (PST) Received: from linux.local (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id 85-v6sm2456868lja.16.2019.02.03.13.42.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 13:42:43 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Tim Harvey , Arnd Bergmann , Olof Johansson , Linus Walleij , Daniel Lezcano , Thomas Gleixner , devicetree@vger.kernel.org Subject: [PATCH 11/17 v1] clocksource/drivers/ixp4xx: Add DT bindings Date: Sun, 3 Feb 2019 22:41:59 +0100 Message-Id: <20190203214205.13594-12-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190203214205.13594-1-linus.walleij@linaro.org> References: <20190203214205.13594-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds device tree bindings for the Intel IXP4xx timers. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Reviewed-by: Rob Herring Acked-by: Daniel Lezcano --- Clocksource/timer maintainers: I am requesting an ACK for this once you're happy with the bindings, as I intend to merge all of this IXP4xx rework through ARM SoC. --- .../bindings/timer/intel,ixp4xx-timer.txt | 18 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt diff --git a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt new file mode 100644 index 000000000000..5b93477bb6ed --- /dev/null +++ b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt @@ -0,0 +1,18 @@ +Intel IXP4xx XScale Networking Processors Timers + +This timer is found in the Intel IXP4xx processors. + +Required properties: + +- compatible : Must be + "intel,ixp4xx-timer" +- reg : Should contain registers location and length +- interrupts : Should contain the two timer interrupts + +Example: + +timer@c8005000 { + compatible = "intel,ixp4xx-timer"; + reg = <0xc8005000 0x100>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index ec318f09540c..775a623dc91d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1651,6 +1651,7 @@ M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt +F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt F: arch/arm/mach-ixp4xx/ F: drivers/clocksource/timer-ixp4xx.c F: drivers/gpio/gpio-ixp4xx.c From patchwork Sun Feb 3 21:42:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1035651 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="IJwvs9MO"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43t47v1JQ3z9sDr for ; Mon, 4 Feb 2019 08:42:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727763AbfBCVmu (ORCPT ); Sun, 3 Feb 2019 16:42:50 -0500 Received: from mail-lj1-f196.google.com ([209.85.208.196]:33215 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727502AbfBCVmu (ORCPT ); Sun, 3 Feb 2019 16:42:50 -0500 Received: by mail-lj1-f196.google.com with SMTP id v1-v6so10080215ljd.0 for ; Sun, 03 Feb 2019 13:42:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tqkowpPvCE0gZkM+u8f2imx7BQRKOcq+GoRfFNueR54=; b=IJwvs9MOeRugN+kldoyML1h6U8pW/u5JfJB+FpKNU2ADfqbW0n4jBoiSTLsuZaaiCq fzSET1TqL26gc9Nm8nB/Qg3wnSuRXW8bp0y7MR35uLlkBwpXvVVnJ1ulUlX10fnVifxm MkuCnHz/yR9EsH/sV3TqEqmUxVxhdeQT3IODk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tqkowpPvCE0gZkM+u8f2imx7BQRKOcq+GoRfFNueR54=; b=r9OAYG0ryBNU1Lv+vEbHK93kyyvIiJvaZaZnR4oeUO4t2d4rzV6SeidnpqUpnqDDIU PJxI3XBurSIAtqxhQ7Pic57ROYXxWDm6LHYXy0In8yTaxe6EuWKhDsDH+PCjKBEVEmnd HCcsMHviGpn2M5MFJl2/MtuZLIYlfSsHBTMzhUCFx2zwQqTNoAwsf9B3/A9OQaqccn1y NaG7DDraYmHtdMRaELu7SxJm2MoPjCJb7XSjS6+7JhavGDrUqo2c0ik3CW6xUdBAMwaY eHb8cIBkUUkAdYF3hCaX33yLgc7omh5eac0JA3vxDAq5Skhww6shfTP2gfPCeOSzJg+K TxVw== X-Gm-Message-State: AJcUukcFFwHYlyI/NO1ev6gL7yYJe2KTDVgKW+1L5pliSuTavqsvOVbL WYuuDJ03BnC8jewRHB2MvfE80w== X-Google-Smtp-Source: ALg8bN6lftZYtdZ8S7AWncbZCgrCMsD4uwVN5T5vyITS3mEQeaJfYm60Z7LS3rMFni3DqnwiQkNV/A== X-Received: by 2002:a2e:e02:: with SMTP id 2-v6mr37835659ljo.10.1549230168522; Sun, 03 Feb 2019 13:42:48 -0800 (PST) Received: from linux.local (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id 85-v6sm2456868lja.16.2019.02.03.13.42.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 13:42:47 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Tim Harvey , Arnd Bergmann , Olof Johansson , Linus Walleij , Bartosz Golaszewski , devicetree@vger.kernel.org Subject: [PATCH 13/17 v1] gpio: ixp4xx: Add DT bindings Date: Sun, 3 Feb 2019 22:42:01 +0100 Message-Id: <20190203214205.13594-14-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190203214205.13594-1-linus.walleij@linaro.org> References: <20190203214205.13594-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds DT bindings for the IXP4xx GPIO controller. Cc: Bartosz Golaszewski Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Reviewed-by: Bartosz Golaszewski Reviewed-by: Rob Herring --- Bartosz: looking for your ACK on this, it'd be good if the other GPIO maintainer is aligned with my ideas here. I intend to merge this through the ARM SoC tree. --- .../bindings/gpio/intel,ixp4xx-gpio.txt | 38 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt new file mode 100644 index 000000000000..8dc41ed99685 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt @@ -0,0 +1,38 @@ +Intel IXP4xx XScale Networking Processors GPIO + +This GPIO controller is found in the Intel IXP4xx processors. +It supports 16 GPIO lines. + +The interrupt portions of the GPIO controller is hierarchical: +the synchronous edge detector is part of the GPIO block, but the +actual enabling/disabling of the interrupt line is done in the +main IXP4xx interrupt controller which has a 1:1 mapping for +the first 12 GPIO lines to 12 system interrupts. + +The remaining 4 GPIO lines can not be used for receiving +interrupts. + +The interrupt parent of this GPIO controller must be the +IXP4xx interrupt controller. + +Required properties: + +- compatible : Should be + "intel,ixp4xx-gpio" +- reg : Should contain registers location and length +- gpio-controller : marks this as a GPIO controller +- #gpio-cells : Should be 2, see gpio/gpio.txt +- interrupt-controller : marks this as an interrupt controller +- #interrupt-cells : a standard two-cell interrupt, see + interrupt-controller/interrupts.txt + +Example: + +gpio0: gpio@c8004000 { + compatible = "intel,ixp4xx-gpio"; + reg = <0xc8004000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index 775a623dc91d..57d098b85523 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1650,6 +1650,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt F: arch/arm/mach-ixp4xx/ From patchwork Sun Feb 3 21:42:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1035652 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id 85-v6sm2456868lja.16.2019.02.03.13.42.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 03 Feb 2019 13:42:51 -0800 (PST) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Imre Kaloz , Krzysztof Halasa Cc: Tim Harvey , Arnd Bergmann , Olof Johansson , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 15/17 v1] ARM: ixp4xx: Add DT bindings Date: Sun, 3 Feb 2019 22:42:03 +0100 Message-Id: <20190203214205.13594-16-linus.walleij@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190203214205.13594-1-linus.walleij@linaro.org> References: <20190203214205.13594-1-linus.walleij@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds initial device tree bindings for the IXP4xx machines. This time I tried something wild and crazy and try to make proper JSON-style YAML bindings for the top level. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij Reviewed-by: Rob Herring --- I have no clear idea on how to auto-test this schema for validity, since it is a bit of a new thing I hope to figure it out as we go. --- .../devicetree/bindings/arm/intel-ixp4xx.yaml | 22 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml new file mode 100644 index 000000000000..da5f6ffe6f2d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx Device Tree Bindings + +maintainers: + - Linus Walleij + +properties: + compatible: + oneOf: + - items: + - enum: + - linksys,nslu2 + - const: intel,ixp42x + - items: + - enum: + - gateworks,gw2358-4 + - const: intel,ixp43x diff --git a/MAINTAINERS b/MAINTAINERS index 57d098b85523..c4ca249a2075 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1650,6 +1650,7 @@ M: Imre Kaloz M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.txt F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.txt