From patchwork Tue Jan 29 15:54:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1032876 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43prgC5bDkz9sDP for ; Wed, 30 Jan 2019 02:55:19 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5D4F3C21E57; Tue, 29 Jan 2019 15:54:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 82BAAC21E1D; Tue, 29 Jan 2019 15:54:34 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 78FE2C21DB6; Tue, 29 Jan 2019 15:54:31 +0000 (UTC) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id 11FDCC21CB1 for ; Tue, 29 Jan 2019 15:54:30 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BB3D01596; Tue, 29 Jan 2019 07:54:28 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EEF323F557; Tue, 29 Jan 2019 07:54:26 -0800 (PST) From: Andre Przywara To: Jagan Teki , Maxime Ripard Date: Tue, 29 Jan 2019 15:54:08 +0000 Message-Id: <20190129155416.116919-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190129155416.116919-1-andre.przywara@arm.com> References: <20190129155416.116919-1-andre.przywara@arm.com> Cc: Tom Rini , Priit Laes , u-boot@lists.denx.de, Icenowy Zheng Subject: [U-Boot] [PATCH v4 1/9] sunxi: clk: enable clk and reset for CCU devices X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some Allwinner clock devices have parent clocks and reset gates itself, which need to be activated for them to work. Add some code to just assert all resets and enable all clocks given. This should enable the A80 MMC config clock, which requires both to be activated. The full CCU devices typically don't require resets, and have just fixed clocks as their parents. Since we treat both as optional and enabling fixed clocks is a NOP, this works for all cases, without the need to differentiate between those clock types. Signed-off-by: Andre Przywara --- drivers/clk/sunxi/clk_sunxi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index 62ce2994e4..6d4aeb5315 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -61,6 +62,9 @@ struct clk_ops sunxi_clk_ops = { int sunxi_clk_probe(struct udevice *dev) { struct ccu_priv *priv = dev_get_priv(dev); + struct clk_bulk clk_bulk; + struct reset_ctl_bulk rst_bulk; + int ret; priv->base = dev_read_addr_ptr(dev); if (!priv->base) @@ -70,5 +74,13 @@ int sunxi_clk_probe(struct udevice *dev) if (!priv->desc) return -EINVAL; + ret = clk_get_bulk(dev, &clk_bulk); + if (!ret) + clk_enable_bulk(&clk_bulk); + + ret = reset_get_bulk(dev, &rst_bulk); + if (!ret) + reset_deassert_bulk(&rst_bulk); + return 0; } From patchwork Tue Jan 29 15:54:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1032877 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43prgK1Xtdz9sDP for ; Wed, 30 Jan 2019 02:55:25 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DCE90C21E57; Tue, 29 Jan 2019 15:55:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EDC40C21EB1; Tue, 29 Jan 2019 15:54:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5B7E1C21E75; Tue, 29 Jan 2019 15:54:35 +0000 (UTC) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id DB11CC21E13 for ; Tue, 29 Jan 2019 15:54:31 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E887715AB; Tue, 29 Jan 2019 07:54:30 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 04E393F557; Tue, 29 Jan 2019 07:54:28 -0800 (PST) From: Andre Przywara To: Jagan Teki , Maxime Ripard Date: Tue, 29 Jan 2019 15:54:09 +0000 Message-Id: <20190129155416.116919-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190129155416.116919-1-andre.przywara@arm.com> References: <20190129155416.116919-1-andre.przywara@arm.com> Cc: Tom Rini , Priit Laes , u-boot@lists.denx.de, Icenowy Zheng Subject: [U-Boot] [PATCH v4 2/9] sunxi: clk: add MMC gates/resets X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara [jagan: add V3S gates/resets] Signed-off-by: Jagan Teki --- drivers/clk/sunxi/clk_a10.c | 4 ++++ drivers/clk/sunxi/clk_a10s.c | 3 +++ drivers/clk/sunxi/clk_a23.c | 6 ++++++ drivers/clk/sunxi/clk_a31.c | 8 ++++++++ drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_a80.c | 4 ++++ drivers/clk/sunxi/clk_a83t.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 6 ++++++ drivers/clk/sunxi/clk_h6.c | 6 ++++++ drivers/clk/sunxi/clk_r40.c | 8 ++++++++ drivers/clk/sunxi/clk_v3s.c | 6 ++++++ 11 files changed, 63 insertions(+) diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index b00f51af8b..2aa41efe17 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -18,6 +18,10 @@ static struct ccu_clk_gate a10_gates[] = { [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)), [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)), [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)), + [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), + [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), + [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), + [CLK_AHB_MMC3] = GATE(0x060, BIT(11)), [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index aa904ce067..87b74e52dc 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -16,6 +16,9 @@ static struct ccu_clk_gate a10s_gates[] = { [CLK_AHB_OTG] = GATE(0x060, BIT(0)), [CLK_AHB_EHCI] = GATE(0x060, BIT(1)), [CLK_AHB_OHCI] = GATE(0x060, BIT(2)), + [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), + [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), + [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), [CLK_APB1_UART0] = GATE(0x06c, BIT(16)), [CLK_APB1_UART1] = GATE(0x06c, BIT(17)), diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 854259bf81..1ef2359286 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -13,6 +13,9 @@ #include static struct ccu_clk_gate a23_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), [CLK_BUS_OHCI] = GATE(0x060, BIT(29)), @@ -35,6 +38,9 @@ static struct ccu_reset a23_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)), [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)), diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index a38d76cb7c..5bd8b7dccc 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -13,6 +13,10 @@ #include static struct ccu_clk_gate a31_gates[] = { + [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)), + [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)), + [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)), + [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)), [CLK_AHB1_OTG] = GATE(0x060, BIT(24)), [CLK_AHB1_EHCI0] = GATE(0x060, BIT(26)), [CLK_AHB1_EHCI1] = GATE(0x060, BIT(27)), @@ -40,6 +44,10 @@ static struct ccu_reset a31_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), + [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)), + [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)), + [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)), + [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)), [RST_AHB1_OTG] = RESET(0x2c0, BIT(24)), [RST_AHB1_EHCI0] = RESET(0x2c0, BIT(26)), [RST_AHB1_EHCI1] = RESET(0x2c0, BIT(27)), diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index a2ba6eefc5..910275fbce 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -13,6 +13,9 @@ #include static const struct ccu_clk_gate a64_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(23)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), @@ -38,6 +41,9 @@ static const struct ccu_reset a64_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)), diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index d6dd6a1fa1..d4bfb0a98b 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -13,6 +13,8 @@ #include static const struct ccu_clk_gate a80_gates[] = { + [CLK_BUS_MMC] = GATE(0x580, BIT(8)), + [CLK_BUS_UART0] = GATE(0x594, BIT(16)), [CLK_BUS_UART1] = GATE(0x594, BIT(17)), [CLK_BUS_UART2] = GATE(0x594, BIT(18)), @@ -22,6 +24,8 @@ static const struct ccu_clk_gate a80_gates[] = { }; static const struct ccu_reset a80_resets[] = { + [RST_BUS_MMC] = RESET(0x5a0, BIT(8)), + [RST_BUS_UART0] = RESET(0x5b4, BIT(16)), [RST_BUS_UART1] = RESET(0x5b4, BIT(17)), [RST_BUS_UART2] = RESET(0x5b4, BIT(18)), diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 1ef6ac5b25..b5a555da36 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -13,6 +13,9 @@ #include static struct ccu_clk_gate a83t_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), @@ -36,6 +39,9 @@ static struct ccu_reset a83t_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_HSIC] = RESET(0x0cc, BIT(2)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f82949b3b6..416aec2b89 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -13,6 +13,9 @@ #include static struct ccu_clk_gate h3_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(23)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), @@ -44,6 +47,9 @@ static struct ccu_reset h3_resets[] = { [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), [RST_USB_PHY3] = RESET(0x0cc, BIT(3)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(23)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)), diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c index 0da3a40e3d..902612da91 100644 --- a/drivers/clk/sunxi/clk_h6.c +++ b/drivers/clk/sunxi/clk_h6.c @@ -13,6 +13,9 @@ #include static struct ccu_clk_gate h6_gates[] = { + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)), + [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)), + [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)), [CLK_BUS_UART0] = GATE(0x90c, BIT(0)), [CLK_BUS_UART1] = GATE(0x90c, BIT(1)), [CLK_BUS_UART2] = GATE(0x90c, BIT(2)), @@ -20,6 +23,9 @@ static struct ccu_clk_gate h6_gates[] = { }; static struct ccu_reset h6_resets[] = { + [RST_BUS_MMC0] = RESET(0x84c, BIT(16)), + [RST_BUS_MMC1] = RESET(0x84c, BIT(17)), + [RST_BUS_MMC2] = RESET(0x84c, BIT(18)), [RST_BUS_UART0] = RESET(0x90c, BIT(16)), [RST_BUS_UART1] = RESET(0x90c, BIT(17)), [RST_BUS_UART2] = RESET(0x90c, BIT(18)), diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index fd7aae97ea..b9457e1971 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -13,6 +13,10 @@ #include static struct ccu_clk_gate r40_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), + [CLK_BUS_MMC3] = GATE(0x060, BIT(11)), [CLK_BUS_OTG] = GATE(0x060, BIT(25)), [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), @@ -43,6 +47,10 @@ static struct ccu_reset r40_resets[] = { [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), [RST_USB_PHY2] = RESET(0x0cc, BIT(2)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), + [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)), [RST_BUS_OTG] = RESET(0x2c0, BIT(25)), [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)), [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)), diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 25ad87500e..c8a9027889 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -13,6 +13,9 @@ #include static struct ccu_clk_gate v3s_gates[] = { + [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), + [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), + [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)), [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), @@ -25,6 +28,9 @@ static struct ccu_clk_gate v3s_gates[] = { static struct ccu_reset v3s_resets[] = { [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), + [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), + [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), + [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), From patchwork Tue Jan 29 15:54:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1032879 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43prhB3qNsz9sDP for ; Wed, 30 Jan 2019 02:56:10 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 38EB3C21E42; Tue, 29 Jan 2019 15:55:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 56D53C21EA8; Tue, 29 Jan 2019 15:54:47 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D9BE1C21E74; Tue, 29 Jan 2019 15:54:37 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id E53B8C21E60 for ; Tue, 29 Jan 2019 15:54:33 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F2609A78; Tue, 29 Jan 2019 07:54:32 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3238C3F557; Tue, 29 Jan 2019 07:54:31 -0800 (PST) From: Andre Przywara To: Jagan Teki , Maxime Ripard Date: Tue, 29 Jan 2019 15:54:10 +0000 Message-Id: <20190129155416.116919-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190129155416.116919-1-andre.przywara@arm.com> References: <20190129155416.116919-1-andre.przywara@arm.com> Cc: Tom Rini , Priit Laes , u-boot@lists.denx.de, Icenowy Zheng Subject: [U-Boot] [PATCH v4 3/9] sunxi: clk: A80: add MMC clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The A80 handles resets and clock gates for the MMC devices differently, outside of the CCU IP block. Consequently we have a separate clock device with a separate binding for that. Implement that with the respective clock gates and resets to allow the A80 taking part in the DM_MMC game. Signed-off-by: Andre Przywara Signed-off-by: Jagan Teki --- drivers/clk/sunxi/clk_a80.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index d4bfb0a98b..aec1d80c46 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -34,19 +34,45 @@ static const struct ccu_reset a80_resets[] = { [RST_BUS_UART5] = RESET(0x5b4, BIT(21)), }; +static const struct ccu_clk_gate a80_mmc_gates[] = { + [0] = GATE(0x0, BIT(16)), + [1] = GATE(0x4, BIT(16)), + [2] = GATE(0x8, BIT(16)), + [3] = GATE(0xc, BIT(16)), +}; + +static const struct ccu_reset a80_mmc_resets[] = { + [0] = GATE(0x0, BIT(18)), + [1] = GATE(0x4, BIT(18)), + [2] = GATE(0x8, BIT(18)), + [3] = GATE(0xc, BIT(18)), +}; + static const struct ccu_desc a80_ccu_desc = { .gates = a80_gates, .resets = a80_resets, }; +static const struct ccu_desc a80_mmc_clk_desc = { + .gates = a80_mmc_gates, + .resets = a80_mmc_resets, +}; + static int a80_clk_bind(struct udevice *dev) { - return sunxi_reset_bind(dev, ARRAY_SIZE(a80_resets)); + ulong count = ARRAY_SIZE(a80_resets); + + if (device_is_compatible(dev, "allwinner,sun9i-a80-mmc-config-clk")) + count = ARRAY_SIZE(a80_mmc_resets); + + return sunxi_reset_bind(dev, count); } static const struct udevice_id a80_ccu_ids[] = { { .compatible = "allwinner,sun9i-a80-ccu", .data = (ulong)&a80_ccu_desc }, + { .compatible = "allwinner,sun9i-a80-mmc-config-clk", + .data = (ulong)&a80_mmc_clk_desc }, { } }; From patchwork Tue Jan 29 15:54:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1032884 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43prlG5JL6z9sDP for ; Wed, 30 Jan 2019 02:58:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 62735C21E96; Tue, 29 Jan 2019 15:56:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 13A1EC21EB4; Tue, 29 Jan 2019 15:55:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 16CB8C21E08; Tue, 29 Jan 2019 15:54:39 +0000 (UTC) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id C2F01C21E75 for ; Tue, 29 Jan 2019 15:54:35 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 086BB15BF; Tue, 29 Jan 2019 07:54:35 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3C0BA3F557; Tue, 29 Jan 2019 07:54:33 -0800 (PST) From: Andre Przywara To: Jagan Teki , Maxime Ripard Date: Tue, 29 Jan 2019 15:54:11 +0000 Message-Id: <20190129155416.116919-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190129155416.116919-1-andre.przywara@arm.com> References: <20190129155416.116919-1-andre.przywara@arm.com> Cc: Tom Rini , Priit Laes , u-boot@lists.denx.de, Icenowy Zheng Subject: [U-Boot] [PATCH v4 4/9] mmc: sunxi: Add remaining compatible strings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Add MMC compatible strings for A83T, A64, H5. Signed-off-by: Jagan Teki Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/mmc/sunxi_mmc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 302332bf97..1259e627cc 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -693,6 +693,18 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun7i-a20-mmc", .data = (ulong)&sun4i_a10_variant, }, + { + .compatible = "allwinner,sun8i-a83t-emmc", + .data = (ulong)&sun4i_a10_variant, + }, + { + .compatible = "allwinner,sun50i-a64-mmc", + .data = (ulong)&sun4i_a10_variant, + }, + { + .compatible = "allwinner,sun50i-a64-emmc", + .data = (ulong)&sun4i_a10_variant, + }, { /* sentinel */ } }; From patchwork Tue Jan 29 15:54:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1032878 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43prgq0k30z9sDP for ; Wed, 30 Jan 2019 02:55:51 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C1A1EC21EBF; Tue, 29 Jan 2019 15:55:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C4FB5C21DFA; Tue, 29 Jan 2019 15:54:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AB6DBC21E1D; Tue, 29 Jan 2019 15:54:41 +0000 (UTC) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id 03472C21E79 for ; Tue, 29 Jan 2019 15:54:38 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 12EBB1596; Tue, 29 Jan 2019 07:54:37 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 463043F557; Tue, 29 Jan 2019 07:54:35 -0800 (PST) From: Andre Przywara To: Jagan Teki , Maxime Ripard Date: Tue, 29 Jan 2019 15:54:12 +0000 Message-Id: <20190129155416.116919-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190129155416.116919-1-andre.przywara@arm.com> References: <20190129155416.116919-1-andre.przywara@arm.com> Cc: Tom Rini , Priit Laes , u-boot@lists.denx.de, Icenowy Zheng Subject: [U-Boot] [PATCH v4 5/9] mmc: sunxi: Add DM_MMC support for H6 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset. Connect that with the respective compatible string. Signed-off-by: Jagan Teki Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/mmc/sunxi_mmc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 1259e627cc..1e13a0665d 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -680,6 +680,10 @@ static const struct sunxi_mmc_variant sun4i_a10_variant = { .mclk_offset = 0x88, }; +static const struct sunxi_mmc_variant sun50i_h6_variant = { + .mclk_offset = 0x830, +}; + static const struct udevice_id sunxi_mmc_ids[] = { { .compatible = "allwinner,sun4i-a10-mmc", @@ -705,6 +709,14 @@ static const struct udevice_id sunxi_mmc_ids[] = { .compatible = "allwinner,sun50i-a64-emmc", .data = (ulong)&sun4i_a10_variant, }, + { + .compatible = "allwinner,sun50i-h6-mmc", + .data = (ulong)&sun50i_h6_variant, + }, + { + .compatible = "allwinner,sun50i-h6-emmc", + .data = (ulong)&sun50i_h6_variant, + }, { /* sentinel */ } }; From patchwork Tue Jan 29 15:54:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1032881 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43prjk1zjqz9sDP for ; Wed, 30 Jan 2019 02:57:30 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E71F2C21EC8; Tue, 29 Jan 2019 15:55:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4FB40C21EBF; Tue, 29 Jan 2019 15:54:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 08DBDC21E74; Tue, 29 Jan 2019 15:54:44 +0000 (UTC) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id 1116FC21EA8 for ; Tue, 29 Jan 2019 15:54:40 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C6E4A78; Tue, 29 Jan 2019 07:54:39 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 505383F557; Tue, 29 Jan 2019 07:54:37 -0800 (PST) From: Andre Przywara To: Jagan Teki , Maxime Ripard Date: Tue, 29 Jan 2019 15:54:13 +0000 Message-Id: <20190129155416.116919-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190129155416.116919-1-andre.przywara@arm.com> References: <20190129155416.116919-1-andre.przywara@arm.com> Cc: Tom Rini , Priit Laes , u-boot@lists.denx.de, Icenowy Zheng Subject: [U-Boot] [PATCH v4 6/9] mmc: sunxi: Add DM clk and reset support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Now that we have the gate clocks and the reset gates in our new Allwinner clock driver, let's make use of them in the MMC driver, when DM_MMC is defined. We treat the reset device as optional now, as the older SoCs don't implement it. Signed-off-by: Andre Przywara --- drivers/mmc/sunxi_mmc.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 1e13a0665d..62b658c435 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -21,7 +23,6 @@ #ifdef CONFIG_DM_MMC struct sunxi_mmc_variant { - u16 gate_offset; u16 mclk_offset; }; #endif @@ -607,9 +608,11 @@ static int sunxi_mmc_probe(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sunxi_mmc_plat *plat = dev_get_platdata(dev); struct sunxi_mmc_priv *priv = dev_get_priv(dev); + struct reset_ctl_bulk reset_bulk; + struct clk gate_clk; struct mmc_config *cfg = &plat->cfg; struct ofnode_phandle_args args; - u32 *gate_reg, *ccu_reg; + u32 *ccu_reg; int bus_width, ret; cfg->name = dev->name; @@ -641,8 +644,14 @@ static int sunxi_mmc_probe(struct udevice *dev) priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000; priv->mclkreg = (void *)ccu_reg + (priv->variant->mclk_offset + (priv->mmc_no * 4)); - gate_reg = (void *)ccu_reg + priv->variant->gate_offset; - setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no))); + + ret = clk_get_by_name(dev, "ahb", &gate_clk); + if (!ret) + clk_enable(&gate_clk); + + ret = reset_get_bulk(dev, &reset_bulk); + if (!ret) + reset_deassert_bulk(&reset_bulk); ret = mmc_set_mod_clk(priv, 24000000); if (ret) @@ -676,7 +685,6 @@ static int sunxi_mmc_bind(struct udevice *dev) } static const struct sunxi_mmc_variant sun4i_a10_variant = { - .gate_offset = 0x60, .mclk_offset = 0x88, }; From patchwork Tue Jan 29 15:54:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1032882 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43prjq4fH1z9sDP for ; Wed, 30 Jan 2019 02:57:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 22755C21DD3; Tue, 29 Jan 2019 15:56:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 187EEC21E90; Tue, 29 Jan 2019 15:55:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4C14CC21E96; Tue, 29 Jan 2019 15:54:46 +0000 (UTC) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id E3E12C21E02 for ; Tue, 29 Jan 2019 15:54:41 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 26305A78; Tue, 29 Jan 2019 07:54:41 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5A48D3F557; Tue, 29 Jan 2019 07:54:39 -0800 (PST) From: Andre Przywara To: Jagan Teki , Maxime Ripard Date: Tue, 29 Jan 2019 15:54:14 +0000 Message-Id: <20190129155416.116919-8-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190129155416.116919-1-andre.przywara@arm.com> References: <20190129155416.116919-1-andre.przywara@arm.com> Cc: Tom Rini , Priit Laes , u-boot@lists.denx.de, Icenowy Zheng Subject: [U-Boot] [PATCH v4 7/9] sunxi: board: do MMC pinmux setup for DM_MMC builds X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enabling DM_MMC skips the call to mmc_pinmux_setup() in board.c, as this is supposed to be handled by the MMC driver, using DT information. However we don't have a pinctrl driver yet, but would still like to keep the working pinmux setup for our MMC devices. So bring this particular call back to the DM_MMC code flow. When booting from either SD card or eMMC, the SPL does the setup for us, but when booting from SPI or USB we must not skip this part. Signed-off-by: Andre Przywara --- board/sunxi/board.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ad14837291..98bc3cd0c1 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -208,6 +208,10 @@ enum env_location env_get_location(enum env_operation op, int prio) } #endif +#ifdef CONFIG_DM_MMC +static void mmc_pinmux_setup(int sdc); +#endif + /* add board specific code here */ int board_init(void) { @@ -269,6 +273,17 @@ int board_init(void) i2c_init_board(); #endif +#ifdef CONFIG_DM_MMC + /* + * Temporary workaround for enabling MMC clocks until a sunxi DM + * pinctrl driver lands. + */ + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); +#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); +#endif +#endif /* CONFIG_DM_MMC */ + /* Uses dm gpio code so do this here and not in i2c_init_board() */ return soft_i2c_board_init(); } From patchwork Tue Jan 29 15:54:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1032880 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43prjJ31ZKz9sDP for ; Wed, 30 Jan 2019 02:57:08 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0C21AC21E0B; Tue, 29 Jan 2019 15:56:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B320EC21EC9; Tue, 29 Jan 2019 15:55:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C4554C21DD3; Tue, 29 Jan 2019 15:54:47 +0000 (UTC) Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id 26365C21EBF for ; Tue, 29 Jan 2019 15:54:44 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 32404A78; Tue, 29 Jan 2019 07:54:43 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 642463F557; Tue, 29 Jan 2019 07:54:41 -0800 (PST) From: Andre Przywara To: Jagan Teki , Maxime Ripard Date: Tue, 29 Jan 2019 15:54:15 +0000 Message-Id: <20190129155416.116919-9-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190129155416.116919-1-andre.przywara@arm.com> References: <20190129155416.116919-1-andre.przywara@arm.com> Cc: Tom Rini , Priit Laes , u-boot@lists.denx.de, Icenowy Zheng Subject: [U-Boot] [PATCH v4 8/9] arm: sunxi: Enable DM_MMC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Enable DM_MMC for all Allwinner SoCs, this will eventually enable BLK. Also removed DM_MMC enablement in few parts of sunxi configurations. Signed-off-by: Jagan Teki Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 1 + arch/arm/mach-sunxi/Kconfig | 1 - configs/Linksprite_pcDuino3_defconfig | 1 - 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cefa8f40d0..f0edb10003 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -851,6 +851,7 @@ config ARCH_SUNXI select DM_ETH select DM_GPIO select DM_KEYBOARD + select DM_MMC if MMC select DM_SERIAL select DM_USB if DISTRO_DEFAULTS select OF_BOARD_SETUP diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 3c54f5106d..74e234cded 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -154,7 +154,6 @@ config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7A select ARM_CORTEX_CPU_IS_UP - select DM_MMC if MMC select DM_SCSI if SCSI select PHY_SUN4I_USB select DRAM_SUN4I diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 9156f132d1..18f658e96b 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -14,7 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" CONFIG_SCSI_AHCI=y -CONFIG_DM_MMC=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_SUN7I_GMAC=y From patchwork Tue Jan 29 15:54:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1032885 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43prlG6ycQz9sML for ; Wed, 30 Jan 2019 02:58:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8350FC21EBF; Tue, 29 Jan 2019 15:56:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4A0D4C21ECA; Tue, 29 Jan 2019 15:55:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 68361C21ECE; Tue, 29 Jan 2019 15:54:49 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by lists.denx.de (Postfix) with ESMTP id 0EC13C21E68 for ; Tue, 29 Jan 2019 15:54:46 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3BEA0A78; Tue, 29 Jan 2019 07:54:45 -0800 (PST) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.197.44]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6FF7E3F557; Tue, 29 Jan 2019 07:54:43 -0800 (PST) From: Andre Przywara To: Jagan Teki , Maxime Ripard Date: Tue, 29 Jan 2019 15:54:16 +0000 Message-Id: <20190129155416.116919-10-andre.przywara@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190129155416.116919-1-andre.przywara@arm.com> References: <20190129155416.116919-1-andre.przywara@arm.com> Cc: Tom Rini , Priit Laes , u-boot@lists.denx.de, Icenowy Zheng Subject: [U-Boot] [PATCH v4 9/9] arm: dts: sunxi: Enumerate MMC2 as MMC1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Jagan Teki Environment and fastboot MMC devices are configured based number of mmc slots defined on particular board in sunxi platform. If number of slots are not more than 1, it assigns 0 which usually mmc device on SD slot. With DM_MMC it is detected as 0 since mmc0 node always be an mmc device. If number of slots are more than 1, it assigns 1 which assumes 0 is mmc device and 1 is emmc device. But with DM_MMC there is chance of detecting emmc as device 2 since mmc1 is SDIO as per devicetree definition. So override mmc2 to mmc1 in sunxi dtsi, this will eventually detect mmc2 as mmc 1 device even if the board dts has mmc0, mmc1, mmc2. Some platforms like A20 has mmc0...mmc3, but there is no usecases now for enabling all mmc controllers in any of A20 board dts files. Signed-off-by: Jagan Teki Signed-off-by: Andre Przywara --- arch/arm/dts/sunxi-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index 8a9f2a6417..fdd4c80aa4 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -1,6 +1,10 @@ #include / { + aliases { + mmc1 = &mmc2; + }; + binman { filename = "u-boot-sunxi-with-spl.bin"; pad-byte = <0xff>;