From patchwork Fri Jan 25 12:28:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1031046 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-494727-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="mGjTXIVk"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43mJGx3ZpQz9s7h for ; Fri, 25 Jan 2019 23:28:56 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=t8IcTxaFPHi7BA5nRYXgcOViwbslfUpfYkV4fkDIzEuMiRI2jO TaJLCK8FlpycWtVOP+RFMVoPOm04qK3dWKrL5i2Bz9NczLx2q10gflxZEU+a12Xy OkkXijQA3D1LcxJgkPsmyj+4trUf+JDGdDUkajFBxs8rqANCEiGIhVpIM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=A9+wwWbQvQhxhdivovBbnD43T/c=; b=mGjTXIVkYZ/A0ujB+Ozg 62yCyTC2iK2+NuuNGs1DxbfFFQFiv+cpMGYBlxtHMGDfNQuQVfmw+VUfjZD5MXQp uo7XOsMrOzVzSTpofLrhgBaxovVRIaMYelaYvZkCJuqqCa0Oh4kS8yKYhPDGt4Zl FoQJ3kXXsdWyiyoVKpaNdbQ= Received: (qmail 2312 invoked by alias); 25 Jan 2019 12:28:49 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 2302 invoked by uid 89); 25 Jan 2019 12:28:48 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.2 spammy=upl X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 25 Jan 2019 12:28:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DB943EBD; Fri, 25 Jan 2019 04:28:45 -0800 (PST) Received: from localhost (unknown [10.32.99.34]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3CEB43F589; Fri, 25 Jan 2019 04:28:45 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, Prathamesh Kulkarni , richard.sandiford@arm.com Cc: Prathamesh Kulkarni Subject: [AArch64][SVE] Handle register-register pred_movs Date: Fri, 25 Jan 2019 12:28:43 +0000 Message-ID: <878sz8vs3o.fsf@arm.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 pred_mov is defined for predicated loads and stores, where exactly one of the operands is a register. However, the instruction condition only checked for "one" rather than "exactly one", and Prathamesh found a case in which combine could fold a predicated pattern to an all-register pred_mov. The constraints would then force one of the registers to memory. This patch splits all-register forms into a normal move as soon as possible, but also adds an all-register alternative in case the instruction doesn't get split before RA (or in case the RA can use inheritance to avoid a reload). The testcase for this will be added to aarch64/sve-acle-branch. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. Applied to trunk and aarch64/sve-acle-branch. Richard 2018-01-25 Richard Sandiford gcc/ * config/aarch64/aarch64-sve.md (*pred_mov) (pred_mov): Handle all-register forms using both a new alternative and a split. Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-01-11 10:55:28.536599178 +0000 +++ gcc/config/aarch64/aarch64-sve.md 2019-01-25 12:16:19.489967684 +0000 @@ -170,18 +170,22 @@ (define_expand "aarch64_sve_reload_be" ;; all-true. Note that this pattern is generated directly by ;; aarch64_emit_sve_pred_move, so changes to this pattern will ;; need changes there as well. -(define_insn "*pred_mov" - [(set (match_operand:SVE_ALL 0 "nonimmediate_operand" "=w, m") +(define_insn_and_split "*pred_mov" + [(set (match_operand:SVE_ALL 0 "nonimmediate_operand" "=w, w, m") (unspec:SVE_ALL - [(match_operand: 1 "register_operand" "Upl, Upl") - (match_operand:SVE_ALL 2 "nonimmediate_operand" "m, w")] + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (match_operand:SVE_ALL 2 "nonimmediate_operand" "w, m, w")] UNSPEC_MERGE_PTRUE))] "TARGET_SVE && (register_operand (operands[0], mode) || register_operand (operands[2], mode))" "@ + # ld1\t%0., %1/z, %2 st1\t%2., %1, %0" + "&& register_operand (operands[0], mode) + && register_operand (operands[2], mode)" + [(set (match_dup 0) (match_dup 2))] ) (define_expand "movmisalign" @@ -401,10 +405,10 @@ (define_split ;; Predicated structure moves. This works for both endiannesses but in ;; practice is only useful for big-endian. (define_insn_and_split "pred_mov" - [(set (match_operand:SVE_STRUCT 0 "aarch64_sve_struct_nonimmediate_operand" "=w, Utx") + [(set (match_operand:SVE_STRUCT 0 "aarch64_sve_struct_nonimmediate_operand" "=w, w, Utx") (unspec:SVE_STRUCT - [(match_operand: 1 "register_operand" "Upl, Upl") - (match_operand:SVE_STRUCT 2 "aarch64_sve_struct_nonimmediate_operand" "Utx, w")] + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (match_operand:SVE_STRUCT 2 "aarch64_sve_struct_nonimmediate_operand" "w, Utx, w")] UNSPEC_MERGE_PTRUE))] "TARGET_SVE && (register_operand (operands[0], mode)