From patchwork Fri Jan 25 11:25:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1031009 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ui2jqoU2"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43mGsl1vvMz9s55 for ; Fri, 25 Jan 2019 22:25:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726095AbfAYLZa (ORCPT ); Fri, 25 Jan 2019 06:25:30 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:38521 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725909AbfAYLZa (ORCPT ); Fri, 25 Jan 2019 06:25:30 -0500 Received: by mail-wr1-f67.google.com with SMTP id v13so9880325wrw.5; Fri, 25 Jan 2019 03:25:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=mzzh5HqkKWgeEDulmsMk+XDsAXJUDsr9GECqwiKTZHY=; b=ui2jqoU21dkv9PHSREaC/P3MeCoDXR0bKcvOXSXVmEmtG0FfptyBW+0nusccGmI43J 0QVnq5jKiYdVZlAIecnpvqSjylRCpIQKrszuLwp3fUNTufAufCx1cUCwHPpQsc7U3p++ MkffM4oTV+F2pz6Bbx2Q9RbDNE3VZtEC5+TGHw9paYCclp0UoNyWdQhcROlgP/8ZR95Z dwU/kUIyPfstWOOpE4hq4yJ0Tzvm5bhqNcdWAuhK3MAshUBZriENuvLjNaluojiETcSd biM2GXLWu8J8SJEhduO5Im3FlNhJKCmMFj/TIHW0hE79yUbLyFmz65gaK87MEHqc6+Rl 3Axg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=mzzh5HqkKWgeEDulmsMk+XDsAXJUDsr9GECqwiKTZHY=; b=LwvVuWb0UFn7K88ySqRnozy5jN4QKE9NYh9MPsxdwHjniWdvpFqkPUrUE6Jbf5V7UJ bP4S3wDFrUJy5KLunj3YwmKRQxQEMWrLhfxZ5wChJODdeF7pSItjDPK4/m7NE/pddd8H rnv00HmtMBabXcx6gtHxsg1ZEvuYd8SxQwRs0/PFQZO+sXuO7j8FW+VwQbM9rUvZdYkJ Z44+Uz5wow1xhGC8hndJGInIC9F4kNdlcqm74O4Z3NLsYS/KT1UYVvD7CseZNU+7OlrU ZqivuA5waG1h/wrKOaeWh2TPjr0pSv+x4XjWBXm49LVBx/fWEUHv6njo5pUFG3Gop/kz rDUA== X-Gm-Message-State: AJcUukd1P1jMI+d5TnyahCpdGvxsahRfDev8V4Plfq99/7omHll8w3jd vJDJdzHNBo92MScBAIKtueU= X-Google-Smtp-Source: ALg8bN7hkAX0wsJwZClkm2Erd1RqVkH0yvfj7pK9yyQ+qaLUJTb339kP8lADUow5fcNX454xzQ0zkg== X-Received: by 2002:adf:bb44:: with SMTP id x4mr11560285wrg.24.1548415527927; Fri, 25 Jan 2019 03:25:27 -0800 (PST) Received: from localhost (pD9E51040.dip0.t-ipconnect.de. [217.229.16.64]) by smtp.gmail.com with ESMTPSA id v132sm63626106wme.20.2019.01.25.03.25.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jan 2019 03:25:27 -0800 (PST) From: Thierry Reding To: Kishon Vijay Abraham I , Rob Herring Cc: Jonathan Hunter , JC Kuo , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/5] dt-bindings: phy: tegra: Add Tegra186 support Date: Fri, 25 Jan 2019 12:25:21 +0100 Message-Id: <20190125112525.10697-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Extend the bindings to cover the set of features found in Tegra186. Note that, technically, there are four more supplies connected to the XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL), but the power sequencing requirements of Tegra186 require these to be under the control of the PMIC. Signed-off-by: Thierry Reding Reviewed-by: JC Kuo --- .../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt index 3742c152c467..daedb15f322e 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt @@ -36,11 +36,20 @@ Required properties: - Tegra124: "nvidia,tegra124-xusb-padctl" - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - Tegra210: "nvidia,tegra210-xusb-padctl" + - Tegra186: "nvidia,tegra186-xusb-padctl" - reg: Physical base address and length of the controller's registers. - resets: Must contain an entry for each entry in reset-names. - reset-names: Must include the following entries: - "padctl" +For Tegra186: +- avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY + power supply. Must supply 1.8 V. +- avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply + 3.3 V. +- vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V. +- vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V. + Pad nodes: ========== From patchwork Fri Jan 25 11:25:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1031013 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ReOvbQCo"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43mGt92mJ5z9s9h for ; Fri, 25 Jan 2019 22:25:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727097AbfAYLZe (ORCPT ); Fri, 25 Jan 2019 06:25:34 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:36677 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726126AbfAYLZb (ORCPT ); Fri, 25 Jan 2019 06:25:31 -0500 Received: by mail-wm1-f65.google.com with SMTP id p6so6282924wmc.1; Fri, 25 Jan 2019 03:25:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/Z8HJRf7jFWL8ndlHDECsk1rDr2pU3ULSQ2VkFakbVM=; b=ReOvbQCoTIwL8WRPo12puX+FLVBg9muumJqmo4+OeXl0dFx9DKt/KoLL6v+zIBXfYo 6Ix8ZPu6YwZYBx4gmQZ2Qk2MymHfjuh/IBl6gV2zDG9aofAV0AZqKLt4rxTrVetzodmt 1xlSs5mvRtCjlz4Hoo5CFpwvdi+bpiiUXkXLg3bWtSG8z3zG+gIylRGguK65Y3tje1Uz BwHoD54qhM0wb5GPElmUf/uSSOvCZyp7bZirDxw8pTJlARCbjPW5NZiMZlomkhj3cOkE lSYyLO08slesdxcYuqFJRyKv1ILMMgnR3WYbHeHzbAA1VY+57xt8HcF1K7GcV5w/1n0f A3nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Z8HJRf7jFWL8ndlHDECsk1rDr2pU3ULSQ2VkFakbVM=; b=mgqB3prKLx5/K3hboySQ314H26epxBOvN9XJ8j6+GwMIEAtsNzpfnhkHZzoDTRqBfO +hFmixPBxgKE1cN0sYPjN5BOuKERCOcwMzPeNZsQz+WF4Q2lKMsyo/N5NCA03jObOjd7 TFABF6wAqaUkMOXmTgzulLStnCmc1qIQmqMsBiYug8DdcRbXRpzXRm2gwiVaetYullSA 8ODDIn1x4H001o7x7q805Y8J2xQNNCmlZypLE8W7cFJEr2oKvj2IECI8RnwmR+tZ4SDk DwWlqyVUsk1iRPbhCZcCSsqwhiCwsh2rPTMyg8aTJv8YiLmyYKoTrt4OI944xIHnlBWj mn4g== X-Gm-Message-State: AJcUukck0hLUDs4WV91Lov0dydd7j6uolOHQS+ETecX4ZGJtzd59jL/w Z2qV8a8mkRQlVT5JZRe1iMQ= X-Google-Smtp-Source: ALg8bN4bYifcjefhPEJ33UuhPbDKkSL8TRnkCqJK/Hp10GVaNvIzzHYvK/iDXqw6jhU8XNRCwROvuw== X-Received: by 2002:a1c:1688:: with SMTP id 130mr6261924wmw.86.1548415529596; Fri, 25 Jan 2019 03:25:29 -0800 (PST) Received: from localhost (pD9E51040.dip0.t-ipconnect.de. [217.229.16.64]) by smtp.gmail.com with ESMTPSA id a187sm57523034wmf.33.2019.01.25.03.25.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jan 2019 03:25:28 -0800 (PST) From: Thierry Reding To: Kishon Vijay Abraham I Cc: Jonathan Hunter , JC Kuo , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] phy: tegra: xusb: Skip single function lane programming Date: Fri, 25 Jan 2019 12:25:22 +0100 Message-Id: <20190125112525.10697-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190125112525.10697-1-thierry.reding@gmail.com> References: <20190125112525.10697-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: JC Kuo Tegra186 USB2 pads and USB3 pads do not have hardware mux for changing the pad function. For such "lanes", we can skip the lane mux register programming. Signed-off-by: JC Kuo Signed-off-by: Thierry Reding Reviewed-by: JC Kuo --- drivers/phy/tegra/xusb.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 5b3b8863363e..e3bc60cfe6a1 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -313,6 +313,10 @@ static void tegra_xusb_lane_program(struct tegra_xusb_lane *lane) const struct tegra_xusb_lane_soc *soc = lane->soc; u32 value; + /* skip single function lanes */ + if (soc->num_funcs < 2) + return; + /* choose function */ value = padctl_readl(padctl, soc->offset); value &= ~(soc->mask << soc->shift); From patchwork Fri Jan 25 11:25:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1031014 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PtM12YcI"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43mGtC13rQz9sBQ for ; Fri, 25 Jan 2019 22:25:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726878AbfAYLZe (ORCPT ); Fri, 25 Jan 2019 06:25:34 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:35347 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725909AbfAYLZd (ORCPT ); Fri, 25 Jan 2019 06:25:33 -0500 Received: by mail-wr1-f68.google.com with SMTP id 96so9923564wrb.2; Fri, 25 Jan 2019 03:25:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=73PhPzZvbQ2Ilmb4WfNnZ6RVNfBIrtWaxQPD7Xifscc=; b=PtM12YcIP31FBY9DbFODt9rpmV434nV3o2v7y5VTHnwjA/TKsk6c4MZX4uva28LHd/ nWjic1fNXYc9BVieOv7ntmFnT1a4wZvBEZLbevkdyc1DD0p3530wCnpZd0/oDzvRQsio JEsviqAb5OmM5b37Di0lNaI1nHXhRsrlCNavOW6lbCZOmBtfOTce2j5g488L/yfOuV9b vDcmXsYs7ASQ8a0n1Mi9wK0appnxCMB8qrvVM6KaMV6pQfdCmjrfZpujZOMh7kqH8dK4 EOUfPwjY5B7+fotIH3uWimeWUo8msKTFqqBIJgRG7TwNvlL7JhkyLpvc4e/NJp3/uvPN 2CIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=73PhPzZvbQ2Ilmb4WfNnZ6RVNfBIrtWaxQPD7Xifscc=; b=SgXfRowSWy3c6vP78jN7oOMg5P8nL84dbWe+SvKXUZ0anFHJYCxhtATFdElhQ7d1Q0 2S0SHTnVYgGzi3/SWIw5WRMSg5vhuoDj18SWHdNijDQiJ2fdXdV304O3u+VS4phxErMV STzKc3xmggJ5HcjpJRwGNdyy62yrK07dgGit2ds4v14Sla9bItnWCbOOWKeF8qJPbxTl hkBOr1T3R1niXieVasRQsL97mQO563cK8zTB8mF+qEWo+6yFhvbwNcPWPaM3D+emLT43 jnfmX7eN7sZqDzGcTyVPffP4ic7R5I4G54BimGZD47UrW1L4XYZlvWCgJ2kGQ/IhKqTN 4NOw== X-Gm-Message-State: AJcUukf46CUTimcYFVDOar9hE98wVJhdLRug49XMxxZU1ckEiSorl4dc WUJmLevR4oyc2jUjFAbmdQNmnPIOnPM= X-Google-Smtp-Source: ALg8bN5416i1O8yVPd9Q0i16l0dIuld6v/0Yk3LEG933+Jy2E5FBbOxeS+ZCCBuWADsdRFOS47az+A== X-Received: by 2002:a5d:6a42:: with SMTP id t2mr11931024wrw.50.1548415531220; Fri, 25 Jan 2019 03:25:31 -0800 (PST) Received: from localhost (pD9E51040.dip0.t-ipconnect.de. [217.229.16.64]) by smtp.gmail.com with ESMTPSA id n11sm40781313wrw.60.2019.01.25.03.25.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jan 2019 03:25:30 -0800 (PST) From: Thierry Reding To: Kishon Vijay Abraham I Cc: Jonathan Hunter , JC Kuo , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] phy: tegra: xusb: Parse dual-role mode property Date: Fri, 25 Jan 2019 12:25:23 +0100 Message-Id: <20190125112525.10697-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190125112525.10697-1-thierry.reding@gmail.com> References: <20190125112525.10697-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The device tree bindings document the "mode" property of "ports" subnodes, but the driver was not parsing the property. In preparation for adding role switching, parse the property at probe time. Based on work by JC Kuo . Signed-off-by: Thierry Reding Reviewed-by: JC Kuo --- drivers/phy/tegra/xusb.c | 21 +++++++++++++++++++++ drivers/phy/tegra/xusb.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index e3bc60cfe6a1..57a2d08ef6da 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -546,13 +546,34 @@ static void tegra_xusb_port_unregister(struct tegra_xusb_port *port) device_unregister(&port->dev); } +static const char *const modes[] = { + [USB_DR_MODE_UNKNOWN] = "", + [USB_DR_MODE_HOST] = "host", + [USB_DR_MODE_PERIPHERAL] = "peripheral", + [USB_DR_MODE_OTG] = "otg", +}; + static int tegra_xusb_usb2_port_parse_dt(struct tegra_xusb_usb2_port *usb2) { struct tegra_xusb_port *port = &usb2->base; struct device_node *np = port->dev.of_node; + const char *mode; usb2->internal = of_property_read_bool(np, "nvidia,internal"); + if (!of_property_read_string(np, "mode", &mode)) { + int err = match_string(modes, ARRAY_SIZE(modes), mode); + if (err < 0) { + dev_err(&port->dev, "invalid value %s for \"mode\"\n", + mode); + usb2->mode = USB_DR_MODE_UNKNOWN; + } else { + usb2->mode = err; + } + } else { + usb2->mode = USB_DR_MODE_HOST; + } + usb2->supply = devm_regulator_get(&port->dev, "vbus"); return PTR_ERR_OR_ZERO(usb2->supply); } diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index b49dbc36efa3..bb60fc09c752 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -19,6 +19,8 @@ #include #include +#include + /* legacy entry points for backwards-compatibility */ int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev); int tegra_xusb_padctl_legacy_remove(struct platform_device *pdev); @@ -271,6 +273,7 @@ struct tegra_xusb_usb2_port { struct tegra_xusb_port base; struct regulator *supply; + enum usb_dr_mode mode; bool internal; }; From patchwork Fri Jan 25 11:25:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1031011 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BZxISA8y"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43mGsr48zcz9s7h for ; Fri, 25 Jan 2019 22:25:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726126AbfAYLZf (ORCPT ); Fri, 25 Jan 2019 06:25:35 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:33426 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726861AbfAYLZf (ORCPT ); Fri, 25 Jan 2019 06:25:35 -0500 Received: by mail-wm1-f65.google.com with SMTP id r24so4574924wmh.0; Fri, 25 Jan 2019 03:25:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JGpF2IEBFq/BcOsKKLH+f+PsD7f218oogkPHqHMFg7w=; b=BZxISA8y5a+JpscJaygKikAzd1hyc0JUnnzegRpBa3t2vCftplYi+Akd4qP8CxiPdp az5LpPr7yJ+a/0NsP48rXRC0mS3+USSjllVZ6YSKtx4+RzFj1xmVEJTNuzVwVMIA86hZ VxXaIHXwtZpPYgkJikPuvr38W9x4UjIkqVGBowU71bI/DjWsFCBZE8jXx+nEoeyk8rtj +UTIInDPlyhNcmKmgQ+/h9J3csIGy/pmeu5QWIdfXjb+opNAfhmZxQJORXaq599egP7+ z7ovdKic5gxbmx4UMNyECKBw3beTPVBbld0eSTIoGQ0c9hG6cIdQ8dlixxU2FVVs/6GE zgJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JGpF2IEBFq/BcOsKKLH+f+PsD7f218oogkPHqHMFg7w=; b=HDE560JvEwldB2Rfn4nsdQ2ScLsTas7QnxQ2KqNnxToDTMDl0CNqINdpQ+7FAjiMH7 8JXItsLCakEPQjezFTqv68DwZB7rdgfGykZnwW3MmqBW5Amorom77VYgoLUjmWaKXyH/ uuT/fDDM5kPa8ks6vxX5wt3/wuNA8AVk9Q0NqTnPW3BVWXalGetrQVN+u7YZrbXZ3vPc hKGD4P+TAKxoQ5G2dHHW6LRZZGD3wKjxPvY4p3if2WFsfbLh6zo2amOPNmnY9k5EmhHK 3B5AkoWawC3udd2zIRig0K2eU98lCsStnFpsqT6LDPZYBSR61eBJvpnLHd8KjR0++u20 v4wg== X-Gm-Message-State: AJcUukfsrTybaLcXnVHumurrxh7ctijjPNxruSBv4JwBc04qD03ibdd0 iGJQ/pL0nEiS8WG9rQtL+nlF0bk2gOs= X-Google-Smtp-Source: ALg8bN4CFeV+ulgys9tgrzrOL5kVIulYpmvOG4GKk+P+X8ko+0gCHXl8YaKlyUmkPDVJGNl7KntW5g== X-Received: by 2002:a1c:dd04:: with SMTP id u4mr6495206wmg.84.1548415532969; Fri, 25 Jan 2019 03:25:32 -0800 (PST) Received: from localhost (pD9E51040.dip0.t-ipconnect.de. [217.229.16.64]) by smtp.gmail.com with ESMTPSA id h17sm104181156wrt.59.2019.01.25.03.25.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jan 2019 03:25:32 -0800 (PST) From: Thierry Reding To: Kishon Vijay Abraham I Cc: Jonathan Hunter , JC Kuo , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] phy: tegra: xusb: Add support for power supplies Date: Fri, 25 Jan 2019 12:25:24 +0100 Message-Id: <20190125112525.10697-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190125112525.10697-1-thierry.reding@gmail.com> References: <20190125112525.10697-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Support enabling various supplies needed to provide power to the PLLs and logic used to drive the USB, PCI and SATA pads. Signed-off-by: Thierry Reding Reviewed-by: JC Kuo --- drivers/phy/tegra/xusb.c | 34 +++++++++++++++++++++++++++++++++- drivers/phy/tegra/xusb.h | 5 +++++ 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 57a2d08ef6da..e510629f4f1c 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -864,6 +864,7 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev) struct tegra_xusb_padctl *padctl; const struct of_device_id *match; struct resource *res; + unsigned int i; int err; /* for backwards compatibility with old device trees */ @@ -901,14 +902,38 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev) goto remove; } + padctl->supplies = devm_kcalloc(&pdev->dev, padctl->soc->num_supplies, + sizeof(*padctl->supplies), GFP_KERNEL); + if (!padctl->supplies) { + err = -ENOMEM; + goto remove; + } + + for (i = 0; i < padctl->soc->num_supplies; i++) + padctl->supplies[i].supply = padctl->soc->supply_names[i]; + + err = devm_regulator_bulk_get(&pdev->dev, padctl->soc->num_supplies, + padctl->supplies); + if (err < 0) { + dev_err(&pdev->dev, "failed to get regulators: %d\n", err); + goto remove; + } + err = reset_control_deassert(padctl->rst); if (err < 0) goto remove; + err = regulator_bulk_enable(padctl->soc->num_supplies, + padctl->supplies); + if (err < 0) { + dev_err(&pdev->dev, "failed to enable supplies: %d\n", err); + goto reset; + } + err = tegra_xusb_setup_pads(padctl); if (err < 0) { dev_err(&pdev->dev, "failed to setup pads: %d\n", err); - goto reset; + goto power_down; } err = tegra_xusb_setup_ports(padctl); @@ -921,6 +946,8 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev) remove_pads: tegra_xusb_remove_pads(padctl); +power_down: + regulator_bulk_disable(padctl->soc->num_supplies, padctl->supplies); reset: reset_control_assert(padctl->rst); remove: @@ -936,6 +963,11 @@ static int tegra_xusb_padctl_remove(struct platform_device *pdev) tegra_xusb_remove_ports(padctl); tegra_xusb_remove_pads(padctl); + err = regulator_bulk_disable(padctl->soc->num_supplies, + padctl->supplies); + if (err < 0) + dev_err(&pdev->dev, "failed to disable supplies: %d\n", err); + err = reset_control_assert(padctl->rst); if (err < 0) dev_err(&pdev->dev, "failed to assert reset: %d\n", err); diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index bb60fc09c752..5d5d22f6cb41 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -370,6 +370,9 @@ struct tegra_xusb_padctl_soc { } ports; const struct tegra_xusb_padctl_ops *ops; + + const char * const *supply_names; + unsigned int num_supplies; }; struct tegra_xusb_padctl { @@ -393,6 +396,8 @@ struct tegra_xusb_padctl { unsigned int enable; struct clk *clk; + + struct regulator_bulk_data *supplies; }; static inline void padctl_writel(struct tegra_xusb_padctl *padctl, u32 value, From patchwork Fri Jan 25 11:25:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1031012 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[217.229.16.64]) by smtp.gmail.com with ESMTPSA id l14sm205720645wrp.55.2019.01.25.03.25.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jan 2019 03:25:33 -0800 (PST) From: Thierry Reding To: Kishon Vijay Abraham I Cc: Jonathan Hunter , JC Kuo , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] phy: tegra: xusb: Add Tegra186 support Date: Fri, 25 Jan 2019 12:25:25 +0100 Message-Id: <20190125112525.10697-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190125112525.10697-1-thierry.reding@gmail.com> References: <20190125112525.10697-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: JC Kuo Add support for the XUSB pad controller found on Tegra186 SoCs. It is mostly similar to the same IP found on earlier chips, but the number of pads exposed differs, as do the programming sequences. Note that the DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL power supplies of the XUSB pad controller require strict power sequencing and are therefore controlled by the PMIC on Tegra186. Signed-off-by: JC Kuo Signed-off-by: Thierry Reding Reviewed-by: JC Kuo --- MAINTAINERS | 5 + drivers/phy/tegra/Makefile | 1 + drivers/phy/tegra/xusb-tegra186.c | 908 ++++++++++++++++++++++++++++++ drivers/phy/tegra/xusb.c | 6 + drivers/phy/tegra/xusb.h | 27 + 5 files changed, 947 insertions(+) create mode 100644 drivers/phy/tegra/xusb-tegra186.c diff --git a/MAINTAINERS b/MAINTAINERS index ddcdc29dfe1f..754f7e757361 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15099,6 +15099,11 @@ M: Laxman Dewangan S: Supported F: drivers/spi/spi-tegra* +TEGRA XUSB PADCTL DRIVER +M: JC Kuo +S: Supported +F: drivers/phy/tegra/xusb* + TEHUTI ETHERNET DRIVER M: Andy Gospodarek L: netdev@vger.kernel.org diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile index 898589238fd9..a93cd9a499b2 100644 --- a/drivers/phy/tegra/Makefile +++ b/drivers/phy/tegra/Makefile @@ -4,3 +4,4 @@ phy-tegra-xusb-y += xusb.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o +phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c new file mode 100644 index 000000000000..0dbcaddade90 --- /dev/null +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -0,0 +1,908 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "xusb.h" + +/* FUSE USB_CALIB registers */ +#define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0) +#define HS_CURR_LEVEL_PAD_MASK 0x3f +#define HS_TERM_RANGE_ADJ_SHIFT 7 +#define HS_TERM_RANGE_ADJ_MASK 0xf +#define HS_SQUELCH_SHIFT 29 +#define HS_SQUELCH_MASK 0x7 + +#define RPD_CTRL_SHIFT 0 +#define RPD_CTRL_MASK 0x1f + +/* XUSB PADCTL registers */ +#define XUSB_PADCTL_USB2_PAD_MUX 0x4 +#define USB2_PORT_SHIFT(x) ((x) * 2) +#define USB2_PORT_MASK 0x3 +#define PORT_XUSB 1 +#define HSIC_PORT_SHIFT(x) ((x) + 20) +#define HSIC_PORT_MASK 0x1 +#define PORT_HSIC 0 + +#define XUSB_PADCTL_USB2_PORT_CAP 0x8 +#define XUSB_PADCTL_SS_PORT_CAP 0xc +#define PORTX_CAP_SHIFT(x) ((x) * 4) +#define PORT_CAP_MASK 0x3 +#define PORT_CAP_DISABLED 0x0 +#define PORT_CAP_HOST 0x1 +#define PORT_CAP_DEVICE 0x2 +#define PORT_CAP_OTG 0x3 + +#define XUSB_PADCTL_ELPG_PROGRAM 0x20 +#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) (1 << (x)) +#define USB2_PORT_WAKEUP_EVENT(x) ( 1 << ((x) + 7)) +#define SS_PORT_WAKE_INTERRUPT_ENABLE(x) (1 << ((x) + 14)) +#define SS_PORT_WAKEUP_EVENT(x) (1 << ((x) + 21)) +#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) (1 << ((x) + 28)) +#define USB2_HSIC_PORT_WAKEUP_EVENT(x) (1 << ((x) + 30)) +#define ALL_WAKE_EVENTS \ + (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \ + USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \ + SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \ + USB2_HSIC_PORT_WAKEUP_EVENT(0)) + +#define XUSB_PADCTL_ELPG_PROGRAM_1 0x24 +#define SSPX_ELPG_CLAMP_EN(x) (1 << (0 + (x) * 3)) +#define SSPX_ELPG_CLAMP_EN_EARLY(x) (1 << (1 + (x) * 3)) +#define SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3)) + +#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40) +#define HS_CURR_LEVEL(x) ((x) & 0x3f) +#define TERM_SEL (1 << 25) +#define USB2_OTG_PD (1 << 26) +#define USB2_OTG_PD2 (1 << 27) +#define USB2_OTG_PD2_OVRD_EN (1 << 28) +#define USB2_OTG_PD_ZI (1 << 29) + +#define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40) +#define USB2_OTG_PD_DR (1 << 2) +#define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3) +#define RPD_CTRL(x) (((x) & 0x1f) << 26) + +#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284 +#define BIAS_PAD_PD (1 << 11) +#define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0) + +#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288 +#define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12) +#define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19) +#define USB2_PD_TRK (1 << 26) + +#define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20) +#define HSIC_PD_TX_DATA0 (1 << 1) +#define HSIC_PD_TX_STROBE (1 << 3) +#define HSIC_PD_RX_DATA0 (1 << 4) +#define HSIC_PD_RX_STROBE (1 << 6) +#define HSIC_PD_ZI_DATA0 (1 << 7) +#define HSIC_PD_ZI_STROBE (1 << 9) +#define HSIC_RPD_DATA0 (1 << 13) +#define HSIC_RPD_STROBE (1 << 15) +#define HSIC_RPU_DATA0 (1 << 16) +#define HSIC_RPU_STROBE (1 << 18) + +#define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 (0x340) +#define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5) +#define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12) +#define HSIC_PD_TRK (1 << 19) + +#define USB2_VBUS_ID (0x360) +#define VBUS_OVERRIDE (1 << 14) +#define ID_OVERRIDE(x) (((x) & 0xf) << 18) +#define ID_OVERRIDE_FLOATING ID_OVERRIDE(8) +#define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0) + +#define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \ + { \ + .name = _name, \ + .offset = _offset, \ + .shift = _shift, \ + .mask = _mask, \ + .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \ + .funcs = tegra186_##_type##_functions, \ + } + +struct tegra_xusb_fuse_calibration { + u32 *hs_curr_level; + u32 hs_squelch; + u32 hs_term_range_adj; + u32 rpd_ctrl; +}; + +struct tegra186_xusb_padctl { + struct tegra_xusb_padctl base; + + struct tegra_xusb_fuse_calibration calib; + + /* UTMI bias and tracking */ + struct clk *usb2_trk_clk; + unsigned int bias_pad_enable; +}; + +static inline struct tegra186_xusb_padctl * +to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl) +{ + return container_of(padctl, struct tegra186_xusb_padctl, base); +} + +/* USB 2.0 UTMI PHY support */ +static struct tegra_xusb_lane * +tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, + unsigned int index) +{ + struct tegra_xusb_usb2_lane *usb2; + int err; + + usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); + if (!usb2) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&usb2->base.list); + usb2->base.soc = &pad->soc->lanes[index]; + usb2->base.index = index; + usb2->base.pad = pad; + usb2->base.np = np; + + err = tegra_xusb_lane_parse_dt(&usb2->base, np); + if (err < 0) { + kfree(usb2); + return ERR_PTR(err); + } + + return &usb2->base; +} + +static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) +{ + struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); + + kfree(usb2); +} + +static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = { + .probe = tegra186_usb2_lane_probe, + .remove = tegra186_usb2_lane_remove, +}; + +static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) +{ + struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); + struct device *dev = padctl->dev; + u32 value; + int err; + + mutex_lock(&padctl->lock); + + if (priv->bias_pad_enable++ > 0) { + mutex_unlock(&padctl->lock); + return; + } + + err = clk_prepare_enable(priv->usb2_trk_clk); + if (err < 0) + dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + value &= ~USB2_TRK_START_TIMER(~0); + value |= USB2_TRK_START_TIMER(0x1e); + value &= ~USB2_TRK_DONE_RESET_TIMER(~0); + value |= USB2_TRK_DONE_RESET_TIMER(0xa); + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); + value &= ~BIAS_PAD_PD; + value &= ~HS_SQUELCH_LEVEL(~0); + value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch); + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); + + udelay(1); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + value &= ~USB2_PD_TRK; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + + mutex_unlock(&padctl->lock); +} + +static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) +{ + struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); + u32 value; + + mutex_lock(&padctl->lock); + + if (WARN_ON(priv->bias_pad_enable == 0)) { + mutex_unlock(&padctl->lock); + return; + } + + if (--priv->bias_pad_enable > 0) { + mutex_unlock(&padctl->lock); + return; + } + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + value |= USB2_PD_TRK; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); + + clk_disable_unprepare(priv->usb2_trk_clk); + + mutex_unlock(&padctl->lock); +} + +void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy) +{ + struct tegra_xusb_lane *lane = phy_get_drvdata(phy); + struct tegra_xusb_padctl *padctl = lane->pad->padctl; + struct tegra_xusb_usb2_port *port; + struct device *dev = padctl->dev; + unsigned int index = lane->index; + u32 value; + + if (!phy) + return; + + port = tegra_xusb_find_usb2_port(padctl, index); + if (!port) { + dev_err(dev, "no port found for USB2 lane %u\n", index); + return; + } + + tegra186_utmi_bias_pad_power_on(padctl); + + udelay(2); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); + value &= ~USB2_OTG_PD; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); + value &= ~USB2_OTG_PD_DR; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); +} + +void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy) +{ + struct tegra_xusb_lane *lane = phy_get_drvdata(phy); + struct tegra_xusb_padctl *padctl = lane->pad->padctl; + unsigned int index = lane->index; + u32 value; + + if (!phy) + return; + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); + value |= USB2_OTG_PD; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); + value |= USB2_OTG_PD_DR; + padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); + + udelay(2); + + tegra186_utmi_bias_pad_power_off(padctl); +} + +static int tegra186_utmi_phy_power_on(struct phy *phy) +{ + struct tegra_xusb_lane *lane = phy_get_drvdata(phy); + struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); + struct tegra_xusb_padctl *padctl = lane->pad->padctl; + struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); + struct tegra_xusb_usb2_port *port; + unsigned int index = lane->index; + struct device *dev = padctl->dev; + u32 value; + + port = tegra_xusb_find_usb2_port(padctl, index); + if (!port) { + dev_err(dev, "no port found for USB2 lane %u\n", index); + return -ENODEV; + } + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); + value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index)); + value |= (PORT_XUSB << USB2_PORT_SHIFT(index)); + padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); + value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index)); + + if (port->mode == USB_DR_MODE_UNKNOWN) + value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index)); + else if (port->mode == USB_DR_MODE_PERIPHERAL) + value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index)); + else if (port->mode == USB_DR_MODE_HOST) + value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index)); + else if (port->mode == USB_DR_MODE_OTG) + value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index)); + + padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); + value &= ~USB2_OTG_PD_ZI; + value |= TERM_SEL; + value &= ~HS_CURR_LEVEL(~0); + + /* TODO hs_curr_level_offset support */ + if (usb2->hs_curr_level_offset) { + int hs_current_level; + + hs_current_level = (int)priv->calib.hs_curr_level[index] + + usb2->hs_curr_level_offset; + + if (hs_current_level < 0) + hs_current_level = 0; + if (hs_current_level > 0x3f) + hs_current_level = 0x3f; + + value |= HS_CURR_LEVEL(hs_current_level); + } else { + value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]); + } + + padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); + + value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); + value &= ~TERM_RANGE_ADJ(~0); + value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj); + value &= ~RPD_CTRL(~0); + value |= RPD_CTRL(priv->calib.rpd_ctrl); + padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); + + /* TODO: pad power saving */ + tegra_phy_xusb_utmi_pad_power_on(phy); + return 0; +} + +static int tegra186_utmi_phy_power_off(struct phy *phy) +{ + /* TODO: pad power saving */ + tegra_phy_xusb_utmi_pad_power_down(phy); + + return 0; +} + +static int tegra186_utmi_phy_init(struct phy *phy) +{ + struct tegra_xusb_lane *lane = phy_get_drvdata(phy); + struct tegra_xusb_padctl *padctl = lane->pad->padctl; + struct tegra_xusb_usb2_port *port; + unsigned int index = lane->index; + struct device *dev = padctl->dev; + int err; + + port = tegra_xusb_find_usb2_port(padctl, index); + if (!port) { + dev_err(dev, "no port found for USB2 lane %u\n", index); + return -ENODEV; + } + + if (port->supply && port->mode == USB_DR_MODE_HOST) { + err = regulator_enable(port->supply); + if (err) { + dev_err(dev, "failed to enable port %u VBUS: %d\n", + index, err); + return err; + } + } + + return 0; +} + +static int tegra186_utmi_phy_exit(struct phy *phy) +{ + struct tegra_xusb_lane *lane = phy_get_drvdata(phy); + struct tegra_xusb_padctl *padctl = lane->pad->padctl; + struct tegra_xusb_usb2_port *port; + unsigned int index = lane->index; + struct device *dev = padctl->dev; + int err; + + port = tegra_xusb_find_usb2_port(padctl, index); + if (!port) { + dev_err(dev, "no port found for USB2 lane %u\n", index); + return -ENODEV; + } + + if (port->supply && port->mode == USB_DR_MODE_HOST) { + err = regulator_disable(port->supply); + if (err) { + dev_err(dev, "failed to disable port %u VBUS: %d\n", + index, err); + return err; + } + } + + return 0; +} + +static const struct phy_ops utmi_phy_ops = { + .init = tegra186_utmi_phy_init, + .exit = tegra186_utmi_phy_exit, + .power_on = tegra186_utmi_phy_power_on, + .power_off = tegra186_utmi_phy_power_off, + .owner = THIS_MODULE, +}; + +static struct tegra_xusb_pad * +tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl, + const struct tegra_xusb_pad_soc *soc, + struct device_node *np) +{ + struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); + struct tegra_xusb_usb2_pad *usb2; + struct tegra_xusb_pad *pad; + int err; + + usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); + if (!usb2) + return ERR_PTR(-ENOMEM); + + pad = &usb2->base; + pad->ops = &tegra186_usb2_lane_ops; + pad->soc = soc; + + err = tegra_xusb_pad_init(pad, padctl, np); + if (err < 0) { + kfree(usb2); + goto out; + } + + priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk"); + if (IS_ERR(usb2->clk)) { + err = PTR_ERR(usb2->clk); + dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err); + goto unregister; + } + + err = tegra_xusb_pad_register(pad, &utmi_phy_ops); + if (err < 0) + goto unregister; + + dev_set_drvdata(&pad->dev, pad); + + return pad; + +unregister: + device_unregister(&pad->dev); +out: + return ERR_PTR(err); +} + +static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad) +{ + struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad); + + kfree(usb2); +} + +static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = { + .probe = tegra186_usb2_pad_probe, + .remove = tegra186_usb2_pad_remove, +}; + +static const char * const tegra186_usb2_functions[] = { + "xusb", +}; + +static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = { + TEGRA186_LANE("usb2-0", 0, 0, 0, usb2), + TEGRA186_LANE("usb2-1", 0, 0, 0, usb2), + TEGRA186_LANE("usb2-2", 0, 0, 0, usb2), +}; + +static const struct tegra_xusb_pad_soc tegra186_usb2_pad = { + .name = "usb2", + .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes), + .lanes = tegra186_usb2_lanes, + .ops = &tegra186_usb2_pad_ops, +}; + +static int tegra186_usb2_port_enable(struct tegra_xusb_port *port) +{ + return 0; +} + +static void tegra186_usb2_port_disable(struct tegra_xusb_port *port) +{ +} + +static struct tegra_xusb_lane * +tegra186_usb2_port_map(struct tegra_xusb_port *port) +{ + return tegra_xusb_find_lane(port->padctl, "usb2", port->index); +} + +static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = { + .enable = tegra186_usb2_port_enable, + .disable = tegra186_usb2_port_disable, + .map = tegra186_usb2_port_map, +}; + +/* SuperSpeed PHY support */ +static struct tegra_xusb_lane * +tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np, + unsigned int index) +{ + struct tegra_xusb_usb3_lane *usb3; + int err; + + usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL); + if (!usb3) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&usb3->base.list); + usb3->base.soc = &pad->soc->lanes[index]; + usb3->base.index = index; + usb3->base.pad = pad; + usb3->base.np = np; + + err = tegra_xusb_lane_parse_dt(&usb3->base, np); + if (err < 0) { + kfree(usb3); + return ERR_PTR(err); + } + + return &usb3->base; +} + +static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane) +{ + struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane); + + kfree(usb3); +} + +static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = { + .probe = tegra186_usb3_lane_probe, + .remove = tegra186_usb3_lane_remove, +}; +static int tegra186_usb3_port_enable(struct tegra_xusb_port *port) +{ + return 0; +} + +static void tegra186_usb3_port_disable(struct tegra_xusb_port *port) +{ +} + +static struct tegra_xusb_lane * +tegra186_usb3_port_map(struct tegra_xusb_port *port) +{ + return tegra_xusb_find_lane(port->padctl, "usb3", port->index); +} + +static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = { + .enable = tegra186_usb3_port_enable, + .disable = tegra186_usb3_port_disable, + .map = tegra186_usb3_port_map, +}; + +static int tegra186_usb3_phy_power_on(struct phy *phy) +{ + struct tegra_xusb_lane *lane = phy_get_drvdata(phy); + struct tegra_xusb_padctl *padctl = lane->pad->padctl; + struct tegra_xusb_usb3_port *port; + struct tegra_xusb_usb2_port *usb2; + unsigned int index = lane->index; + struct device *dev = padctl->dev; + u32 value; + + port = tegra_xusb_find_usb3_port(padctl, index); + if (!port) { + dev_err(dev, "no port found for USB3 lane %u\n", index); + return -ENODEV; + } + + usb2 = tegra_xusb_find_usb2_port(padctl, port->port); + if (!usb2) { + dev_err(dev, "no companion port found for USB3 lane %u\n", + index); + return -ENODEV; + } + + mutex_lock(&padctl->lock); + + value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP); + value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index)); + + if (usb2->mode == USB_DR_MODE_UNKNOWN) + value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index)); + else if (usb2->mode == USB_DR_MODE_PERIPHERAL) + value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index)); + else if (usb2->mode == USB_DR_MODE_HOST) + value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index)); + else if (usb2->mode == USB_DR_MODE_OTG) + value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index)); + + padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); + value &= ~SSPX_ELPG_VCORE_DOWN(index); + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); + + usleep_range(100, 200); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); + value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index); + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); + + usleep_range(100, 200); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); + value &= ~SSPX_ELPG_CLAMP_EN(index); + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); + + mutex_unlock(&padctl->lock); + + return 0; +} + +static int tegra186_usb3_phy_power_off(struct phy *phy) +{ + struct tegra_xusb_lane *lane = phy_get_drvdata(phy); + struct tegra_xusb_padctl *padctl = lane->pad->padctl; + struct tegra_xusb_usb3_port *port; + unsigned int index = lane->index; + struct device *dev = padctl->dev; + u32 value; + + port = tegra_xusb_find_usb3_port(padctl, index); + if (!port) { + dev_err(dev, "no port found for USB3 lane %u\n", index); + return -ENODEV; + } + + mutex_lock(&padctl->lock); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); + value |= SSPX_ELPG_CLAMP_EN_EARLY(index); + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); + + usleep_range(100, 200); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); + value |= SSPX_ELPG_CLAMP_EN(index); + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); + + usleep_range(250, 350); + + value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); + value |= SSPX_ELPG_VCORE_DOWN(index); + padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); + + mutex_unlock(&padctl->lock); + + return 0; +} + +static int tegra186_usb3_phy_init(struct phy *phy) +{ + return 0; +} + +static int tegra186_usb3_phy_exit(struct phy *phy) +{ + return 0; +} + +static const struct phy_ops usb3_phy_ops = { + .init = tegra186_usb3_phy_init, + .exit = tegra186_usb3_phy_exit, + .power_on = tegra186_usb3_phy_power_on, + .power_off = tegra186_usb3_phy_power_off, + .owner = THIS_MODULE, +}; + +static struct tegra_xusb_pad * +tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl, + const struct tegra_xusb_pad_soc *soc, + struct device_node *np) +{ + struct tegra_xusb_usb3_pad *usb3; + struct tegra_xusb_pad *pad; + int err; + + usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL); + if (!usb3) + return ERR_PTR(-ENOMEM); + + pad = &usb3->base; + pad->ops = &tegra186_usb3_lane_ops; + pad->soc = soc; + + err = tegra_xusb_pad_init(pad, padctl, np); + if (err < 0) { + kfree(usb3); + goto out; + } + + err = tegra_xusb_pad_register(pad, &usb3_phy_ops); + if (err < 0) + goto unregister; + + dev_set_drvdata(&pad->dev, pad); + + return pad; + +unregister: + device_unregister(&pad->dev); +out: + return ERR_PTR(err); +} + +static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad) +{ + struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad); + + kfree(usb2); +} + +static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = { + .probe = tegra186_usb3_pad_probe, + .remove = tegra186_usb3_pad_remove, +}; + +static const char * const tegra186_usb3_functions[] = { + "xusb", +}; + +static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = { + TEGRA186_LANE("usb3-0", 0, 0, 0, usb3), + TEGRA186_LANE("usb3-1", 0, 0, 0, usb3), + TEGRA186_LANE("usb3-2", 0, 0, 0, usb3), +}; + +static const struct tegra_xusb_pad_soc tegra186_usb3_pad = { + .name = "usb3", + .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes), + .lanes = tegra186_usb3_lanes, + .ops = &tegra186_usb3_pad_ops, +}; + +static const struct tegra_xusb_pad_soc * const tegra186_pads[] = { + &tegra186_usb2_pad, + &tegra186_usb3_pad, +#if 0 /* TODO implement */ + &tegra186_hsic_pad, +#endif +}; + +static int +tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl) +{ + struct device *dev = padctl->base.dev; + unsigned int i, count; + u32 value, *level; + int err; + + count = padctl->base.soc->ports.usb2.count; + + level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL); + if (!level) + return -ENOMEM; + + err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value); + if (err) { + dev_err(dev, "failed to read calibration fuse: %d\n", err); + return err; + } + + dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value); + + for (i = 0; i < count; i++) + level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) & + HS_CURR_LEVEL_PAD_MASK; + + padctl->calib.hs_curr_level = level; + + padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) & + HS_SQUELCH_MASK; + padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) & + HS_TERM_RANGE_ADJ_MASK; + + err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value); + if (err) { + dev_err(dev, "failed to read calibration fuse: %d\n", err); + return err; + } + + dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value); + + padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK; + + return 0; +} + +static struct tegra_xusb_padctl * +tegra186_xusb_padctl_probe(struct device *dev, + const struct tegra_xusb_padctl_soc *soc) +{ + struct tegra186_xusb_padctl *priv; + int err; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return ERR_PTR(-ENOMEM); + + priv->base.dev = dev; + priv->base.soc = soc; + + err = tegra186_xusb_read_fuse_calibration(priv); + if (err < 0) + return ERR_PTR(err); + + return &priv->base; +} + +static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl) +{ +} + +static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = { + .probe = tegra186_xusb_padctl_probe, + .remove = tegra186_xusb_padctl_remove, +}; + +static const char * const tegra186_xusb_padctl_supply_names[] = { + "avdd-pll-erefeut", + "avdd-usb", + "vclamp-usb", + "vddio-hsic", +}; + +const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = { + .num_pads = ARRAY_SIZE(tegra186_pads), + .pads = tegra186_pads, + .ports = { + .usb2 = { + .ops = &tegra186_usb2_port_ops, + .count = 3, + }, +#if 0 /* TODO implement */ + .hsic = { + .ops = &tegra186_hsic_port_ops, + .count = 1, + }, +#endif + .usb3 = { + .ops = &tegra186_usb3_port_ops, + .count = 3, + }, + }, + .ops = &tegra186_xusb_padctl_ops, + .supply_names = tegra186_xusb_padctl_supply_names, + .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names), +}; +EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc); + +MODULE_AUTHOR("JC Kuo "); +MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index e510629f4f1c..0417213ed68b 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -67,6 +67,12 @@ static const struct of_device_id tegra_xusb_padctl_of_match[] = { .compatible = "nvidia,tegra210-xusb-padctl", .data = &tegra210_xusb_padctl_soc, }, +#endif +#if defined(CONFIG_ARCH_TEGRA_186_SOC) + { + .compatible = "nvidia,tegra186-xusb-padctl", + .data = &tegra186_xusb_padctl_soc, + }, #endif { } }; diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index 5d5d22f6cb41..e0028b9fe702 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -56,10 +56,21 @@ struct tegra_xusb_lane { int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, struct device_node *np); +struct tegra_xusb_usb3_lane { + struct tegra_xusb_lane base; +}; + +static inline struct tegra_xusb_usb3_lane * +to_usb3_lane(struct tegra_xusb_lane *lane) +{ + return container_of(lane, struct tegra_xusb_usb3_lane, base); +} + struct tegra_xusb_usb2_lane { struct tegra_xusb_lane base; u32 hs_curr_level_offset; + bool powered_on; }; static inline struct tegra_xusb_usb2_lane * @@ -170,6 +181,19 @@ int tegra_xusb_pad_register(struct tegra_xusb_pad *pad, const struct phy_ops *ops); void tegra_xusb_pad_unregister(struct tegra_xusb_pad *pad); +struct tegra_xusb_usb3_pad { + struct tegra_xusb_pad base; + + unsigned int enable; + struct mutex lock; +}; + +static inline struct tegra_xusb_usb3_pad * +to_usb3_pad(struct tegra_xusb_pad *pad) +{ + return container_of(pad, struct tegra_xusb_usb3_pad, base); +} + struct tegra_xusb_usb2_pad { struct tegra_xusb_pad base; @@ -425,5 +449,8 @@ extern const struct tegra_xusb_padctl_soc tegra124_xusb_padctl_soc; #if defined(CONFIG_ARCH_TEGRA_210_SOC) extern const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc; #endif +#if defined(CONFIG_ARCH_TEGRA_186_SOC) +extern const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc; +#endif #endif /* __PHY_TEGRA_XUSB_H */