From patchwork Fri Jan 25 10:00:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1030874 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pX8mCmjd"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43mF0M1gs9z9s7h for ; Fri, 25 Jan 2019 21:01:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728047AbfAYKBG (ORCPT ); Fri, 25 Jan 2019 05:01:06 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:38599 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726926AbfAYKBC (ORCPT ); Fri, 25 Jan 2019 05:01:02 -0500 Received: by mail-wm1-f65.google.com with SMTP id m22so6048323wml.3; Fri, 25 Jan 2019 02:01:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=T/UQeUZj1wfzsljb8R8UvciTizazppkj1s++DiCAs9I=; b=pX8mCmjdmtaXMrxBigBVvKhEBdr4tHYJV4ClPV0jcKnO3BIzMQOT2F61VGRFbsuhFP +YfgguumYbhVyBsNV1SmCSkownk3IIsMV9N05WwveSB8xYS9gRj2YKHSNWw8cegJEZ1K aZiTqrYqR8MN6XA279ivkaGgusJYviSGZTIB6L6HQjo11ntDDNkatIkOhpiGSPNKvSfs z4345K99sL38rgLLh3P0iOtK/rgrM0JVOtzgMxPK+CY6zN6/MVAOhby3YHifh7KKYVmq nlTUK9HRRppyaF5bS8bVIJRpgeZsJmloMUBcUH6abSUnj7LKuWrxbZzflWCs0CWbRD6a BbGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=T/UQeUZj1wfzsljb8R8UvciTizazppkj1s++DiCAs9I=; b=El93Sz85hXVgBPoDn54u2WndmUJ3dFdmhVlqXLJY3nKb4zsc/Jjj6RoXKVRICVVi11 I/d/zmIt6J2yZygCkVQL6T8pBXlThfipJ5DCox0Jfl/D/mhue4VtrZ0fu94X21s5Lq6L 49omRtilMRAfvNbtXfrA9wvJLQb202+nyKf9aswRS8uOEjFQdGJR53ReDdsFTVS3NFWY Pp1r8B4xbN3fVEqsBB2htPDsuzU3a6DLFoTf/z9XEDCjhTu8XCbE803MKsh3m9kfGzlp b3gFnwqXRF9ikQcPPeOV7Gq/M4BbCsvndAVe5uibTe5EBha2u+myOr+D13OUy9WuUBW7 PNrg== X-Gm-Message-State: AJcUukdymNLX/HAUPyNTZ0+gmQWdtoO1MyjI+gClXnSFrwy68OAygbmT KXtbXhQBqgmZwfQKYgzwmMI= X-Google-Smtp-Source: ALg8bN6o/Ufqg4njtKKf9pfdHFjfMD0mV2VuySrKKpMHLEs5GvUIuMZ+KUn3V6k77mLYkakE72K06w== X-Received: by 2002:a1c:8c13:: with SMTP id o19mr5929161wmd.56.1548410459958; Fri, 25 Jan 2019 02:00:59 -0800 (PST) Received: from localhost (pD9E51040.dip0.t-ipconnect.de. [217.229.16.64]) by smtp.gmail.com with ESMTPSA id n82sm61745661wma.42.2019.01.25.02.00.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jan 2019 02:00:59 -0800 (PST) From: Thierry Reding To: Thierry Reding , Rob Herring Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: display: tegra: Support SOR crossbar configuration Date: Fri, 25 Jan 2019 11:00:57 +0100 Message-Id: <20190125100058.20203-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The SOR has a crossbar that can map each lane of the SOR to each of the SOR pads. The mapping is usually the same across designs for a specific SoC generation, but every now and then there's a design that doesn't. Allow the crossbar configuration to be specified in device tree to make it possible to support these designs. Signed-off-by: Thierry Reding --- .../bindings/display/tegra/nvidia,tegra20-host1x.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 593be44a53c9..9999255ac5b6 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -238,6 +238,9 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane + of the SOR, identified by the cell's index, is mapped via the crossbar to + the pad specified by the cell's value. Optional properties when driving an eDP output: - nvidia,dpaux: phandle to a DispayPort AUX interface From patchwork Fri Jan 25 10:00:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1030876 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="DTbdIZNz"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43mF0Q2PgMz9s4s for ; Fri, 25 Jan 2019 21:01:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728673AbfAYKBF (ORCPT ); Fri, 25 Jan 2019 05:01:05 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:44005 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728047AbfAYKBD (ORCPT ); Fri, 25 Jan 2019 05:01:03 -0500 Received: by mail-wr1-f67.google.com with SMTP id r10so9579643wrs.10; Fri, 25 Jan 2019 02:01:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CyDtzJnNcUg1tv7KpcUNHzz0pb2P+fxH3FnYCzVySEE=; b=DTbdIZNzQpg4VSHjfpReLfCjDcu9UmW0f/dwF9/8ThK/OP6iFGfnfXGlFVevl0ZGuj 9Lj8lN0ee5ZcpyXUKgE4fFvv379yC0YroHyLAgafE7gz9Dt0OtuBRN4ZVTdOmWkHCZVP nDCAAp7biUwviTxoS/2tlMqKAUPIJ/qS4QoiKZc/3DwyQnYWvz6YZeUJLy0TaBY8D3lq WBsGOoJd1LDqlLVlOmCip5PsnnYbzJif9NrQTEzL+s7iMOfTqu1/dq/G+4w8ZmZVN5wS L7tTmdkbwHsOgsfNwOkz5w87S0iyn7kuRwiFkq+3xDoCpYwArEoYX7yqu6t7VKL+6eUn +ZoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CyDtzJnNcUg1tv7KpcUNHzz0pb2P+fxH3FnYCzVySEE=; b=oM7na4nNk41MgzZPwpctdOtb8MQJ3dESoVV9ANbvqtxvhGO0UqUiMv3OmYkt1NWcrI vyCSdTw89rFoUvidC4ENGcKaSbPi9fKzfbErqvN7Y1vvwRwLz+pqcfQL+jR5KyhMqLED 4ocLOZErk8Id0KPL52jBRiCwWRwoevALPTQ/kQHVOKV04EkrcULs+QrIuIYjATrf6BoV GsHF8+uZC5HiWzH3S2I60oQ07I4rd7XrpHmzvSjm1qS5q8Vetj7RDnI5O2/LlVv2TGgL sHqQdQadLRgkrg9yaak4PswK3C84Cul+iNmLJYgw1IiVkq/VmcwwYLNMwku0w0h03Ipl v4eA== X-Gm-Message-State: AJcUukcxNAdRfNQaCnKIzJqdPa1nngocvcuscWosB4MpH30zrYbkh2fM IKl+fVt+QRRI3znNkMoTI/4= X-Google-Smtp-Source: ALg8bN7Nfi5hAOOklmZyujjf255Q92k3Q1Z/koKaPpJmmIFdzx8R2N8YsVFxa9jHyPGNTD6Vw9aFWQ== X-Received: by 2002:adf:bb8d:: with SMTP id q13mr10623495wrg.183.1548410461423; Fri, 25 Jan 2019 02:01:01 -0800 (PST) Received: from localhost (pD9E51040.dip0.t-ipconnect.de. [217.229.16.64]) by smtp.gmail.com with ESMTPSA id c1sm50933264wmb.14.2019.01.25.02.01.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Jan 2019 02:01:00 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] drm/tegra: sor: Support device tree crossbar configuration Date: Fri, 25 Jan 2019 11:00:58 +0100 Message-Id: <20190125100058.20203-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190125100058.20203-1-thierry.reding@gmail.com> References: <20190125100058.20203-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The crossbar configuration is usually the same across all designs for a given SoC generation. But sometimes there are designs that require some other configuration. Implement support for parsing the crossbar configuration from a device tree. If the crossbar configuration is not present in the device tree, fall back to the default crossbar configuration. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/sor.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 23329f1e07e8..40057106f5f3 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -410,6 +410,8 @@ struct tegra_sor { struct clk *clk_dp; struct clk *clk; + u8 xbar_cfg[5]; + struct drm_dp_aux *aux; struct drm_info_list *debugfs_files; @@ -1814,7 +1816,7 @@ static void tegra_sor_edp_enable(struct drm_encoder *encoder) /* XXX not in TRM */ for (value = 0, i = 0; i < 5; i++) - value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | + value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | SOR_XBAR_CTRL_LINK1_XSEL(i, i); tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); @@ -2551,7 +2553,7 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) /* XXX not in TRM */ for (value = 0, i = 0; i < 5; i++) - value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | + value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | SOR_XBAR_CTRL_LINK1_XSEL(i, i); tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); @@ -3172,6 +3174,8 @@ MODULE_DEVICE_TABLE(of, tegra_sor_of_match); static int tegra_sor_parse_dt(struct tegra_sor *sor) { struct device_node *np = sor->dev->of_node; + u32 xbar_cfg[5]; + unsigned int i; u32 value; int err; @@ -3189,6 +3193,17 @@ static int tegra_sor_parse_dt(struct tegra_sor *sor) sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; } + err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); + if (err < 0) { + /* fall back to default per-SoC XBAR configuration */ + for (i = 0; i < 5; i++) + sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; + } else { + /* copy cells to SOR XBAR configuration */ + for (i = 0; i < 5; i++) + sor->xbar_cfg[i] = xbar_cfg[i]; + } + return 0; }