From patchwork Tue Jan 22 15:59:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029367 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY6M1Fr9z9s9G for ; Wed, 23 Jan 2019 03:00:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728784AbfAVQA0 (ORCPT ); Tue, 22 Jan 2019 11:00:26 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:57156 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728899AbfAVQA0 (ORCPT ); Tue, 22 Jan 2019 11:00:26 -0500 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFvM5U028192 for ; Tue, 22 Jan 2019 11:00:25 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2q65ejttj6-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:00:25 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:00:20 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0BLj4391378 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:11 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A2462A405D; Tue, 22 Jan 2019 16:00:11 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D5BC8A405F; Tue, 22 Jan 2019 16:00:08 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:08 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 01/13] KVM: PPC: Ultravisor: generic ucall handler plpar_ucall() Date: Tue, 22 Jan 2019 07:59:32 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0008-0000-0000-000002B476A2 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0009-0000-0000-00002220A34A Message-Id: <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=716 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org plpar_ucall() function can now be used to make ucalls with varied number of in and out arguments. It handles 4 out arguments and a lot of in arguments. copies the implementation of plpar_hcall(). Signed-off-by: Ram Pai --- arch/powerpc/platforms/powernv/Makefile | 1 + arch/powerpc/platforms/powernv/uvCall.S | 41 +++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 arch/powerpc/platforms/powernv/uvCall.S diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile index b540ce8e..5ae1df02 100644 --- a/arch/powerpc/platforms/powernv/Makefile +++ b/arch/powerpc/platforms/powernv/Makefile @@ -4,6 +4,7 @@ obj-y += opal-rtc.o opal-nvram.o opal-lpc.o opal-flash.o obj-y += rng.o opal-elog.o opal-dump.o opal-sysparam.o opal-sensor.o obj-y += opal-msglog.o opal-hmi.o opal-power.o opal-irqchip.o obj-y += opal-kmsg.o opal-powercap.o opal-psr.o opal-sensor-groups.o +obj-y += uvCall.o obj-$(CONFIG_SMP) += smp.o subcore.o subcore-asm.o obj-$(CONFIG_PCI) += pci.o pci-ioda.o npu-dma.o pci-ioda-tce.o diff --git a/arch/powerpc/platforms/powernv/uvCall.S b/arch/powerpc/platforms/powernv/uvCall.S new file mode 100644 index 0000000..a5e976a --- /dev/null +++ b/arch/powerpc/platforms/powernv/uvCall.S @@ -0,0 +1,41 @@ +/* + * This file contains the generic code to perform a ultracall. + * + * Copyright IBM Corporation 2019. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include + +_GLOBAL_TOC(plpar_ucall) + + mfcr r0 + stw r0,8(r1) + mr r0,r3 + + std r4,STK_PARAM(R4)(r1) /* Save ret buffer */ + + mr r3,r5 + mr r4,r6 + mr r5,r7 + mr r6,r8 + mr r7,r9 + mr r8,r10 + + sc 2 /* invoke the ultravisor */ + + ld r12,STK_PARAM(R4)(r1) + std r4, 0(r12) + std r5, 8(r12) + std r6, 16(r12) + std r7, 24(r12) + + lwz r0,8(r1) + mtcrf 0xff,r0 + + blr /* return r3 = status */ From patchwork Tue Jan 22 15:59:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029369 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY6f5LSLz9s9G for ; Wed, 23 Jan 2019 03:00:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728828AbfAVQAm (ORCPT ); Tue, 22 Jan 2019 11:00:42 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:35730 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728673AbfAVQAm (ORCPT ); Tue, 22 Jan 2019 11:00:42 -0500 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFtld0096636 for ; Tue, 22 Jan 2019 11:00:41 -0500 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0b-001b2d01.pphosted.com with ESMTP id 2q64k3d0a4-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:00:38 -0500 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:00:25 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0GTS1966584 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:16 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A8E37A4070; Tue, 22 Jan 2019 16:00:16 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 81D4BA406F; Tue, 22 Jan 2019 16:00:13 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:13 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 02/13] KVM: PPC: Ultravisor: Include ultravisor header file. Date: Tue, 22 Jan 2019 07:59:33 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0020-0000-0000-00000309E678 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0021-0000-0000-0000215B1C6C Message-Id: <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=645 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org This file contains the definitions of all ultracalls. Signed-off-by: Ram Pai --- arch/powerpc/include/asm/ucall-api.h | 5 +++++ arch/powerpc/include/uapi/asm/uapi_uvcall.h | 10 ++++++++++ 2 files changed, 15 insertions(+) create mode 100644 arch/powerpc/include/asm/ucall-api.h create mode 100644 arch/powerpc/include/uapi/asm/uapi_uvcall.h diff --git a/arch/powerpc/include/asm/ucall-api.h b/arch/powerpc/include/asm/ucall-api.h new file mode 100644 index 0000000..3833b55 --- /dev/null +++ b/arch/powerpc/include/asm/ucall-api.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_POWERPC_UCALL_API_H +#define _ASM_POWERPC_UCALL_API_H +#include +#endif /* _ASM_POWERPC_UCALL_API_H */ diff --git a/arch/powerpc/include/uapi/asm/uapi_uvcall.h b/arch/powerpc/include/uapi/asm/uapi_uvcall.h new file mode 100644 index 0000000..7e213a1 --- /dev/null +++ b/arch/powerpc/include/uapi/asm/uapi_uvcall.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Ultravisor calls. + * + * Copyright 2018, IBM Corporation. + * + */ +#ifndef UAPI_UC_H +#define UAPI_UC_H +#endif /* #ifndef UAPI_UC_H */ From patchwork Tue Jan 22 15:59:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029370 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY6g4Gx4z9sBn for ; Wed, 23 Jan 2019 03:00:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728673AbfAVQAm (ORCPT ); Tue, 22 Jan 2019 11:00:42 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:8583 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728784AbfAVQAm (ORCPT ); Tue, 22 Jan 2019 11:00:42 -0500 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFvaUT040790 for ; Tue, 22 Jan 2019 11:00:41 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2q6421y7fp-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:00:38 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:00:24 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0MPW42664088 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:22 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E40C4A406F; Tue, 22 Jan 2019 16:00:21 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 24228A407C; Tue, 22 Jan 2019 16:00:18 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:17 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 03/13] KVM: PPC: Ultravisor: Introduce the MSR_S bit Date: Tue, 22 Jan 2019 07:59:34 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0016-0000-0000-00000248E385 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0017-0000-0000-000032A31CB0 Message-Id: <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=454 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Sukadev Bhattiprolu MSR_S bit enables access to secure memory. Signed-off-by: Ram Pai Signed-off-by: Sukadev Bhattiprolu --- arch/powerpc/include/asm/reg.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 1c98ef1..3c3588a 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -38,6 +38,7 @@ #define MSR_TM_LG 32 /* Trans Mem Available */ #define MSR_VEC_LG 25 /* Enable AltiVec */ #define MSR_VSX_LG 23 /* Enable VSX */ +#define MSR_S_LG 22 /* Secure VM bit */ #define MSR_POW_LG 18 /* Enable Power Management */ #define MSR_WE_LG 18 /* Wait State Enable */ #define MSR_TGPR_LG 17 /* TLB Update registers in use */ @@ -71,11 +72,13 @@ #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ +#define MSR_S __MASK(MSR_S_LG) /* Secure state */ #else /* so tests for these bits fail on 32-bit */ #define MSR_SF 0 #define MSR_ISF 0 #define MSR_HV 0 +#define MSR_S 0 #endif /* From patchwork Tue Jan 22 15:59:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029371 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY6k44Wkz9s9G for ; Wed, 23 Jan 2019 03:00:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728822AbfAVQAq (ORCPT ); Tue, 22 Jan 2019 11:00:46 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:40918 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728784AbfAVQAq (ORCPT ); Tue, 22 Jan 2019 11:00:46 -0500 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFvan8040761 for ; Tue, 22 Jan 2019 11:00:44 -0500 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2q6421y7yd-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:00:43 -0500 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:00:38 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0S8n39059614 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:28 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 80A9BA405B; Tue, 22 Jan 2019 16:00:27 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 66C3CA405E; Tue, 22 Jan 2019 16:00:23 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:23 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 04/13] KVM: PPC: Ultravisor: Use UV_WRITE_PATE ucall to register a PATE Date: Tue, 22 Jan 2019 07:59:35 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0008-0000-0000-000002B476A8 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0009-0000-0000-00002220A351 Message-Id: <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Michael Anderson The Nest_MMU needs to know the address of the Partition table (PT). However the PT is in secure memory, and nestMMU cannot access secure memory. Hence hypevisor will continue to use a Partition table of its own. It will have PATE entries for HV and for Normal virtual machines. The same entries are also in the UV's PT. The HV's PT is programmed with the nest MMU. Suggested-by: Ryan Grimm Signed-off-by: Madhavan Srinivasan [device node name to ibm,ultravisor] Signed-off-by: Michael Anderson Signed-off-by: Ram Pai --- arch/powerpc/include/asm/ucall-api.h | 30 +++++++++++++++++++++++++++++ arch/powerpc/include/uapi/asm/uapi_uvcall.h | 2 ++ arch/powerpc/mm/hash_utils_64.c | 4 +++- arch/powerpc/mm/pgtable-book3s64.c | 29 ++++++++++++++++++++++++++-- arch/powerpc/mm/pgtable-radix.c | 10 +++++++--- 5 files changed, 69 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/ucall-api.h b/arch/powerpc/include/asm/ucall-api.h index 3833b55..f411dcb 100644 --- a/arch/powerpc/include/asm/ucall-api.h +++ b/arch/powerpc/include/asm/ucall-api.h @@ -1,5 +1,35 @@ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_POWERPC_UCALL_API_H #define _ASM_POWERPC_UCALL_API_H + #include + +#ifndef __ASSEMBLY__ + +#include +#include + +extern unsigned int smf_state; +static inline bool smf_enabled(void) +{ + unsigned long smf; + + if (!smf_state) { + smf = of_get_flat_dt_subnode_by_name(0, "ibm,ultravisor"); + smf_state = (smf == -FDT_ERR_NOTFOUND) ? 1 : 2; + } + return (smf_state == 2); +} + +#define PLPAR_UCALL_BUFSIZE 4 +long plpar_ucall(unsigned long opcode, unsigned long *retbuf, ...); + +static inline int uv_register_pate(u64 lpid, u64 dw0, u64 dw1) +{ + unsigned long retbuf[PLPAR_UCALL_BUFSIZE]; + + return plpar_ucall(UV_WRITE_PATE, retbuf, lpid, dw0, dw1); +} + +#endif /* __ASSEMBLY__ */ #endif /* _ASM_POWERPC_UCALL_API_H */ diff --git a/arch/powerpc/include/uapi/asm/uapi_uvcall.h b/arch/powerpc/include/uapi/asm/uapi_uvcall.h index 7e213a1..7f018cf 100644 --- a/arch/powerpc/include/uapi/asm/uapi_uvcall.h +++ b/arch/powerpc/include/uapi/asm/uapi_uvcall.h @@ -7,4 +7,6 @@ */ #ifndef UAPI_UC_H #define UAPI_UC_H + +#define UV_WRITE_PATE 0xf104 #endif /* #ifndef UAPI_UC_H */ diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 0cc7fbc..6d0eef6 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -64,6 +64,7 @@ #include #include #include +#include #ifdef DEBUG #define DBG(fmt...) udbg_printf(fmt) @@ -1051,9 +1052,10 @@ void hash__early_init_mmu_secondary(void) if (!cpu_has_feature(CPU_FTR_ARCH_300)) mtspr(SPRN_SDR1, _SDR1); - else + else if (!smf_enabled()) mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); + } /* Initialize SLB */ slb_initialize(); diff --git a/arch/powerpc/mm/pgtable-book3s64.c b/arch/powerpc/mm/pgtable-book3s64.c index f3c31f5..ba6b34d 100644 --- a/arch/powerpc/mm/pgtable-book3s64.c +++ b/arch/powerpc/mm/pgtable-book3s64.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "mmu_decl.h" #include @@ -206,11 +207,23 @@ void __init mmu_partition_table_init(void) * 64 K size. */ ptcr = __pa(partition_tb) | (PATB_SIZE_SHIFT - 12); - mtspr(SPRN_PTCR, ptcr); + /* + * Ultravisor creates and manages partition table if SMF + * is enabled. + */ + if (!smf_enabled()) + mtspr(SPRN_PTCR, ptcr); + + /* + * Since nestMMU cannot access secure memory. Create + * and manage our own partition table. This table + * contains entries for nonsecure and hypervisor + * partition. + */ powernv_set_nmmu_ptcr(ptcr); } -void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, +static void __mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, unsigned long dw1) { unsigned long old = be64_to_cpu(partition_tb[lpid].patb0); @@ -238,6 +251,18 @@ void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, /* do we need fixup here ?*/ asm volatile("eieio; tlbsync; ptesync" : : : "memory"); } + +void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, + unsigned long dw1) +{ + pr_info("%s: SMF Regitered PATE for Hypervisor dw0 = 0x%lx dw1 = 0x%lx ", __func__, dw0, dw1); + if (smf_enabled()) + uv_register_pate(lpid, dw0, dw1); + + __mmu_partition_table_set_entry(lpid, dw0, dw1); + return; +} + EXPORT_SYMBOL_GPL(mmu_partition_table_set_entry); static pmd_t *get_pmd_from_cache(struct mm_struct *mm) diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c index 9311560..bcc8398 100644 --- a/arch/powerpc/mm/pgtable-radix.c +++ b/arch/powerpc/mm/pgtable-radix.c @@ -29,11 +29,13 @@ #include #include #include +#include #include unsigned int mmu_pid_bits; unsigned int mmu_base_pid; +unsigned int smf_state; static int native_register_process_table(unsigned long base, unsigned long pg_sz, unsigned long table_size) @@ -623,8 +625,9 @@ void radix__early_init_mmu_secondary(void) lpcr = mfspr(SPRN_LPCR); mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); - mtspr(SPRN_PTCR, - __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); + if (!smf_enabled()) + mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12)); + radix_init_amor(); } radix_init_iamr(); @@ -641,7 +644,8 @@ void radix__mmu_cleanup_all(void) if (!firmware_has_feature(FW_FEATURE_LPAR)) { lpcr = mfspr(SPRN_LPCR); mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT); - mtspr(SPRN_PTCR, 0); + if (!smf_enabled()) + mtspr(SPRN_PTCR, 0); powernv_set_nmmu_ptcr(0); radix__flush_tlb_all(); } From patchwork Tue Jan 22 15:59:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029372 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY6p5cxPz9sD4 for ; Wed, 23 Jan 2019 03:00:50 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728886AbfAVQAu (ORCPT ); Tue, 22 Jan 2019 11:00:50 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:51404 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728784AbfAVQAu (ORCPT ); Tue, 22 Jan 2019 11:00:50 -0500 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFt5oE120254 for ; Tue, 22 Jan 2019 11:00:49 -0500 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0a-001b2d01.pphosted.com with ESMTP id 2q65xt95v5-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:00:47 -0500 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:00:40 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0XNT24051754 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:33 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A7584A4069; Tue, 22 Jan 2019 16:00:32 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DD6E8A4070; Tue, 22 Jan 2019 16:00:28 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:28 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 05/13] KVM: PPC: Ultravisor: Flush partition tlb cache, only if smf is not enabled. Date: Tue, 22 Jan 2019 07:59:36 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0020-0000-0000-00000309E682 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0021-0000-0000-0000215B1C76 Message-Id: <1548172784-27414-6-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=903 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org Ultravisor is responsible for flushing the tlb cache, since it manages the PATE entries. Hence skip tlb flush, if a Ultravisor is enabled on the system. Signed-off-by: Ram Pai --- arch/powerpc/mm/pgtable-book3s64.c | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/mm/pgtable-book3s64.c b/arch/powerpc/mm/pgtable-book3s64.c index ba6b34d..1d79b06 100644 --- a/arch/powerpc/mm/pgtable-book3s64.c +++ b/arch/powerpc/mm/pgtable-book3s64.c @@ -223,21 +223,9 @@ void __init mmu_partition_table_init(void) powernv_set_nmmu_ptcr(ptcr); } -static void __mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, - unsigned long dw1) +static void flush_partition(unsigned int lpid, unsigned long dw0) { - unsigned long old = be64_to_cpu(partition_tb[lpid].patb0); - - partition_tb[lpid].patb0 = cpu_to_be64(dw0); - partition_tb[lpid].patb1 = cpu_to_be64(dw1); - - /* - * Global flush of TLBs and partition table caches for this lpid. - * The type of flush (hash or radix) depends on what the previous - * use of this partition ID was, not the new use. - */ - asm volatile("ptesync" : : : "memory"); - if (old & PATB_HR) { + if (dw0 & PATB_HR) { asm volatile(PPC_TLBIE_5(%0,%1,2,0,1) : : "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid)); asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : : @@ -252,10 +240,28 @@ static void __mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0 asm volatile("eieio; tlbsync; ptesync" : : : "memory"); } +static void __mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, + unsigned long dw1) +{ + unsigned long old = be64_to_cpu(partition_tb[lpid].patb0); + + partition_tb[lpid].patb0 = cpu_to_be64(dw0); + partition_tb[lpid].patb1 = cpu_to_be64(dw1); + + /* + * Global flush of TLBs and partition table caches for this lpid. + * The type of flush (hash or radix) depends on what the previous + * use of this partition ID was, not the new use. + */ + if (!smf_enabled()) + flush_partition(lpid, old); +} + void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, unsigned long dw1) { - pr_info("%s: SMF Regitered PATE for Hypervisor dw0 = 0x%lx dw1 = 0x%lx ", __func__, dw0, dw1); + pr_info("%s: SMF Regitered PATE dw0 = 0x%lx dw1 = 0x%lx lpid=%x", + __func__, dw0, dw1, lpid); if (smf_enabled()) uv_register_pate(lpid, dw0, dw1); From patchwork Tue Jan 22 15:59:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029373 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY6w4h36z9s9G for ; Wed, 23 Jan 2019 03:00:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728895AbfAVQA4 (ORCPT ); Tue, 22 Jan 2019 11:00:56 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:60650 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728828AbfAVQA4 (ORCPT ); Tue, 22 Jan 2019 11:00:56 -0500 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFvIrm045095 for ; Tue, 22 Jan 2019 11:00:54 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0b-001b2d01.pphosted.com with ESMTP id 2q6540ky02-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:00:52 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:00:47 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0cCY26935374 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:38 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8D924A405F; Tue, 22 Jan 2019 16:00:37 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1CE82A4070; Tue, 22 Jan 2019 16:00:34 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:33 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 06/13] KVM: PPC: Ultravisor: UV_RESTRICTED_SPR_WRITE ucall Date: Tue, 22 Jan 2019 07:59:37 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-6-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> <1548172784-27414-6-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-4275-0000-0000-00000302A0F0 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-4276-0000-0000-00003810D2AC Message-Id: <1548172784-27414-7-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=532 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org Introduce UV_RESTRICTED_SPR_WRITE. Hypervisor loses access to some registers when Ultravisor is enabled. Hypervisor can request write access to those registers using UV_RESTRICTED_SPR_WRITE ucall. Signed-off-by: Ram Pai --- arch/powerpc/include/asm/ucall-api.h | 6 ++++++ arch/powerpc/include/uapi/asm/uapi_uvcall.h | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/powerpc/include/asm/ucall-api.h b/arch/powerpc/include/asm/ucall-api.h index f411dcb..7723b4e 100644 --- a/arch/powerpc/include/asm/ucall-api.h +++ b/arch/powerpc/include/asm/ucall-api.h @@ -31,5 +31,11 @@ static inline int uv_register_pate(u64 lpid, u64 dw0, u64 dw1) return plpar_ucall(UV_WRITE_PATE, retbuf, lpid, dw0, dw1); } +static inline int uv_restricted_spr_write(u64 reg, u64 val) +{ + unsigned long retbuf[PLPAR_UCALL_BUFSIZE]; + + return plpar_ucall(UV_RESTRICTED_SPR_WRITE, retbuf, reg, val); +} #endif /* __ASSEMBLY__ */ #endif /* _ASM_POWERPC_UCALL_API_H */ diff --git a/arch/powerpc/include/uapi/asm/uapi_uvcall.h b/arch/powerpc/include/uapi/asm/uapi_uvcall.h index 7f018cf..d76dd1f 100644 --- a/arch/powerpc/include/uapi/asm/uapi_uvcall.h +++ b/arch/powerpc/include/uapi/asm/uapi_uvcall.h @@ -9,4 +9,5 @@ #define UAPI_UC_H #define UV_WRITE_PATE 0xf104 +#define UV_RESTRICTED_SPR_WRITE 0xf108 #endif /* #ifndef UAPI_UC_H */ From patchwork Tue Jan 22 15:59:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029374 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY6z4MTBz9s9G for ; Wed, 23 Jan 2019 03:00:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728899AbfAVQA7 (ORCPT ); Tue, 22 Jan 2019 11:00:59 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:43266 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728828AbfAVQA7 (ORCPT ); Tue, 22 Jan 2019 11:00:59 -0500 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFtj7A096471 for ; Tue, 22 Jan 2019 11:00:57 -0500 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0b-001b2d01.pphosted.com with ESMTP id 2q64k3d1ef-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:00:57 -0500 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:00:50 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0fH663242456 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:41 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A2F3CA4070; Tue, 22 Jan 2019 16:00:41 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 12766A4076; Tue, 22 Jan 2019 16:00:39 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:38 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 07/13] KVM: PPC: Ultravisor: UV_RESTRICTED_SPR_READ ucall Date: Tue, 22 Jan 2019 07:59:38 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-7-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> <1548172784-27414-6-git-send-email-linuxram@us.ibm.com> <1548172784-27414-7-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0020-0000-0000-00000309E68E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0021-0000-0000-0000215B1C84 Message-Id: <1548172784-27414-8-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=571 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org Introduce UV_RESTRICTED_SPR_READ. Hypervisor loses previlege to access some registers when Ultravisor is enabled. Hypervisor can request read access to those registers using UV_RESTRICTED_SPR_READ ucall. Signed-off-by: Ram Pai --- arch/powerpc/include/asm/ucall-api.h | 11 +++++++++++ arch/powerpc/include/uapi/asm/uapi_uvcall.h | 1 + 2 files changed, 12 insertions(+) diff --git a/arch/powerpc/include/asm/ucall-api.h b/arch/powerpc/include/asm/ucall-api.h index 7723b4e..ffafd9e 100644 --- a/arch/powerpc/include/asm/ucall-api.h +++ b/arch/powerpc/include/asm/ucall-api.h @@ -37,5 +37,16 @@ static inline int uv_restricted_spr_write(u64 reg, u64 val) return plpar_ucall(UV_RESTRICTED_SPR_WRITE, retbuf, reg, val); } +static inline int uv_restricted_spr_read(u64 reg, u64 *val) +{ + long rc; + unsigned long retbuf[PLPAR_UCALL_BUFSIZE]; + + rc = plpar_ucall(UV_RESTRICTED_SPR_READ, retbuf, reg); + + *val = retbuf[0]; + return rc; +} + #endif /* __ASSEMBLY__ */ #endif /* _ASM_POWERPC_UCALL_API_H */ diff --git a/arch/powerpc/include/uapi/asm/uapi_uvcall.h b/arch/powerpc/include/uapi/asm/uapi_uvcall.h index d76dd1f..bbcd026 100644 --- a/arch/powerpc/include/uapi/asm/uapi_uvcall.h +++ b/arch/powerpc/include/uapi/asm/uapi_uvcall.h @@ -10,4 +10,5 @@ #define UV_WRITE_PATE 0xf104 #define UV_RESTRICTED_SPR_WRITE 0xf108 +#define UV_RESTRICTED_SPR_READ 0xf10C #endif /* #ifndef UAPI_UC_H */ From patchwork Tue Jan 22 15:59:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029375 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY7732XPz9sD9 for ; Wed, 23 Jan 2019 03:01:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728784AbfAVQBG (ORCPT ); Tue, 22 Jan 2019 11:01:06 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:3737 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728828AbfAVQBG (ORCPT ); Tue, 22 Jan 2019 11:01:06 -0500 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFvI1Q045079 for ; Tue, 22 Jan 2019 11:01:03 -0500 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0b-001b2d01.pphosted.com with ESMTP id 2q6540kygv-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:01:01 -0500 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:00:55 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0k9Q40697950 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:46 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 50CE7A4055; Tue, 22 Jan 2019 16:00:46 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1F1E5A4076; Tue, 22 Jan 2019 16:00:43 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:42 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 08/13] KVM: PPC: Ultravisor: fix mtspr and mfspr Date: Tue, 22 Jan 2019 07:59:39 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-8-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> <1548172784-27414-6-git-send-email-linuxram@us.ibm.com> <1548172784-27414-7-git-send-email-linuxram@us.ibm.com> <1548172784-27414-8-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0028-0000-0000-0000033C982B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0029-0000-0000-000023F9D29B Message-Id: <1548172784-27414-9-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org fix mtspr and mfspr to conditionally make ucalls if the target register is previleged. Signed-off-by: Ram Pai Signed-off-by: Sukadev Bhattiprolu --- arch/powerpc/include/asm/reg.h | 30 ++++++++++++++---- arch/powerpc/include/asm/ucall-api.h | 8 ++++- arch/powerpc/kernel/paca.c | 4 +-- arch/powerpc/oprofile/op_model_pa6t.c | 4 +-- arch/powerpc/perf/core-book3s.c | 8 ++--- arch/powerpc/xmon/xmon.c | 58 +++++++++++++++++++---------------- 6 files changed, 70 insertions(+), 42 deletions(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 3c3588a..eab2c19 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1350,20 +1350,38 @@ #define __MTMSR "mtmsr" #endif +#include + static inline void mtmsr_isync(unsigned long val) { asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : : "r" (val), "i" (CPU_FTR_ARCH_206) : "memory"); } -#define mfspr(rn) ({unsigned long rval; \ - asm volatile("mfspr %0," __stringify(rn) \ - : "=r" (rval)); rval;}) +#ifndef mfspr +static inline __attribute__((always_inline)) +u64 mfspr(const unsigned int spr) +{ + u64 val; + if (is_uv_register(spr)) + uv_restricted_spr_read(spr, &val); + else + asm volatile("mfspr %0,%1" : "=r"(val) : "i"(spr) : "memory"); + return val; +} +#endif + #ifndef mtspr -#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \ - : "r" ((unsigned long)(v)) \ - : "memory") +static inline __attribute__((always_inline)) +void mtspr(const unsigned int rn, unsigned long v) +{ + if (is_uv_register(rn)) + uv_restricted_spr_write(rn, (u64)v); + else + asm volatile("mtspr %0,%1" : : "i"(rn), "r"(v) : "memory"); +} #endif + #define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",0" : \ : : "memory") diff --git a/arch/powerpc/include/asm/ucall-api.h b/arch/powerpc/include/asm/ucall-api.h index ffafd9e..82d8edd 100644 --- a/arch/powerpc/include/asm/ucall-api.h +++ b/arch/powerpc/include/asm/ucall-api.h @@ -21,6 +21,12 @@ static inline bool smf_enabled(void) return (smf_state == 2); } +static inline bool is_uv_register(u64 reg) +{ + return ((reg == SPRN_DAWR || reg == SPRN_DAWRX || reg == SPRN_CIABR) && + smf_enabled()); +} + #define PLPAR_UCALL_BUFSIZE 4 long plpar_ucall(unsigned long opcode, unsigned long *retbuf, ...); @@ -48,5 +54,5 @@ static inline int uv_restricted_spr_read(u64 reg, u64 *val) return rc; } -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLY__ */ #endif /* _ASM_POWERPC_UCALL_API_H */ diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c index 913bfca..37931aa 100644 --- a/arch/powerpc/kernel/paca.c +++ b/arch/powerpc/kernel/paca.c @@ -183,9 +183,9 @@ void setup_paca(struct paca_struct *new_paca) * applied */ if (early_cpu_has_feature(CPU_FTR_HVMODE)) - mtspr(SPRN_SPRG_HPACA, local_paca); + mtspr(SPRN_SPRG_HPACA, (u64)local_paca); #endif - mtspr(SPRN_SPRG_PACA, local_paca); + mtspr(SPRN_SPRG_PACA, (u64)local_paca); } diff --git a/arch/powerpc/oprofile/op_model_pa6t.c b/arch/powerpc/oprofile/op_model_pa6t.c index a114a7c..386cd53 100644 --- a/arch/powerpc/oprofile/op_model_pa6t.c +++ b/arch/powerpc/oprofile/op_model_pa6t.c @@ -151,9 +151,9 @@ static int pa6t_cpu_setup(struct op_counter_config *ctr) /* program selected programmable events in */ mtspr(SPRN_PA6T_MMCR1, mmcr1); - pr_debug("setup on cpu %d, mmcr0 %016lx\n", smp_processor_id(), + pr_debug("setup on cpu %d, mmcr0 %016llx\n", smp_processor_id(), mfspr(SPRN_PA6T_MMCR0)); - pr_debug("setup on cpu %d, mmcr1 %016lx\n", smp_processor_id(), + pr_debug("setup on cpu %d, mmcr1 %016llx\n", smp_processor_id(), mfspr(SPRN_PA6T_MMCR1)); return 0; diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index b072300..b3cc5cd 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -834,7 +834,7 @@ void perf_event_print_debug(void) pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", pmcs[4], pmcs[5], pmcs[6], pmcs[7]); - pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", + pr_info("MMCR0: %016llx MMCR1: %016llx MMCRA: %016llx\n", mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); sdar = sier = 0; @@ -845,13 +845,13 @@ void perf_event_print_debug(void) sier = mfspr(SPRN_SIER); if (ppmu->flags & PPMU_ARCH_207S) { - pr_info("MMCR2: %016lx EBBHR: %016lx\n", + pr_info("MMCR2: %016llx EBBHR: %016llx\n", mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); - pr_info("EBBRR: %016lx BESCR: %016lx\n", + pr_info("EBBRR: %016llx BESCR: %016llx\n", mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); } #endif - pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", + pr_info("SIAR: %016llx SDAR: %016lx SIER: %016lx\n", mfspr(SPRN_SIAR), sdar, sier); local_irq_restore(flags); diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index 757b849..cf811e6 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -192,8 +192,12 @@ static void xmon_print_symbol(unsigned long address, const char *mid, #ifdef CONFIG_PPC64 #define REG "%.16lx" +#define REG16 "%.16llx" +#define REG8 "%.8llx" #else #define REG "%.8lx" +#define REG16 REG +#define REG8 REG #endif #ifdef __LITTLE_ENDIAN__ @@ -1798,25 +1802,25 @@ static void dump_206_sprs(void) /* Actually some of these pre-date 2.06, but whatevs */ - printf("srr0 = %.16lx srr1 = %.16lx dsisr = %.8lx\n", + printf("srr0 = "REG16" srr1 = "REG16" dsisr = "REG8"\n", mfspr(SPRN_SRR0), mfspr(SPRN_SRR1), mfspr(SPRN_DSISR)); - printf("dscr = %.16lx ppr = %.16lx pir = %.8lx\n", + printf("dscr = "REG16" ppr = "REG16" pir = "REG16"\n", mfspr(SPRN_DSCR), mfspr(SPRN_PPR), mfspr(SPRN_PIR)); - printf("amr = %.16lx uamor = %.16lx\n", + printf("amr = "REG16" uamor = "REG16"\n", mfspr(SPRN_AMR), mfspr(SPRN_UAMOR)); if (!(mfmsr() & MSR_HV)) return; - printf("sdr1 = %.16lx hdar = %.16lx hdsisr = %.8lx\n", + printf("sdr1 = "REG16" hdar = "REG16" hdsisr = "REG8"\n", mfspr(SPRN_SDR1), mfspr(SPRN_HDAR), mfspr(SPRN_HDSISR)); - printf("hsrr0 = %.16lx hsrr1 = %.16lx hdec = %.16lx\n", + printf("hsrr0 = "REG16" hsrr1 = "REG16" hdec = "REG16"\n", mfspr(SPRN_HSRR0), mfspr(SPRN_HSRR1), mfspr(SPRN_HDEC)); - printf("lpcr = %.16lx pcr = %.16lx lpidr = %.8lx\n", + printf("lpcr = "REG16" pcr = "REG16" lpidr = "REG16"\n", mfspr(SPRN_LPCR), mfspr(SPRN_PCR), mfspr(SPRN_LPID)); - printf("hsprg0 = %.16lx hsprg1 = %.16lx amor = %.16lx\n", + printf("hsprg0 = "REG16" hsprg1 = "REG16" amor = "REG16"\n", mfspr(SPRN_HSPRG0), mfspr(SPRN_HSPRG1), mfspr(SPRN_AMOR)); - printf("dabr = %.16lx dabrx = %.16lx\n", + printf("dabr = "REG16" dabrx = "REG16"\n", mfspr(SPRN_DABR), mfspr(SPRN_DABRX)); #endif } @@ -1829,39 +1833,39 @@ static void dump_207_sprs(void) if (!cpu_has_feature(CPU_FTR_ARCH_207S)) return; - printf("dpdes = %.16lx tir = %.16lx cir = %.8lx\n", + printf("dpdes = "REG16" tir = "REG16" cir = "REG8"\n", mfspr(SPRN_DPDES), mfspr(SPRN_TIR), mfspr(SPRN_CIR)); - printf("fscr = %.16lx tar = %.16lx pspb = %.8lx\n", + printf("fscr = "REG16" tar = "REG16" pspb = "REG16"\n", mfspr(SPRN_FSCR), mfspr(SPRN_TAR), mfspr(SPRN_PSPB)); msr = mfmsr(); if (msr & MSR_TM) { /* Only if TM has been enabled in the kernel */ - printf("tfhar = %.16lx tfiar = %.16lx texasr = %.16lx\n", + printf("tfhar = "REG16" tfiar = "REG16" texasr = "REG16"\n", mfspr(SPRN_TFHAR), mfspr(SPRN_TFIAR), mfspr(SPRN_TEXASR)); } - printf("mmcr0 = %.16lx mmcr1 = %.16lx mmcr2 = %.16lx\n", + printf("mmcr0 = "REG16" mmcr1 = "REG16" mmcr2 = "REG16"\n", mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCR2)); - printf("pmc1 = %.8lx pmc2 = %.8lx pmc3 = %.8lx pmc4 = %.8lx\n", + printf("pmc1 = "REG8" pmc2 = "REG8" pmc3 = "REG8" pmc4 = "REG8"\n", mfspr(SPRN_PMC1), mfspr(SPRN_PMC2), mfspr(SPRN_PMC3), mfspr(SPRN_PMC4)); - printf("mmcra = %.16lx siar = %.16lx pmc5 = %.8lx\n", + printf("mmcra = "REG16" siar = "REG16" pmc5 = "REG8"\n", mfspr(SPRN_MMCRA), mfspr(SPRN_SIAR), mfspr(SPRN_PMC5)); - printf("sdar = %.16lx sier = %.16lx pmc6 = %.8lx\n", + printf("sdar = "REG16" sier = "REG16" pmc6 = "REG16"\n", mfspr(SPRN_SDAR), mfspr(SPRN_SIER), mfspr(SPRN_PMC6)); - printf("ebbhr = %.16lx ebbrr = %.16lx bescr = %.16lx\n", + printf("ebbhr = "REG16" ebbrr = "REG16" bescr = "REG16"\n", mfspr(SPRN_EBBHR), mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); - printf("iamr = %.16lx\n", mfspr(SPRN_IAMR)); + printf("iamr = "REG16"\n", mfspr(SPRN_IAMR)); if (!(msr & MSR_HV)) return; - printf("hfscr = %.16lx dhdes = %.16lx rpr = %.16lx\n", + printf("hfscr = "REG16" dhdes = "REG16" rpr = "REG16"\n", mfspr(SPRN_HFSCR), mfspr(SPRN_DHDES), mfspr(SPRN_RPR)); - printf("dawr = %.16lx dawrx = %.16lx ciabr = %.16lx\n", + printf("dawr = "REG16" dawrx = "REG16" ciabr = "REG16"\n", mfspr(SPRN_DAWR), mfspr(SPRN_DAWRX), mfspr(SPRN_CIABR)); #endif } @@ -1874,16 +1878,16 @@ static void dump_300_sprs(void) if (!cpu_has_feature(CPU_FTR_ARCH_300)) return; - printf("pidr = %.16lx tidr = %.16lx\n", + printf("pidr = "REG16" tidr = "REG16"\n", mfspr(SPRN_PID), mfspr(SPRN_TIDR)); - printf("asdr = %.16lx psscr = %.16lx\n", + printf("asdr = "REG16" psscr = "REG16"\n", mfspr(SPRN_ASDR), hv ? mfspr(SPRN_PSSCR) : mfspr(SPRN_PSSCR_PR)); if (!hv) return; - printf("ptcr = %.16lx\n", + printf("ptcr = "REG16"\n", mfspr(SPRN_PTCR)); #endif } @@ -1930,14 +1934,14 @@ static void super_regs(void) asm("mr %0,1" : "=r" (sp) :); asm("mr %0,2" : "=r" (toc) :); - printf("msr = "REG" sprg0 = "REG"\n", + printf("msr = "REG" sprg0 = "REG16"\n", mfmsr(), mfspr(SPRN_SPRG0)); - printf("pvr = "REG" sprg1 = "REG"\n", + printf("pvr = "REG16" sprg1 = "REG16"\n", mfspr(SPRN_PVR), mfspr(SPRN_SPRG1)); - printf("dec = "REG" sprg2 = "REG"\n", + printf("dec = "REG16" sprg2 = "REG16"\n", mfspr(SPRN_DEC), mfspr(SPRN_SPRG2)); - printf("sp = "REG" sprg3 = "REG"\n", sp, mfspr(SPRN_SPRG3)); - printf("toc = "REG" dar = "REG"\n", toc, mfspr(SPRN_DAR)); + printf("sp = "REG" sprg3 = "REG16"\n", sp, mfspr(SPRN_SPRG3)); + printf("toc = "REG" dar = "REG16"\n", toc, mfspr(SPRN_DAR)); dump_206_sprs(); dump_207_sprs(); From patchwork Tue Jan 22 15:59:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029376 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY791S4dz9sNC for ; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:01:00 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0p7R1442222 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:51 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 67E15A404D; Tue, 22 Jan 2019 16:00:51 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B03DAA4051; Tue, 22 Jan 2019 16:00:47 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:47 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 09/13] KVM: PPC: Ultravisor: Return to UV for hcalls from SVM Date: Tue, 22 Jan 2019 07:59:40 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-9-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> <1548172784-27414-6-git-send-email-linuxram@us.ibm.com> <1548172784-27414-7-git-send-email-linuxram@us.ibm.com> <1548172784-27414-8-git-send-email-linuxram@us.ibm.com> <1548172784-27414-9-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0008-0000-0000-000002B476BC X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0009-0000-0000-00002220A365 Message-Id: <1548172784-27414-10-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=745 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Sukadev Bhattiprolu All hcalls from a secure VM go to the ultravisor from where they are reflected into the HV. When we (HV) complete processing such hcalls, we should return to the UV rather than to the guest kernel. Before reflecting the hcall, the ultravisor sets the MSR_S bit in SRR1 (which gets copied into HSRR1 in kvmppc_interrupt_hv()). If the S bit is set in HSRR1, return to ultravisor (using UV_RETURN ucall). Otherwise return to the guest. Thanks to input from Ram Pai and Mike Anderson. Signed-off-by: Sukadev Bhattiprolu Signed-off-by: Ram Pai [fix: UV_RETURN token number] --- arch/powerpc/include/uapi/asm/uapi_uvcall.h | 1 + arch/powerpc/kvm/book3s_hv_rmhandlers.S | 27 ++++++++++++++++++++++++--- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/include/uapi/asm/uapi_uvcall.h b/arch/powerpc/include/uapi/asm/uapi_uvcall.h index bbcd026..b657af6 100644 --- a/arch/powerpc/include/uapi/asm/uapi_uvcall.h +++ b/arch/powerpc/include/uapi/asm/uapi_uvcall.h @@ -11,4 +11,5 @@ #define UV_WRITE_PATE 0xf104 #define UV_RESTRICTED_SPR_WRITE 0xf108 #define UV_RESTRICTED_SPR_READ 0xf10C +#define UV_RETURN 0xf11C #endif /* #ifndef UAPI_UC_H */ diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index 9b8d50a..6f2f786 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -35,6 +35,7 @@ #include #include #include +#include /* Sign-extend HDEC if not on POWER9 */ #define EXTEND_HDEC(reg) \ @@ -1092,15 +1093,12 @@ BEGIN_FTR_SECTION END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) ld r5, VCPU_LR(r4) - ld r6, VCPU_CR(r4) mtlr r5 - mtcr r6 ld r1, VCPU_GPR(R1)(r4) ld r2, VCPU_GPR(R2)(r4) ld r3, VCPU_GPR(R3)(r4) ld r5, VCPU_GPR(R5)(r4) - ld r6, VCPU_GPR(R6)(r4) ld r7, VCPU_GPR(R7)(r4) ld r8, VCPU_GPR(R8)(r4) ld r9, VCPU_GPR(R9)(r4) @@ -1119,10 +1117,33 @@ BEGIN_FTR_SECTION mtspr SPRN_HDSISR, r0 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) + mfspr r6, SPRN_HSRR1 + andis. r6, r6, MSR_S@high + cmplwi r6, 0 + bne ret_to_ultra; + + lwz r6, VCPU_CR(r4) + mtcr r6 + + ld r6, VCPU_GPR(R6)(r4) ld r0, VCPU_GPR(R0)(r4) ld r4, VCPU_GPR(R4)(r4) HRFI_TO_GUEST b . +/* + * The hcall we just completed was from Ultravisor. Use UV_RETURN + * ultra call to return to the Ultravisor. Results from the hcall + * are already in the appropriate registers (r3:12), except for + * R6 which we used as a temporary register above. Restore that, + * and set R0 to the ucall number (UV_RETURN). + */ +ret_to_ultra: + lwz r6, VCPU_CR(r4) + mtcr r6 + LOAD_REG_IMMEDIATE(r0, UV_RETURN) + ld r6, VCPU_GPR(R6)(r4) + ld r4, VCPU_GPR(R4)(r4) + sc 2 /* * Enter the guest on a P9 or later system where we have exactly From patchwork Tue Jan 22 15:59:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029377 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY7F2ZBKz9sD9 for ; Wed, 23 Jan 2019 03:01:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728952AbfAVQBN (ORCPT ); Tue, 22 Jan 2019 11:01:13 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:47128 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728895AbfAVQBM (ORCPT ); Tue, 22 Jan 2019 11:01:12 -0500 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFt344013723 for ; Tue, 22 Jan 2019 11:01:11 -0500 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0a-001b2d01.pphosted.com with ESMTP id 2q65b9k5c5-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:01:10 -0500 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 22 Jan 2019 16:01:08 -0000 Received: from b06cxnps3074.portsmouth.uk.ibm.com (9.149.109.194) by e06smtp05.uk.ibm.com (192.168.101.135) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:01:06 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG0vGf34340884 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:00:57 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0E062A4040; Tue, 22 Jan 2019 16:00:57 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0EEDEA4051; Tue, 22 Jan 2019 16:00:53 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:52 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 10/13] KVM: PPC: Ultravisor: Add PPC_KVM_UV config option Date: Tue, 22 Jan 2019 07:59:41 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-10-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> <1548172784-27414-6-git-send-email-linuxram@us.ibm.com> <1548172784-27414-7-git-send-email-linuxram@us.ibm.com> <1548172784-27414-8-git-send-email-linuxram@us.ibm.com> <1548172784-27414-9-git-send-email-linuxram@us.ibm.com> <1548172784-27414-10-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0020-0000-0000-00000309E696 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0021-0000-0000-0000215B1C8C Message-Id: <1548172784-27414-11-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=582 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Anshuman Khandual CONFIG_PPC_KVM_UV enables support for ultravisor. Signed-off-by: Anshuman Khandual Signed-off-by: Bharata B Rao Signed-off-by: Ram Pai --- arch/powerpc/Kconfig | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 2890d36..8c03857 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -447,6 +447,24 @@ config PPC_TRANSACTIONAL_MEM ---help--- Support user-mode Transactional Memory on POWERPC. +config PPC_KVM_UV + bool "KVM support for Ultravisor on POWER" + depends on KVM_BOOK3S_HV_POSSIBLE + select HMM_MIRROR + select HMM + select ZONE_DEVICE + select MIGRATE_VMA_HELPER + select DEV_PAGEMAP_OPS + select DEVICE_PRIVATE + select MEMORY_HOTPLUG + select MEMORY_HOTREMOVE + default n + help + Paravirtualize KVM. There are certain POWER platforms + which support Protected Execution Facility to enable Secure Virtual Machines. + + If unsure, say "N". + config LD_HEAD_STUB_CATCH bool "Reserve 256 bytes to cope with linker stubs in HEAD text" if EXPERT depends on PPC64 From patchwork Tue Jan 22 15:59:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029378 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY7N6r0xz9s9G for ; Wed, 23 Jan 2019 03:01:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728828AbfAVQBU (ORCPT ); Tue, 22 Jan 2019 11:01:20 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:59964 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728784AbfAVQBU (ORCPT ); Tue, 22 Jan 2019 11:01:20 -0500 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFt6ud120396 for ; Tue, 22 Jan 2019 11:01:19 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2q65xt9782-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:01:17 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:01:10 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG119162783566 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:01:01 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4529BA404D; Tue, 22 Jan 2019 16:01:01 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 61751A406D; Tue, 22 Jan 2019 16:00:58 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:00:58 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 11/13] KVM: PPC: Ultravisor: Check for MSR_S during hv_reset_msr Date: Tue, 22 Jan 2019 07:59:42 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-11-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> <1548172784-27414-6-git-send-email-linuxram@us.ibm.com> <1548172784-27414-7-git-send-email-linuxram@us.ibm.com> <1548172784-27414-8-git-send-email-linuxram@us.ibm.com> <1548172784-27414-9-git-send-email-linuxram@us.ibm.com> <1548172784-27414-10-git-send-email-linuxram@us.ibm.com> <1548172784-27414-11-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0016-0000-0000-00000248E3A9 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0017-0000-0000-000032A31CDA Message-Id: <1548172784-27414-12-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=982 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Michael Anderson - Check for MSR_S so that kvmppc_set_msr will include. Prior to this change return to guest would not have the S bit set. - Patch based on comment from Paul Mackerras Signed-off-by: Michael Anderson --- arch/powerpc/kvm/book3s_64_mmu_hv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c index bd2dcfb..b7077cd 100644 --- a/arch/powerpc/kvm/book3s_64_mmu_hv.c +++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c @@ -295,6 +295,7 @@ static void kvmppc_mmu_book3s_64_hv_reset_msr(struct kvm_vcpu *vcpu) msr |= MSR_TS_S; else msr |= vcpu->arch.shregs.msr & MSR_TS_MASK; + msr |= vcpu->arch.shregs.msr & MSR_S; kvmppc_set_msr(vcpu, msr); } From patchwork Tue Jan 22 15:59:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029379 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY7Y4kxVz9s9h for ; Wed, 23 Jan 2019 03:01:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728895AbfAVQB3 (ORCPT ); Tue, 22 Jan 2019 11:01:29 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:41720 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728784AbfAVQB3 (ORCPT ); Tue, 22 Jan 2019 11:01:29 -0500 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFuibw043882 for ; Tue, 22 Jan 2019 11:01:27 -0500 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2q65jda9s2-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:01:20 -0500 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:01:15 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG16ct37617748 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:01:06 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1C2CCA4057; Tue, 22 Jan 2019 16:01:06 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CD311A406B; Tue, 22 Jan 2019 16:01:02 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:01:02 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 12/13] KVM: PPC: Book3S HV: Fixed for running secure guests Date: Tue, 22 Jan 2019 07:59:43 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-12-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> <1548172784-27414-6-git-send-email-linuxram@us.ibm.com> <1548172784-27414-7-git-send-email-linuxram@us.ibm.com> <1548172784-27414-8-git-send-email-linuxram@us.ibm.com> <1548172784-27414-9-git-send-email-linuxram@us.ibm.com> <1548172784-27414-10-git-send-email-linuxram@us.ibm.com> <1548172784-27414-11-git-send-email-linuxram@us.ibm.com> <1548172784-27414-12-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0012-0000-0000-000002EB7182 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0013-0000-0000-000021229DCB Message-Id: <1548172784-27414-13-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=772 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Paul Mackerras - Pass SRR1 in r11 for UV_RETURN because SRR0 and SRR1 get set by the sc 2 instruction. (Note r3 - r10 potentially have hcall return values in them.) - Fix kvmppc_msr_interrupt to preserve the MSR_S bit. Signed-off-by: Paul Mackerras --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index 6f2f786..627b823 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -1119,8 +1119,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) mfspr r6, SPRN_HSRR1 andis. r6, r6, MSR_S@high - cmplwi r6, 0 - bne ret_to_ultra; + bne ret_to_ultra lwz r6, VCPU_CR(r4) mtcr r6 @@ -1140,6 +1139,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) ret_to_ultra: lwz r6, VCPU_CR(r4) mtcr r6 + mfspr r11, SPRN_SRR1 LOAD_REG_IMMEDIATE(r0, UV_RETURN) ld r6, VCPU_GPR(R6)(r4) ld r4, VCPU_GPR(R4)(r4) @@ -3344,13 +3344,16 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) * r0 is used as a scratch register */ kvmppc_msr_interrupt: + andis. r0, r11, MSR_S@h rldicl r0, r11, 64 - MSR_TS_S_LG, 62 - cmpwi r0, 2 /* Check if we are in transactional state.. */ + cmpwi cr1, r0, 2 /* Check if we are in transactional state.. */ ld r11, VCPU_INTR_MSR(r9) - bne 1f + bne cr1, 1f /* ... if transactional, change to suspended */ li r0, 1 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG + beqlr + oris r11, r11, MSR_S@h /* preserve MSR_S bit setting */ blr /* From patchwork Tue Jan 22 15:59:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ram Pai X-Patchwork-Id: 1029380 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43kY7Z38tyz9sDL for ; Wed, 23 Jan 2019 03:01:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728784AbfAVQB3 (ORCPT ); Tue, 22 Jan 2019 11:01:29 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:58254 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728848AbfAVQB3 (ORCPT ); Tue, 22 Jan 2019 11:01:29 -0500 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x0MFtlt8096651 for ; Tue, 22 Jan 2019 11:01:28 -0500 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0b-001b2d01.pphosted.com with ESMTP id 2q64k3d2ne-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jan 2019 11:01:27 -0500 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 22 Jan 2019 16:01:19 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x0MG1BDR9044330 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Jan 2019 16:01:11 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 44D11A4053; Tue, 22 Jan 2019 16:01:11 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A0B79A4065; Tue, 22 Jan 2019 16:01:07 +0000 (GMT) Received: from ram.ibm.com (unknown [9.85.201.166]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 22 Jan 2019 16:01:07 +0000 (GMT) From: Ram Pai To: kvm-ppc@vger.kernel.org Cc: cclaudio@br.ibm.com, maddy@linux.vnet.ibm.com, rgrimm@us.ibm.com, pmac@au1.ibm.com, andmike@us.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, santosh@linux.ibm.com, benh@linux.ibm.com, sesmith@au1.ibm.com, bharata@linux.ibm.com Subject: [PATCH 13/13] KVM: PPC: Ultravisor: Have fast_guest_return check secure_guest Date: Tue, 22 Jan 2019 07:59:44 -0800 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548172784-27414-13-git-send-email-linuxram@us.ibm.com> References: <1548172784-27414-1-git-send-email-linuxram@us.ibm.com> <1548172784-27414-2-git-send-email-linuxram@us.ibm.com> <1548172784-27414-3-git-send-email-linuxram@us.ibm.com> <1548172784-27414-4-git-send-email-linuxram@us.ibm.com> <1548172784-27414-5-git-send-email-linuxram@us.ibm.com> <1548172784-27414-6-git-send-email-linuxram@us.ibm.com> <1548172784-27414-7-git-send-email-linuxram@us.ibm.com> <1548172784-27414-8-git-send-email-linuxram@us.ibm.com> <1548172784-27414-9-git-send-email-linuxram@us.ibm.com> <1548172784-27414-10-git-send-email-linuxram@us.ibm.com> <1548172784-27414-11-git-send-email-linuxram@us.ibm.com> <1548172784-27414-12-git-send-email-linuxram@us.ibm.com> <1548172784-27414-13-git-send-email-linuxram@us.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19012216-0028-0000-0000-0000033C9840 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19012216-0029-0000-0000-000023F9D2AF Message-Id: <1548172784-27414-14-git-send-email-linuxram@us.ibm.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-22_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=858 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901220124 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org From: Sukadev Bhattiprolu fast_guest_return checks if HSRR1 has the MSR_S bit set to determine if we should return to UV. The problem is that when a new CPU starts up (in response to a RTAS start-cpu call), it will not have the MSR_S bit set in HSRR1 yet so the new CPU will not enter UV. Have fast_guest_return check the kvm_arch.secure_guest field instead so even the new CPU will enter UV. Thanks to input from Paul Mackerras, Ram Pai, Mike Anderson. Signed-off-by: Sukadev Bhattiprolu --- arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/kernel/asm-offsets.c | 1 + arch/powerpc/kvm/book3s_hv_rmhandlers.S | 12 +++++++----- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h index 0f98f00..162005a 100644 --- a/arch/powerpc/include/asm/kvm_host.h +++ b/arch/powerpc/include/asm/kvm_host.h @@ -288,6 +288,7 @@ struct kvm_arch { cpumask_t cpu_in_guest; u8 radix; u8 fwnmi_enabled; + u8 secure_guest; bool threads_indep; bool nested_enable; pgd_t *pgtable; diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index 9ffc72d..05f8a79 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -495,6 +495,7 @@ int main(void) OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v); OFFSET(KVM_RADIX, kvm, arch.radix); OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled); + OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest); OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr); OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar); OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr); diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index 627b823..b1710c8 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -1099,7 +1099,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) ld r2, VCPU_GPR(R2)(r4) ld r3, VCPU_GPR(R3)(r4) ld r5, VCPU_GPR(R5)(r4) - ld r7, VCPU_GPR(R7)(r4) ld r8, VCPU_GPR(R8)(r4) ld r9, VCPU_GPR(R9)(r4) ld r10, VCPU_GPR(R10)(r4) @@ -1117,13 +1116,15 @@ BEGIN_FTR_SECTION mtspr SPRN_HDSISR, r0 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) - mfspr r6, SPRN_HSRR1 - andis. r6, r6, MSR_S@high - bne ret_to_ultra + ld r6, VCPU_KVM(r4) + lbz r7, KVM_SECURE_GUEST(r6) + cmpdi r7, 1 + beq ret_to_ultra lwz r6, VCPU_CR(r4) mtcr r6 + ld r7, VCPU_GPR(R7)(r4) ld r6, VCPU_GPR(R6)(r4) ld r0, VCPU_GPR(R0)(r4) ld r4, VCPU_GPR(R4)(r4) @@ -1133,7 +1134,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) * The hcall we just completed was from Ultravisor. Use UV_RETURN * ultra call to return to the Ultravisor. Results from the hcall * are already in the appropriate registers (r3:12), except for - * R6 which we used as a temporary register above. Restore that, + * R6,7 which we used as temporary registers above. Restore them, * and set R0 to the ucall number (UV_RETURN). */ ret_to_ultra: @@ -1141,6 +1142,7 @@ ret_to_ultra: mtcr r6 mfspr r11, SPRN_SRR1 LOAD_REG_IMMEDIATE(r0, UV_RETURN) + ld r7, VCPU_GPR(R7)(r4) ld r6, VCPU_GPR(R6)(r4) ld r4, VCPU_GPR(R4)(r4) sc 2