From patchwork Tue Jan 15 17:05:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tamar Christina X-Patchwork-Id: 1025329 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-494088-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="lZBvRp0u"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.b="cwKchGHv"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43fGtw4DQRz9sCs for ; Wed, 16 Jan 2019 04:05:43 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; q=dns; s=default; b=f2r9CsvP4LuUc9JQnZO/hFYR06+SJImMFdLafKCQ9Z743UcFk1 2bYXjXcNZc4mLRAvLpFe0PwoFtv9TuKumDIeppmGYcTRyqJ6pbOqJCVciZoiMcCj bqtj+rKd4uIrgmRXx1uNir7zgLYsrT9YVrlniz3vwRZvEa+yiOj5Bw8Y8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:content-type:mime-version; s= default; bh=YZOwgQvCv0dMwIiurTQysyCn+A4=; b=lZBvRp0uMhSYnDpcgO/i v5RWWcjrjuOYP1p7NhEKiVGa6wzIwDxS+UFSprMhQj0xD/GI2/RQewumEG2yLNcG AjBW5Dw2lkbqkPqTeTy8T/32rDyb9KuF5/tRRJufNk1+iayTydlfDubgm4oJMeoO /BXTYQc+liuEOZMYceGJ8JY= Received: (qmail 9260 invoked by alias); 15 Jan 2019 17:05:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 9248 invoked by uid 89); 15 Jan 2019 17:05:35 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS, URIBL_ABUSE_SURBL autolearn=ham version=3.3.2 spammy=Verified, UD:md, H*c:HHH X-HELO: EUR02-VE1-obe.outbound.protection.outlook.com Received: from mail-bgr052101133086.outbound.protection.outlook.com (HELO EUR02-VE1-obe.outbound.protection.outlook.com) (52.101.133.86) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 15 Jan 2019 17:05:33 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6T3m5blQfbeVZGdamF00aeTylTVO+8Yc1A5uByJmniY=; b=cwKchGHvLXvlPraYtP+LU9FdUCWzNk1gpblfAIo1V+KFU17Jo4U317RQmpGNXY8LCmeLyuz5F5xlfzgY1ALkICZp22SsRmlR8TMpJMbCU5tNM8ztflu83oXVYGNxDQmvIEt43D8xcF6jXcQgBeEjetKLlKWnLMD9CYgrjgbFD4o= Received: from HE1PR0802MB2316.eurprd08.prod.outlook.com (10.172.127.22) by HE1PR0802MB2460.eurprd08.prod.outlook.com (10.175.34.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1516.18; Tue, 15 Jan 2019 17:05:29 +0000 Received: from HE1PR0802MB2316.eurprd08.prod.outlook.com ([fe80::603e:2c62:e89e:5983]) by HE1PR0802MB2316.eurprd08.prod.outlook.com ([fe80::603e:2c62:e89e:5983%5]) with mapi id 15.20.1516.019; Tue, 15 Jan 2019 17:05:29 +0000 From: Tamar Christina To: "gcc-patches@gcc.gnu.org" CC: nd , Ramana Radhakrishnan , Richard Earnshaw , "nickc@redhat.com" , Kyrylo Tkachov Subject: [PATCH][GCC][Arm] Fix arm big-endian intrinsics regressions. Date: Tue, 15 Jan 2019 17:05:29 +0000 Message-ID: <20190115170523.GA21796@arm.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tamar.Christina@arm.com; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) MIME-Version: 1.0 X-IsSubscribed: yes Hi All, We are a bit inconsistent when it comes to lane index endianness on Arm, we don't seem to always stick to the expected GCC vector extensions index endianness, for these tests since they are modelled as UNSPEC anyway just keep the indexes in Arm NEON order. There are other intrinsics that require an update, but for now these will fix the new ones. Bootstrapped Regtested on arm-none-Linux-gnueabihf and no issues. Cross compiled on armeb-none-eabi and regtested and no issues. Verified example by hand with execution tests and no issues. Ok for trunk? Thanks, Tamar gcc/ChangeLog: 2019-01-15 Tamar Christina * config/arm/arm-protos.h (neon_vcmla_lane_prepare_operands): Remove patternmode. * config/arm/arm.c (neon_vcmla_lane_prepare_operands): Likewise. * config/arm/neon.md (neon_vcmla_lane, neon_vcmla_laneq, neon_vcmlaq_lane): Remove endianness conversion. diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 2bc43019864ef70ed1bf1e725bad7437cf9b11d8..79ede0db174fcce87abe8b4d18893550d4c7e2f6 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -109,7 +109,7 @@ extern int arm_coproc_mem_operand (rtx, bool); extern int neon_vector_mem_operand (rtx, int, bool); extern int neon_struct_mem_operand (rtx); -extern rtx *neon_vcmla_lane_prepare_operands (machine_mode, rtx *); +extern rtx *neon_vcmla_lane_prepare_operands (rtx *); extern int tls_mentioned_p (rtx); extern int symbol_mentioned_p (rtx); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index cb5e7215e813dc922d606662df3fdc5040fd3524..0b598d20a46ebc6b5c29c782228da045f9a078c1 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -12724,8 +12724,7 @@ neon_struct_mem_operand (rtx op) /* Prepares the operands for the VCMLA by lane instruction such that the right register number is selected. This instruction is special in that it always requires a D register, however there is a choice to be made between Dn[0], - Dn[1], D(n+1)[0], and D(n+1)[1] depending on the mode of the registers and - the PATTERNMODE of the insn. + Dn[1], D(n+1)[0], and D(n+1)[1] depending on the mode of the registers. The VCMLA by lane function always selects two values. For instance given D0 and a V2SF, the only valid index is 0 as the values in S0 and S1 will be @@ -12737,9 +12736,9 @@ neon_struct_mem_operand (rtx op) updated to contain the right index. */ rtx * -neon_vcmla_lane_prepare_operands (machine_mode patternmode, rtx *operands) +neon_vcmla_lane_prepare_operands (rtx *operands) { - int lane = NEON_ENDIAN_LANE_N (patternmode, INTVAL (operands[4])); + int lane = INTVAL (operands[4]); machine_mode constmode = SImode; machine_mode mode = GET_MODE (operands[3]); int regno = REGNO (operands[3]); diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 6f8e7c1cffd2751c1ee7e03ded0410ad3c09c13f..f9d7ba35b137fed383f84eecbe81dd942943d216 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -3494,7 +3494,7 @@ VCMLA)))] "TARGET_COMPLEX" { - operands = neon_vcmla_lane_prepare_operands (mode, operands); + operands = neon_vcmla_lane_prepare_operands (operands); return "vcmla.\t%0, %2, d%c3[%c4], #"; } [(set_attr "type" "neon_fcmla")] @@ -3509,7 +3509,7 @@ VCMLA)))] "TARGET_COMPLEX" { - operands = neon_vcmla_lane_prepare_operands (mode, operands); + operands = neon_vcmla_lane_prepare_operands (operands); return "vcmla.\t%0, %2, d%c3[%c4], #"; } [(set_attr "type" "neon_fcmla")] @@ -3524,7 +3524,7 @@ VCMLA)))] "TARGET_COMPLEX" { - operands = neon_vcmla_lane_prepare_operands (mode, operands); + operands = neon_vcmla_lane_prepare_operands (operands); return "vcmla.\t%0, %2, d%c3[%c4], #"; } [(set_attr "type" "neon_fcmla")]