From patchwork Tue Oct 17 05:43:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Faiz Abbas X-Patchwork-Id: 826770 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="j/pZhhgF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yGPJT28D3z9sPk for ; Tue, 17 Oct 2017 16:44:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753367AbdJQFoC (ORCPT ); Tue, 17 Oct 2017 01:44:02 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:42681 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751935AbdJQFoB (ORCPT ); Tue, 17 Oct 2017 01:44:01 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9H5heTK015509; Tue, 17 Oct 2017 00:43:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1508219020; bh=oPjWBUjDJX9FXrSEVfdW7rWyN9z2OueImXo2krtrcBg=; h=From:To:CC:Subject:Date; b=j/pZhhgFhXlXFuhEgz1mtn3lHhNsKcau3mZt5KCUqXiKH+FpB3czWDjZD9A+JamRv AGza7OTxO7JdjZNTqfQEAYjr8Aa7ofSswrPmZP7kDbtAlVcSfnI7jt0gi2Mn8boQrK F0Y7iNL5EWrQjlWbblR+mfAGktbLxKk53wik6SsY= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9H5hZWP011976; Tue, 17 Oct 2017 00:43:35 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Tue, 17 Oct 2017 00:43:35 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Tue, 17 Oct 2017 00:43:35 -0500 Received: from a0230074-OptiPlex-7010.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9H5hXWN001717; Tue, 17 Oct 2017 00:43:33 -0500 From: Faiz Abbas To: CC: , , , , Subject: [PATCH] PCI: dwc: dra7xx: Print link state to console for debug Date: Tue, 17 Oct 2017 11:13:51 +0530 Message-ID: <1508219031-25592-1-git-send-email-faiz_abbas@ti.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable support for printing the LTSSM link state for debugging PCI when link is down. Signed-off-by: Faiz Abbas --- drivers/pci/dwc/pci-dra7xx.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 34427a6..7b150b0 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -98,6 +98,18 @@ struct dra7xx_pcie_of_data { #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev) +static char state[][20] = { + "DETECT_QUIET", "DETECT_ACT", "POLL_ACTIVE", "POLL_COMPLIANCE", + "POLL_CONFIG", "PRE_DETECT_QUIET", "DETECT_WAIT", "CFG_LINKWD_START", + "CFG_LINKWD_ACEPT", "CFG_LANENUM_WAIT", "CFG_LANENUM_ACEPT", + "CFG_COMPLETE", "CFG_IDLE", "RCVRY_LOCK", "RCVRY_SPEED", + "RCVRY_RCVRCFG", "RCVRY_IDLE", "L0", "L0S", "L123_SEND_EIDLE", + "L1_IDLE", "L2_IDLE", "L2_WAKE", "DISABLED_ENTRY", "DISABLED_IDLE", + "DISABLED", "LPBK_ENTRY", "LPBK_ACTIVE", "LPBK_EXIT", + "LPBK_EXIT_TIMEOUT", "HOT_RESET_ENTRY", "HOT_RESET", "RCVRY_EQ0", + "RCVRY_EQ1", "RCVRY_EQ2", "RCVRY_EQ3" +}; + static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) { return readl(pcie->base + offset); @@ -118,6 +130,15 @@ static int dra7xx_pcie_link_up(struct dw_pcie *pci) { struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); + u32 cmd_reg; + u32 ltssm_state; + + if (!(reg & LINK_UP)) { + cmd_reg = dra7xx_pcie_readl(dra7xx, + PCIECTRL_DRA7XX_CONF_DEVICE_CMD); + ltssm_state = (cmd_reg & GENMASK(7, 2)) >> 2; + dev_err(pci->dev, "Link state:%s\n", state[ltssm_state]); + } return !!(reg & LINK_UP); }