From patchwork Thu Jan 10 04:11:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Zhang X-Patchwork-Id: 1022721 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="ONF/pSr3"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43Zsxx0hqHz9sMQ for ; Thu, 10 Jan 2019 15:11:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727141AbfAJELb (ORCPT ); Wed, 9 Jan 2019 23:11:31 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19154 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727015AbfAJELb (ORCPT ); Wed, 9 Jan 2019 23:11:31 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 09 Jan 2019 20:11:05 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 09 Jan 2019 20:11:30 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 09 Jan 2019 20:11:30 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 10 Jan 2019 04:11:30 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 10 Jan 2019 04:11:30 +0000 Received: from localhost.localdomain (Not Verified[10.19.225.143]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 09 Jan 2019 20:11:30 -0800 From: Mark Zhang To: , , CC: , Mark Zhang , Jinyoung Park Subject: [PATCH 1/2] regulator: max77620: Initialize values for DT properties Date: Thu, 10 Jan 2019 12:11:16 +0800 Message-ID: <20190110041117.8216-1-markz@nvidia.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1547093465; bh=o2p44xN65nInpkkbxhA73quEzc+FQFCXP97mHOEic2c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:X-NVConfidentiality:Content-Transfer-Encoding: Content-Type; b=ONF/pSr3YsloxqZPxB0Vt0ynerev/se+HjwV/mPs+9FW+oXysy/CmtOdmjaixKvRM phCM9JFrqboC5HBKW/kB0Bia8+uu0ePy/nFR3YatV6KC6Yc4IIEiw1lU24tgbUIQDw 8MFHQZpiaN+p1pmU4A5L/luzkcxXKjha7JGUb9guT7R/w0Yc14nRygx0/uzdTQXHvN Ut1gAYkXcyoN+yGLF3RLLUjkPbFh6+NBjXoQdv/ifg4OpiAuxh4NQMQyJlsKNqlrJ9 MStTlx/4r5HwQ0Ezop+kTeKlohdjiC4E+3OFVmOrdtTRiqaaIs7cjzG/xmFaMCFSyr W42tCCd3mPgqA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org If regulator DT node doesn't exist, its of_parse_cb callback function isn't called. Then all values for DT properties are filled with zero. This leads to wrong register update for FPS and POK settings. Signed-off-by: Jinyoung Park Signed-off-by: Mark Zhang --- drivers/regulator/max77620-regulator.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/max77620-regulator.c b/drivers/regulator/max77620-regulator.c index b94e3a721721..cd93cf53e23c 100644 --- a/drivers/regulator/max77620-regulator.c +++ b/drivers/regulator/max77620-regulator.c @@ -1,7 +1,7 @@ /* * Maxim MAX77620 Regulator driver * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Author: Mallikarjun Kasoju * Laxman Dewangan @@ -803,6 +803,14 @@ static int max77620_regulator_probe(struct platform_device *pdev) rdesc = &rinfo[id].desc; pmic->rinfo[id] = &max77620_regs_info[id]; pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL; + pmic->reg_pdata[id].active_fps_src = -1; + pmic->reg_pdata[id].active_fps_pd_slot = -1; + pmic->reg_pdata[id].active_fps_pu_slot = -1; + pmic->reg_pdata[id].suspend_fps_src = -1; + pmic->reg_pdata[id].suspend_fps_pd_slot = -1; + pmic->reg_pdata[id].suspend_fps_pu_slot = -1; + pmic->reg_pdata[id].power_ok = -1; + pmic->reg_pdata[id].ramp_rate_setting = -1; ret = max77620_read_slew_rate(pmic, id); if (ret < 0) From patchwork Thu Jan 10 04:11:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Zhang X-Patchwork-Id: 1022722 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="rRDyxmwl"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43Zsy01cBfz9sMQ for ; Thu, 10 Jan 2019 15:11:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727200AbfAJELe (ORCPT ); Wed, 9 Jan 2019 23:11:34 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:4775 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727015AbfAJELe (ORCPT ); Wed, 9 Jan 2019 23:11:34 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 09 Jan 2019 20:11:20 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 09 Jan 2019 20:11:33 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 09 Jan 2019 20:11:33 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 10 Jan 2019 04:11:32 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 10 Jan 2019 04:11:33 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 10 Jan 2019 04:11:32 +0000 Received: from localhost.localdomain (Not Verified[10.19.225.143]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 09 Jan 2019 20:11:32 -0800 From: Mark Zhang To: , , CC: , Mark Zhang , "Venkat Reddy Talla" Subject: [PATCH 2/2] regulator: max77620: disable notifier events for FPS rails Date: Thu, 10 Jan 2019 12:11:17 +0800 Message-ID: <20190110041117.8216-2-markz@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20190110041117.8216-1-markz@nvidia.com> References: <20190110041117.8216-1-markz@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1547093480; bh=ANuGvTGYMoCE/3OxiFWpD45mC+dsL4A5k+RFn7JGYe0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=rRDyxmwldO62y0no+pKyN2itzGm6fXDNTYNa79eWVgQ7X0yeRPKSXMkaPqGSUw8ei SsX/l3Pp7+/EVvBbCpTrEIxDvFVc2fKgNqqJK+QESlzEWAvSz7OWgfh96RJqELm+Iq Pm4j9S9w+lIxyw8BzPAp5FF7174gNC9FE2bUQ0PYacEe54EOFFpU67YLS4CO46IQkX zblkWAOgv0Ki8sb6ehRThpVDIUGGizLVDpNsK5ILAC2CJ+JVltTUZvTfv8C2ok4I75 IUEr+pTiRXNNcD32SHfmCohZU/1NjTNDRfpzfPOn58s6X66iLW8mfHs0P1Rfn7TPzM hVRwb4cGrpj0A== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Disabling regulator notifier events if regulator is configured part of flexible power sequencer(FPS), there is no SW control to enable/disable if regulator is configured part of FPS, so disabling notifier events if client driver try to enable/disable FPS rails. Signed-off-by: Venkat Reddy Talla Signed-off-by: Mark Zhang --- drivers/regulator/max77620-regulator.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/regulator/max77620-regulator.c b/drivers/regulator/max77620-regulator.c index cd93cf53e23c..20e985071bfc 100644 --- a/drivers/regulator/max77620-regulator.c +++ b/drivers/regulator/max77620-regulator.c @@ -823,6 +823,13 @@ static int max77620_regulator_probe(struct platform_device *pdev) rdesc->name, ret); return ret; } + + /* there is no SW control for rails which are part of FPS + * set always no contraint to true to avoid regulator + * enable/disable notification + */ + if (pmic->reg_pdata[id].active_fps_src != MAX77620_FPS_SRC_NONE) + rdev->constraints->always_on = true; } return 0;