From patchwork Mon Jan 7 15:21:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauricio Faria de Oliveira X-Patchwork-Id: 1021389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.ubuntu.com (client-ip=91.189.94.19; helo=huckleberry.canonical.com; envelope-from=kernel-team-bounces@lists.ubuntu.com; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=canonical.com Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43YJzL34q9z9sMp; Tue, 8 Jan 2019 02:22:22 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.86_2) (envelope-from ) id 1ggWjJ-0008QC-4a; Mon, 07 Jan 2019 15:22:17 +0000 Received: from youngberry.canonical.com ([91.189.89.112]) by huckleberry.canonical.com with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.86_2) (envelope-from ) id 1ggWjH-0008Pj-E8 for kernel-team@lists.ubuntu.com; Mon, 07 Jan 2019 15:22:15 +0000 Received: from mail-qk1-f200.google.com ([209.85.222.200]) by youngberry.canonical.com with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.76) (envelope-from ) id 1ggWjH-00034R-4R for kernel-team@lists.ubuntu.com; Mon, 07 Jan 2019 15:22:15 +0000 Received: by mail-qk1-f200.google.com with SMTP id r145so517142qke.20 for ; Mon, 07 Jan 2019 07:22:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zN56cziPqvgOKl6rSTmfu1E3gjkDo+HSeNKHkNLoDi0=; b=lYjzKLFPK+PFQAC0Eq/JMtrLjgR6A2ICLBD2Namt9qUiDzjAT4ZyAED+isTQqRpnQG sNbD1mWvcowMqp16lCfjW5NOjU7guD7p2ztjvbDHAeJrAx46UvP7armybVTs0makX6k5 uWKZepskaQ6NMt+Efvv6aa704Y5C1Km0FXTTDIJC4hnPS+RYLMZX3mogce1t+BXzrUxe FquVF3k9ZNUk+xQcNhV+lBPM415DJJA0F8HB9MbVNexaF13gR2mUs09YB03Ut2y+fno4 FAHhXsWp0lEYm230mXZRxXLoQ50khPeGrNLGFfTh3uEFn5JjxK8/0nWHgbHnd9RP5lbb 2fFg== X-Gm-Message-State: AA+aEWa28KXd2IegC3GGs1O/LkWGDseBisUYPyjmGNrrVfEEftPilySG mMol0DhehqMNftyBQyCTV9fKiKQ1MBHAKPzGY1G2R+3ZSf6HqCF/XSveNwDsN7Oq4vVWJy00AiS XJZw8sSd2JTFPaG+ZdfO+qiEgpe1wE8/P+82u+Smtbg== X-Received: by 2002:aed:3802:: with SMTP id j2mr61701918qte.146.1546874533995; Mon, 07 Jan 2019 07:22:13 -0800 (PST) X-Google-Smtp-Source: ALg8bN7v74GInjFcZmU3KwoXrWIGf+66n9JIGxYf/T4e2A/CYsuGaR8W1Fjj3LGB3Q3WGGRABjeQNw== X-Received: by 2002:aed:3802:: with SMTP id j2mr61701912qte.146.1546874533837; Mon, 07 Jan 2019 07:22:13 -0800 (PST) Received: from localhost.localdomain ([177.181.227.0]) by smtp.gmail.com with ESMTPSA id w81sm42979306qkg.43.2019.01.07.07.22.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 07 Jan 2019 07:22:13 -0800 (PST) From: Mauricio Faria de Oliveira To: kernel-team@lists.ubuntu.com Subject: [SRU C/B][PATCH 1/1] scsi: mpt3sas: As per MPI-spec, use combined reply queue for SAS3.5 controllers when HBA supports more than 16 MSI-x vectors. Date: Mon, 7 Jan 2019 13:21:27 -0200 Message-Id: <20190107152127.29939-2-mfo@canonical.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190107152127.29939-1-mfo@canonical.com> References: <20190107152127.29939-1-mfo@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gpiccoli@canonical.com MIME-Version: 1.0 Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" From: Chaitra P B BugLink: https://bugs.launchpad.net/bugs/1810781 Presently driver is using combined reply queue feature when MSI-x vectors > 8 for both SAS3 and SAS3.5 controllers. But as per MPI-spec, 1. For SAS3 controllers, driver should use combined reply queue when HBA supports more than 8 MSI-x vectors. 2. For SAS3.5 controllers, driver should use combined reply queue when HBA supports more than 16 MSI-x vectors. Modified driver code to use combined reply queue for SAS3 controllers when HBA supports > 8 MSI-x vectors and for SAS3.5 controllers when HBA supports > 16 MSI-x vectors. Signed-off-by: Chaitra P B Signed-off-by: Martin K. Petersen (cherry picked from commit 2b48be65685a23f4ffc7a06858992bc31e98e198) Signed-off-by: Mauricio Faria de Oliveira Acked-by: Stefan Bader Acked-by: Khalid Elmously --- drivers/scsi/mpt3sas/mpt3sas_base.c | 15 ++++++++------- drivers/scsi/mpt3sas/mpt3sas_base.h | 1 + 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 3c8c17c0b547..7efc7f00c907 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -2924,10 +2924,9 @@ mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc) _base_free_irq(ioc); _base_disable_msix(ioc); - if (ioc->combined_reply_queue) { - kfree(ioc->replyPostRegisterIndex); - ioc->replyPostRegisterIndex = NULL; - } + kfree(ioc->replyPostRegisterIndex); + ioc->replyPostRegisterIndex = NULL; + if (ioc->chip_phys) { iounmap(ioc->chip); @@ -3034,7 +3033,7 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) /* Use the Combined reply queue feature only for SAS3 C0 & higher * revision HBAs and also only when reply queue count is greater than 8 */ - if (ioc->combined_reply_queue && ioc->reply_queue_count > 8) { + if (ioc->combined_reply_queue) { /* Determine the Supplemental Reply Post Host Index Registers * Addresse. Supplemental Reply Post Host Index Registers * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and @@ -3058,8 +3057,7 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET + (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET)); } - } else - ioc->combined_reply_queue = 0; + } if (ioc->is_warpdrive) { ioc->reply_post_host_index[0] = (resource_size_t __iomem *) @@ -5682,6 +5680,9 @@ _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc) facts->WhoInit = mpi_reply.WhoInit; facts->NumberOfPorts = mpi_reply.NumberOfPorts; facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors; + if (ioc->msix_enable && (facts->MaxMSIxVectors <= + MAX_COMBINED_MSIX_VECTORS(ioc->is_gen35_ioc))) + ioc->combined_reply_queue = 0; facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit); facts->MaxReplyDescriptorPostQueueDepth = le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth); diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index f02974c0be4a..e3095fb0f77a 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -323,6 +323,7 @@ * There are twelve Supplemental Reply Post Host Index Registers * and each register is at offset 0x10 bytes from the previous one. */ +#define MAX_COMBINED_MSIX_VECTORS(gen35) ((gen35 == 1) ? 16 : 8) #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G3 12 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G35 16 #define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET (0x10)