From patchwork Thu Dec 27 20:24:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1018995 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="ftsnpkt9"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43QhFD0d5Yz9s55 for ; Fri, 28 Dec 2018 07:26:23 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 95316C21E4E; Thu, 27 Dec 2018 20:25:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D16D9C21D83; Thu, 27 Dec 2018 20:25:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5662AC21DD4; Thu, 27 Dec 2018 20:25:10 +0000 (UTC) Received: from mail-io1-f70.google.com (mail-io1-f70.google.com [209.85.166.70]) by lists.denx.de (Postfix) with ESMTPS id D57A2C21E02 for ; Thu, 27 Dec 2018 20:25:07 +0000 (UTC) Received: by mail-io1-f70.google.com with SMTP id q18so2641589ioj.5 for ; Thu, 27 Dec 2018 12:25:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=MVcrhGowTBAy7jDotAimuEXAM/82laoFgM8Zs01zFSE=; b=ftsnpkt9aqhFD/sjbRdwf4BoVqEcXEBIsdYqNceENktkZNifPh8ZOgih5nIjn/KI0u 0VceyTnbknYbkOTuDIS0lzZ2n3+n5HKYah+nbPt4MnK+mGvtLfgSH/u2DKuoChCgBCQp aTpe/inSN0JKo+AeXk6hO9p3XI1+DrOkrCMR0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=MVcrhGowTBAy7jDotAimuEXAM/82laoFgM8Zs01zFSE=; b=aieJ2DsadDUQ1SUoy3cJoLUT3rClP+rakk55zKELwxgTfwpnwBBXLzLdvVpHab7zan +ZoaRvov6SwikdmXWTQmT8uU8xrtM6a1InoQr0+U1F3PfOGZoIgDCJ97YosOsvP96wqO cKeO4KgWPpBlzagSGgJ02QHVmRyei27WQEoW1FBjZC1TMEPn4HjP1puyyPUDVFEgIsqr ei16jH8NDPNT50vePfINZWunL3PPBaxh22OCl+8AayPN4V1N2okr2IVczQXW1vkDLVz+ ECphCyGLao5JkxgQMVCl1WxK8Mb0JUUvVRg62TD4Vy0FMp/5m3i0lQin1hNjSm1va39U 996A== X-Gm-Message-State: AA+aEWZpJr89VRIStvIrvCLQA3s3+t2lDeNEUw0WImP2z/ViejN+K637 GxXE8nc7BYhTgWeYuouQxnupGgGony7KJ+VU X-Google-Smtp-Source: AFSGD/WNdtAe7Z0tWMzaRQGX7TfjSPFB9/qStdSM7jm2JoM5skSUMINvFzXfX3YtZlLj4UnlGNasSW7aVDGSFSl8 X-Received: by 2002:a24:7a05:: with SMTP id a5mr18686733itc.30.1545942306532; Thu, 27 Dec 2018 12:25:06 -0800 (PST) Date: Thu, 27 Dec 2018 13:24:36 -0700 In-Reply-To: <20181227202446.229042-1-sjg@chromium.org> Message-Id: <20181227202446.229042-2-sjg@chromium.org> Mime-Version: 1.0 References: <20181227202446.229042-1-sjg@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog From: Simon Glass To: U-Boot Mailing List Subject: [U-Boot] [PATCH 01/11] misc: Allow child devices X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Allow misc devices to have children, so that we can use this uclass for cases where a child device (e.g. I2S) needs to access a misc driver for transferring data. Signed-off-by: Simon Glass Signed-off-by: Simon Glass --- drivers/misc/misc-uclass.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c index f240cda5c05..f432bc91997 100644 --- a/drivers/misc/misc-uclass.c +++ b/drivers/misc/misc-uclass.c @@ -68,4 +68,5 @@ int misc_set_enabled(struct udevice *dev, bool val) UCLASS_DRIVER(misc) = { .id = UCLASS_MISC, .name = "misc", + .post_bind = dm_scan_fdt_dev, }; From patchwork Thu Dec 27 20:24:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1019001 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="lf4qvz2i"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43QhKk5Cv1z9s55 for ; Fri, 28 Dec 2018 07:30:18 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 59FF4C21DFF; Thu, 27 Dec 2018 20:27:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7F5D3C21E2B; Thu, 27 Dec 2018 20:25:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0E7A4C21D8A; Thu, 27 Dec 2018 20:25:10 +0000 (UTC) Received: from mail-qk1-f200.google.com (mail-qk1-f200.google.com [209.85.222.200]) by lists.denx.de (Postfix) with ESMTPS id EFC07C21DD4 for ; Thu, 27 Dec 2018 20:25:08 +0000 (UTC) Received: by mail-qk1-f200.google.com with SMTP id 98so24360888qkp.22 for ; Thu, 27 Dec 2018 12:25:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=BwBbZ8EXDuPiOi1K97OWBmrxOaAhPy27W2zlQRoUrbw=; b=lf4qvz2i3jvfaPt8Psek63uGmdVoWKlLVjjATE7ttMU5ULd82znSoHEyTeH1SwBGwc KVeKZlvobifkiIcArSoamq0b//vYSUlM5HCBNTZ20YbsfY97QNd3qcWe0Bw5v9tiF/Xa Yf5WKVVkWDAj8ZaEluPSCatURSc24f2BQ6wZs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=BwBbZ8EXDuPiOi1K97OWBmrxOaAhPy27W2zlQRoUrbw=; b=OIR6B5/1uF4CTQqYYiHQtu6OiD9rpfLXR5OTMFqNVMIpqnUP7mHEHNEegvEeaKWwrN xdxb/L2sn5Je7xrainDBgg043eb/DoUm2JtoRZZATdDb7Py1BbtdTCqLr4Rj4nSUDrsk FbOFGzUwVRT5lWxmCRqj+6psEJLLhPmiebGhuw/Qs/u09OBmskf8KCYW8hTgqvhoNzVx 8viGlcxqpXBm88uQkPoYieFfjJ2rDG+8OkjMk3gETIjtpKtaWQExfzJtKqi5umZ1Htvu JV9g/YDMdJJIb+OmAYHaKFbZNIKa7QRco2r5NfgTdeok6grLA570j6BJjVsMEsjKl1/8 Amdw== X-Gm-Message-State: AJcUukfWiBBOLLEW6K7UHXbVA8tuSfYyyFILK2gygbQdeTMtH9bR7aTL lV7P4WVtEYIRyrLTyxTD7GjbQ6t8T+EzqwPd X-Google-Smtp-Source: ALg8bN6r07chxszFBxIfgxeV6YURNHDNH0sjOmk6i9VeIrA89VaeaJm+WGJDDoxvU9cz/u8rB+5/m+Y3Pw9tFUhe X-Received: by 2002:a0c:8ac2:: with SMTP id 2mr17279970qvw.27.1545942308006; Thu, 27 Dec 2018 12:25:08 -0800 (PST) Date: Thu, 27 Dec 2018 13:24:37 -0700 In-Reply-To: <20181227202446.229042-1-sjg@chromium.org> Message-Id: <20181227202446.229042-3-sjg@chromium.org> Mime-Version: 1.0 References: <20181227202446.229042-1-sjg@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog From: Simon Glass To: U-Boot Mailing List Subject: [U-Boot] [PATCH 02/11] sound: samsung: Fix 'regiter' typo X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Fix a typo that appears many times in this file. Signed-off-by: Simon Glass Signed-off-by: Simon Glass --- drivers/sound/samsung-i2s.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/sound/samsung-i2s.c b/drivers/sound/samsung-i2s.c index c19e08e7e30..104584073af 100644 --- a/drivers/sound/samsung-i2s.c +++ b/drivers/sound/samsung-i2s.c @@ -24,7 +24,7 @@ /* * Sets the frame size for I2S LR clock * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param rfs Frame Size */ static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs) @@ -54,7 +54,7 @@ static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs) /* * Sets the i2s transfer control * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param on 1 enable tx , 0 disable tx transfer */ static void i2s_txctrl(struct i2s_reg *i2s_reg, int on) @@ -77,7 +77,7 @@ static void i2s_txctrl(struct i2s_reg *i2s_reg, int on) /* * set the bit clock frame size (in multiples of LRCLK) * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param bfs bit Frame Size */ static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs) @@ -108,7 +108,7 @@ static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs) /* * flushes the i2stx fifo * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param flush Tx fifo flush command (0x00 - do not flush * 0x80 - flush tx fifo) */ @@ -122,7 +122,7 @@ static void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush) /* * Set System Clock direction * - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * @param dir Clock direction * * @return int value 0 for success, -1 in case of error @@ -145,7 +145,7 @@ static int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir) * Sets I2S Clcok format * * @param fmt i2s clock properties - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * * @return int value 0 for success, -1 in case of error */ @@ -222,7 +222,7 @@ static int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt) * Sets the sample width in bits * * @param blc samplewidth (size of sample in bits) - * @param i2s_reg i2s regiter address + * @param i2s_reg i2s register address * * @return int value 0 for success, -1 in case of error */ @@ -294,7 +294,7 @@ int i2s_transfer_tx_data(struct i2s_uc_priv *pi2s_tx, void *data, return 0; } -int i2s_tx_init(struct i2s_uc_priv *pi2s_tx) +static int i2s_tx_init(struct i2s_uc_priv *pi2s_tx) { int ret; struct i2s_reg *i2s_reg = (struct i2s_reg *)pi2s_tx->base_address; From patchwork Thu Dec 27 20:24:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1018994 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="lZ44Py4V"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43QhDT42pmz9s55 for ; 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Thu, 27 Dec 2018 12:25:09 -0800 (PST) Date: Thu, 27 Dec 2018 13:24:38 -0700 In-Reply-To: <20181227202446.229042-1-sjg@chromium.org> Message-Id: <20181227202446.229042-4-sjg@chromium.org> Mime-Version: 1.0 References: <20181227202446.229042-1-sjg@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog From: Simon Glass To: U-Boot Mailing List Subject: [U-Boot] [PATCH 03/11] sound: i2s: Tidy up a few comments X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Fix a struct typo and drop a comment (and function prototype) which is not actually used. Signed-off-by: Simon Glass Signed-off-by: Simon Glass --- include/i2s.h | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/include/i2s.h b/include/i2s.h index 28f6184811c..7760aab7c46 100644 --- a/include/i2s.h +++ b/include/i2s.h @@ -78,7 +78,7 @@ struct i2s_reg { /* This structure stores the i2s related information */ struct i2s_uc_priv { unsigned int rfs; /* LR clock frame size */ - unsigned int bfs; /* Bit slock frame size */ + unsigned int bfs; /* Bit clock frame size */ unsigned int audio_pll_clk; /* Audio pll frequency in Hz */ unsigned int samplingrate; /* sampling rate */ unsigned int bitspersample; /* bits per sample */ @@ -123,13 +123,4 @@ int i2s_tx_data(struct udevice *dev, void *data, uint data_size); int i2s_transfer_tx_data(struct i2s_uc_priv *pi2s_tx, void *data, uint data_size); -/* - * Initialise i2s transmiter - * - * @param pi2s_tx pointer of i2s transmitter parameter structure. - * - * @return int value 0 for success, -1 in case of error - */ -int i2s_tx_init(struct i2s_uc_priv *pi2s_tx); - #endif /* __I2S_H__ */ From patchwork Thu Dec 27 20:24:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1019002 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="KhlmbZI3"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43QhLZ3pmzz9s55 for ; Fri, 28 Dec 2018 07:31:02 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3204BC21DCA; Thu, 27 Dec 2018 20:28:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 05634C21E49; Thu, 27 Dec 2018 20:25:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BE1C6C21DA6; Thu, 27 Dec 2018 20:25:12 +0000 (UTC) Received: from mail-io1-f70.google.com (mail-io1-f70.google.com [209.85.166.70]) by lists.denx.de (Postfix) with ESMTPS id 25DEDC21BE5 for ; Thu, 27 Dec 2018 20:25:12 +0000 (UTC) Received: by mail-io1-f70.google.com with SMTP id t13so17964311ioi.3 for ; Thu, 27 Dec 2018 12:25:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=ZUtYmtLZJ+7kvvkFDuawTjVtXr1XW80WcJSYx7I1zBM=; b=KhlmbZI3mx62XmyBiKHIOpBzOd+JBYyD78toOrbwRpUXpj0kd+h/3MR2x9omN9KWw/ SRQjtiEj34EpYARijzFaAgUMvADKEa4ttSqNFrnUrmeM3VFuhYQq445Kq5IJ4rqQIpK1 wMFVaxEhtd7CmLacuv1dJHZntwIJ63GvgPOPA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=ZUtYmtLZJ+7kvvkFDuawTjVtXr1XW80WcJSYx7I1zBM=; b=WbczGC0FJs0OA5kZ1HM+w8OmE3z85XubkOlgLcQ7ulQjvh35tyFtIfImzHm6mHZW9t GLsgmXc0PuxGsjUo+p0G1AB45R0TnLuJm266C+n4OVLhe4aslGbK3I3M7lpqIbFYMb6P 4Wh8zCcVw3RJJftKmPjIeNXqvtm/2Llgw5WUFWYsSpkktmUsukGKfW9Uw99Og/VxSdt0 K2mPPr24oGNnXwa8J9Zx+IIkRq9+5dme/gX11QENsKxdmPwXs5TfkyiIardVGStfkdjW kMPeqhSIa6J003RJc0v4J+0ORW60y7Ua0Y0DvXG0COUMXw4cpqoGfSv/n6orSSTb3xQ6 2bnQ== X-Gm-Message-State: AJcUukc2N2WWpQJqRmIosaoKr3yDjsgXBw4tJDHc0UCzMnWsYjrOLJKD Pax27X22g79QznQxLE0M5iJ+Tij8Qc2Uv/Gk X-Google-Smtp-Source: AFSGD/WhC2bS4YrgPwmCnLpLwN4yuCGkHSjM+3mOvt6FvGC3kpt5CdZIKtldX52U4fXZxlWPKtmVzCpeCaeN+Uck X-Received: by 2002:a24:5ac2:: with SMTP id v185mr18740872ita.28.1545942311169; Thu, 27 Dec 2018 12:25:11 -0800 (PST) Date: Thu, 27 Dec 2018 13:24:39 -0700 In-Reply-To: <20181227202446.229042-1-sjg@chromium.org> Message-Id: <20181227202446.229042-5-sjg@chromium.org> Mime-Version: 1.0 References: <20181227202446.229042-1-sjg@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog From: Simon Glass To: U-Boot Mailing List Subject: [U-Boot] [PATCH 04/11] sound: Allow audio codecs to be used by other SoCs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present there is still some samsung-specific code in the audio codecs. Remove it so that these can be used by other SoCs. Signed-off-by: Simon Glass Signed-off-by: Simon Glass --- drivers/sound/Kconfig | 8 ++++---- drivers/sound/max98088.c | 7 ------- drivers/sound/max98090.c | 7 ------- drivers/sound/max98095.c | 7 ------- drivers/sound/maxim_codec.c | 3 --- drivers/sound/samsung_sound.c | 4 ++++ 6 files changed, 8 insertions(+), 28 deletions(-) diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig index 6a04a59dada..506a60a7c7b 100644 --- a/drivers/sound/Kconfig +++ b/drivers/sound/Kconfig @@ -23,7 +23,7 @@ config I2S config I2S_SAMSUNG bool "Enable I2C support for Samsung SoCs" - depends on SOUND + depends on I2S help Samsung Exynos SoCs support an I2S interface for sending audio data to an audio codec. This option enables support for this, @@ -33,7 +33,7 @@ config I2S_SAMSUNG config SOUND_MAX98088 bool "Support Maxim max98088 audio codec" - depends on I2S_SAMSUNG + depends on I2S help Enable the max98088 audio codec. This is connected via I2S for audio data and I2C for codec control. At present it only works @@ -41,7 +41,7 @@ config SOUND_MAX98088 config SOUND_MAX98090 bool "Support Maxim max98090 audio codec" - depends on I2S_SAMSUNG + depends on I2S help Enable the max98090 audio codec. This is connected via I2S for audio data and I2C for codec control. At present it only works @@ -49,7 +49,7 @@ config SOUND_MAX98090 config SOUND_MAX98095 bool "Support Maxim max98095 audio codec" - depends on I2S_SAMSUNG + depends on I2S help Enable the max98095 audio codec. This is connected via I2S for audio data and I2C for codec control. At present it only works diff --git a/drivers/sound/max98088.c b/drivers/sound/max98088.c index 5ddc11ac5c7..46d068cca64 100644 --- a/drivers/sound/max98088.c +++ b/drivers/sound/max98088.c @@ -16,10 +16,6 @@ #include #include #include -#include -#include -#include -#include #include "maxim_codec.h" #include "max98088.h" @@ -288,9 +284,6 @@ static int max98088_device_init(struct maxim_priv *priv) unsigned char id; int error = 0; - /* Enable codec clock */ - set_xclkout(); - /* reset the codec, the DSP core, and disable all interrupts */ error = max98088_reset(priv); if (error != 0) { diff --git a/drivers/sound/max98090.c b/drivers/sound/max98090.c index 346ff5ffbec..5505c351666 100644 --- a/drivers/sound/max98090.c +++ b/drivers/sound/max98090.c @@ -13,10 +13,6 @@ #include #include #include -#include -#include -#include -#include #include "maxim_codec.h" #include "max98090.h" @@ -240,9 +236,6 @@ int max98090_device_init(struct maxim_priv *priv) unsigned char id; int error = 0; - /* Enable codec clock */ - set_xclkout(); - /* reset the codec, the DSP core, and disable all interrupts */ error = max98090_reset(priv); if (error != 0) { diff --git a/drivers/sound/max98095.c b/drivers/sound/max98095.c index 99c0e996b4f..9e08e96670e 100644 --- a/drivers/sound/max98095.c +++ b/drivers/sound/max98095.c @@ -15,10 +15,6 @@ #include #include #include -#include -#include -#include -#include #include "i2s.h" #include "max98095.h" @@ -306,9 +302,6 @@ static int max98095_device_init(struct maxim_priv *priv) unsigned char id; int ret; - /* Enable codec clock */ - set_xclkout(); - /* reset the codec, the DSP core, and disable all interrupts */ ret = max98095_reset(priv); if (ret != 0) { diff --git a/drivers/sound/maxim_codec.c b/drivers/sound/maxim_codec.c index dcaf081988b..5480dce1080 100644 --- a/drivers/sound/maxim_codec.c +++ b/drivers/sound/maxim_codec.c @@ -12,9 +12,6 @@ #include #include #include -#include -#include -#include #include "maxim_codec.h" /* diff --git a/drivers/sound/samsung_sound.c b/drivers/sound/samsung_sound.c index 84064ebd0fe..b6952675bde 100644 --- a/drivers/sound/samsung_sound.c +++ b/drivers/sound/samsung_sound.c @@ -10,6 +10,7 @@ #include #include #include +#include static int samsung_sound_setup(struct udevice *dev) { @@ -79,6 +80,9 @@ static int samsung_sound_probe(struct udevice *dev) debug("Probed sound '%s' with codec '%s' and i2s '%s'\n", dev->name, uc_priv->codec->name, uc_priv->i2s->name); + /* Enable codec clock */ + set_xclkout(); + return 0; } From patchwork Thu Dec 27 20:24:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1019000 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="e+vPX04Q"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43QhKV1ddYz9s8J for ; Fri, 28 Dec 2018 07:30:06 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E3893C21DB3; Thu, 27 Dec 2018 20:28:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D087FC21E3A; Thu, 27 Dec 2018 20:25:29 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A8766C21D4A; Thu, 27 Dec 2018 20:25:14 +0000 (UTC) Received: from mail-io1-f70.google.com (mail-io1-f70.google.com [209.85.166.70]) by lists.denx.de (Postfix) with ESMTPS id 9A189C21DAF for ; Thu, 27 Dec 2018 20:25:13 +0000 (UTC) Received: by mail-io1-f70.google.com with SMTP id f24so23273563ioh.21 for ; Thu, 27 Dec 2018 12:25:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=EZ9tCq1pbtHiWM3BbCH8TVu+4JCYDlNUuW/qUk0Ddss=; b=e+vPX04QKOtDFUACWoCfouFsQiOjIc86w2HZNZSWw1/M6IszgGGr9Tgs5hEhHxiOch I1gqtTfls2wfzXw2hhZpzobbXqlJ1u4cs10WT7YoO2XkGhtqL2P1M0gYNb+FBrTj51ft 7dAWwLxoHkJ7ZOarTZG1JTYBl4ztVy6RDowM0= X-Google-DKIM-Signature: v=1; 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It should be CLK_M, not OSC. Fix it and its only user. Signed-off-by: Simon Glass --- arch/arm/mach-tegra/tegra124/clock.c | 2 +- board/nvidia/nyan-big/nyan-big.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 3bd6cf2afff..70916ea3c18 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -71,7 +71,7 @@ enum { */ #define CLK(x) CLOCK_ID_ ## x static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = { - { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC), + { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(CLK_M), CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE), MASK_BITS_31_30}, { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO), diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index ff5c67de985..3c7bfead249 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -121,7 +121,7 @@ static void enable_required_clocks(void) int nvidia_board_init(void) { clock_start_periph_pll(PERIPH_ID_EXTPERIPH1, CLOCK_ID_OSC, 12000000); - clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_OSC, 1500000); + clock_start_periph_pll(PERIPH_ID_I2S1, CLOCK_ID_CLK_M, 1500000); /* For external MAX98090 audio codec */ clock_external_output(1); From patchwork Thu Dec 27 20:24:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1018999 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="a7XgSPlh"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43QhK94TGfz9s55 for ; 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Thu, 27 Dec 2018 12:25:14 -0800 (PST) Date: Thu, 27 Dec 2018 13:24:41 -0700 In-Reply-To: <20181227202446.229042-1-sjg@chromium.org> Message-Id: <20181227202446.229042-7-sjg@chromium.org> Mime-Version: 1.0 References: <20181227202446.229042-1-sjg@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog From: Simon Glass To: U-Boot Mailing List Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH 06/11] tegra: Add a delay in clock_start_periph_pll() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This function enables a peripheral clock and then immediately sets its divider. Add a delay to allow the clock to settle first. This matches the delay in other places which do a similar thing. Without this, the I2S device on Nyan does not init properly. Signed-off-by: Simon Glass --- arch/arm/mach-tegra/clock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 096330748f2..dc5f16b41b6 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -477,6 +477,7 @@ unsigned clock_start_periph_pll(enum periph_id periph_id, reset_set_enable(periph_id, 1); clock_enable(periph_id); + udelay(2); effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate, NULL); From patchwork Thu Dec 27 20:24:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1019004 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="WOOhZ/JS"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43QhMd5yP2z9s8r for ; Fri, 28 Dec 2018 07:31:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2F861C21E42; Thu, 27 Dec 2018 20:28:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.8 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID, UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B32A1C21E35; Thu, 27 Dec 2018 20:25:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 074BFC21D4A; Thu, 27 Dec 2018 20:25:18 +0000 (UTC) Received: from mail-io1-f71.google.com (mail-io1-f71.google.com [209.85.166.71]) by lists.denx.de (Postfix) with ESMTPS id 46BF4C21E18 for ; Thu, 27 Dec 2018 20:25:17 +0000 (UTC) Received: by mail-io1-f71.google.com with SMTP id r65so23004999iod.12 for ; Thu, 27 Dec 2018 12:25:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=Af1SgZQo6rkChzZJDi27a3Fa9USDse+8atEuDwOIBgM=; b=WOOhZ/JSPNrvUykOAM5xIxGjTluoPhD7BanYdn+aNlAEQdpiC98292KPwfg5U6tpNh gONRw/bRdSW+rMgNiEIcg8gDWnMpFlg5Y5nx2cuKbhkX4DdAKn96rlCSYAhe3nlw0E0o OlGi/TPVSUncG69HgBQzcog/5wbsXoKfugaVg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=Af1SgZQo6rkChzZJDi27a3Fa9USDse+8atEuDwOIBgM=; b=jxSya+5b0yXOx2sNq4rHobMLXsycqgojv4bzFw5pZHHsXCoS4VoXA56gVGpZCsvVaf C3UtVvfEn/9JdAWiwHclyaVp/JJ01OUQOJuVfEiTeA8HSBp45ml+sg/V/OmqzsWJ4q6g pIl+Gj6kv+2HXFUUtR0L4FFH6zfhS1fExUdBGqVR/4BLjZh8OdMRtwl+uq0kARIYzEFE SbzIFoN8sGG5kUuJJ5cXtxmUzjq8oSkvG0gKWGgnoOC0lmjcqfZC/cslQAMWK0Rr5tcS Si7dqrs9bwChEVZGt/B7RurgeES293yzYVWEzmF7pprYZPWoWmQq+QhpqwSKFyHXqroZ i3ZA== X-Gm-Message-State: AA+aEWZp09OGXiilbRbhC15MvdCYf1MFqCG74dlezz30HoWZsDSADgel hx2ILt93G1y8jLAgLkmCnzKC53ukWVCc7rmS X-Google-Smtp-Source: AFSGD/UMrQudLiszPIfXvMrgdZEIjbyflxf3yo3wRbe72aYYOvRk8FxTNvhGsn4QMzgNSDqy+6E0C/ccqbSKRFhS X-Received: by 2002:a24:4746:: with SMTP id t67mr19063663itb.1.1545942316236; Thu, 27 Dec 2018 12:25:16 -0800 (PST) Date: Thu, 27 Dec 2018 13:24:42 -0700 In-Reply-To: <20181227202446.229042-1-sjg@chromium.org> Message-Id: <20181227202446.229042-8-sjg@chromium.org> Mime-Version: 1.0 References: <20181227202446.229042-1-sjg@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog From: Simon Glass To: U-Boot Mailing List Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH 07/11] tegra: sound: Add an audio hub driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a driver for the audio hub. This is modelled as a misc device which supports writing audio data from I2S. Signed-off-by: Simon Glass --- arch/arm/include/asm/arch-tegra/tegra_ahub.h | 475 +++++++++++++++++++ drivers/sound/Kconfig | 9 + drivers/sound/Makefile | 1 + drivers/sound/tegra_ahub.c | 256 ++++++++++ 4 files changed, 741 insertions(+) create mode 100644 arch/arm/include/asm/arch-tegra/tegra_ahub.h create mode 100644 drivers/sound/tegra_ahub.c diff --git a/arch/arm/include/asm/arch-tegra/tegra_ahub.h b/arch/arm/include/asm/arch-tegra/tegra_ahub.h new file mode 100644 index 00000000000..96d542a91ca --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/tegra_ahub.h @@ -0,0 +1,475 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * tegra_ahub.h - Definitions for Tegra124 audio hub driver + * Taken from dc tegra_ahub.h + * + * Copyright 2018 Google LLC + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA_AHUB_H_ +#define _TEGRA_AHUB_H_ + +/* + * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio + * transmitted by a particular TX CIF. + */ +struct xbar_regs { + u32 apbif_rx0; /* AUDIO_APBIF_RX0, offset 0x00 */ + u32 apbif_rx1; /* AUDIO_APBIF_RX1, offset 0x04 */ + u32 apbif_rx2; /* AUDIO_APBIF_RX2, offset 0x08 */ + u32 apbif_rx3; /* AUDIO_APBIF_RX3, offset 0x0C */ + + u32 i2s0_rx0; /* AUDIO_I2S0_RX0, offset 0x10 */ + u32 i2s1_rx0; /* AUDIO_I2S1_RX0, offset 0x14 */ + u32 i2s2_rx0; /* AUDIO_I2S2_RX0, offset 0x18 */ + u32 i2s3_rx0; /* AUDIO_I2S3_RX0, offset 0x1C */ + u32 i2s4_rx0; /* AUDIO_I2S4_RX0, offset 0x20 */ + + u32 dam0_rx0; /* AUDIO_DAM0_RX0, offset 0x24 */ + u32 dam0_rx1; /* AUDIO_DAM0_RX1, offset 0x28 */ + u32 dam1_rx0; /* AUDIO_DAM1_RX0, offset 0x2C */ + u32 dam1_rx1; /* AUDIO_DAM1_RX1, offset 0x30 */ + u32 dam2_rx0; /* AUDIO_DAM2_RX0, offset 0x34 */ + u32 dam2_rx1; /* AUDIO_DAM2_RX1, offset 0x38 */ + + u32 spdif_rx0; /* AUDIO_SPDIF_RX0, offset 0x3C */ + u32 spdif_rx1; /* AUDIO_SPDIF_RX1, offset 0x40 */ + + u32 apbif_rx4; /* AUDIO_APBIF_RX4, offset 0x44 */ + u32 apbif_rx5; /* AUDIO_APBIF_RX4, offset 0x48 */ + u32 apbif_rx6; /* AUDIO_APBIF_RX4, offset 0x4C */ + u32 apbif_rx7; /* AUDIO_APBIF_RX4, offset 0x50 */ + u32 apbif_rx8; /* AUDIO_APBIF_RX4, offset 0x54 */ + u32 apbif_rx9; /* AUDIO_APBIF_RX4, offset 0x58 */ + + u32 amx0_rx0; /* AUDIO_AMX0_RX0, offset 0x5C */ + u32 amx0_rx1; /* AUDIO_AMX0_RX1, offset 0x60 */ + u32 amx0_rx2; /* AUDIO_AMX0_RX2, offset 0x64 */ + u32 amx0_rx3; /* AUDIO_AMX0_RX3, offset 0x68 */ + + u32 adx0_rx0; /* AUDIO_ADX0_RX0, offset 0x6C */ +}; + +struct apbif_regs { + u32 channel0_ctrl; /* APBIF_CHANNEL0_CTRL */ + u32 channel0_clr; /* APBIF_CHANNEL0_CLEAR */ + u32 channel0_stat; /* APBIF_CHANNEL0_STATUS */ + u32 channel0_txfifo; /* APBIF_CHANNEL0_TXFIFO */ + u32 channel0_rxfifo; /* APBIF_CHANNEL0_RXFIFO */ + u32 channel0_cif_tx0_ctrl; /* APBIF_AUDIOCIF_TX0_CTRL */ + u32 channel0_cif_rx0_ctrl; /* APBIF_AUDIOCIF_RX0_CTRL */ + u32 channel0_reserved0; /* RESERVED, offset 0x1C */ + /* ahub_channel1_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ + /* ahub_channel2_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ + /* ahub_channel3_ctrl/clr/stat/txfifo/rxfifl/ciftx/cifrx ... here */ + u32 reserved123[3 * 8]; + u32 config_link_ctrl; /* APBIF_CONFIG_LINK_CTRL_0, off 0x80 */ + u32 misc_ctrl; /* APBIF_MISC_CTRL_0, offset 0x84 */ + u32 apbdma_live_stat; /* APBIF_APBDMA_LIVE_STATUS_0 */ + u32 i2s_live_stat; /* APBIF_I2S_LIVE_STATUS_0 */ + u32 dam0_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ + u32 dam1_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ + u32 dam2_live_stat; /* APBIF_DAM0_LIVE_STATUS_0 */ + u32 spdif_live_stat; /* APBIF_SPDIF_LIVE_STATUS_0 */ + u32 i2s_int_mask; /* APBIF_I2S_INT_MASK_0, offset B0 */ + u32 dam_int_mask; /* APBIF_DAM_INT_MASK_0 */ + u32 reserved_int_mask; /* RESERVED, offset 0xB8 */ + u32 spdif_int_mask; /* APBIF_SPDIF_INT_MASK_0 */ + u32 apbif_int_mask; /* APBIF_APBIF_INT_MASK_0, off C0 */ + u32 reserved2_int_mask; /* RESERVED, offset 0xC4 */ + u32 i2s_int_stat; /* APBIF_I2S_INT_STATUS_0, offset C8 */ + u32 dam_int_stat; /* APBIF_DAM_INT_STATUS_0 */ + u32 reserved_int_stat; /* RESERVED, offset 0xD0 */ + u32 spdif_int_stat; /* APBIF_SPDIF_INT_STATUS_0 */ + u32 apbif_int_stat; /* APBIF_APBIF_INT_STATUS_0 */ + u32 reserved2_int_stat; /* RESERVED, offset 0xDC */ + u32 i2s_int_src; /* APBIF_I2S_INT_SOURCE_0, offset E0 */ + u32 dam_int_src; /* APBIF_DAM_INT_SOURCE_0 */ + u32 reserved_int_src; /* RESERVED, offset 0xE8 */ + u32 spdif_int_src; /* APBIF_SPDIF_INT_SOURCE_0 */ + u32 apbif_int_src; /* APBIF_APBIF_INT_SOURCE_0, off F0 */ + u32 reserved2_int_src; /* RESERVED, offset 0xF4 */ + u32 i2s_int_set; /* APBIF_I2S_INT_SET_0, offset 0xF8 */ + u32 dam_int_set; /* APBIF_DAM_INT_SET_0, offset 0xFC */ + u32 spdif_int_set; /* APBIF_SPDIF_INT_SET_0, off 0x100 */ + u32 apbif_int_set; /* APBIF_APBIF_INT_SET_0, off 0x104 */ +}; + +/* + * Tegra AHUB Registers Definition + */ +enum { + TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT = 24, + TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US = 0x3f, + TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK = + TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << + TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT, + + /* Channel count minus 1 */ + TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT = 20, + TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US = 0xf, + TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK = + TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << + TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT, + + /* Channel count minus 1 */ + TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT = 16, + TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US = 0xf, + TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK = + TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << + TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT, + + TEGRA_AUDIOCIF_BITS_4 = 0, + TEGRA_AUDIOCIF_BITS_8 = 1, + TEGRA_AUDIOCIF_BITS_12 = 2, + TEGRA_AUDIOCIF_BITS_16 = 3, + TEGRA_AUDIOCIF_BITS_20 = 4, + TEGRA_AUDIOCIF_BITS_24 = 5, + TEGRA_AUDIOCIF_BITS_28 = 6, + TEGRA_AUDIOCIF_BITS_32 = 7, + + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT = 12, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_MASK = + 7 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_4 = + TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_8 = + TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_12 = + TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_16 = + TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_20 = + TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_24 = + TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_28 = + TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_32 = + TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT, + + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT = 8, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_MASK = + 7 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_4 = + TEGRA_AUDIOCIF_BITS_4 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_8 = + TEGRA_AUDIOCIF_BITS_8 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_12 = + TEGRA_AUDIOCIF_BITS_12 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_16 = + TEGRA_AUDIOCIF_BITS_16 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_20 = + TEGRA_AUDIOCIF_BITS_20 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_24 = + TEGRA_AUDIOCIF_BITS_24 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_28 = + TEGRA_AUDIOCIF_BITS_28 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_32 = + TEGRA_AUDIOCIF_BITS_32 << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT, + + TEGRA_AUDIOCIF_EXPAND_ZERO = 0, + TEGRA_AUDIOCIF_EXPAND_ONE = 1, + TEGRA_AUDIOCIF_EXPAND_LFSR = 2, + + TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT = 6, + TEGRA_AUDIOCIF_CTRL_EXPAND_MASK = 3 << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, + TEGRA_AUDIOCIF_CTRL_EXPAND_ZERO = + TEGRA_AUDIOCIF_EXPAND_ZERO << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, + TEGRA_AUDIOCIF_CTRL_EXPAND_ONE = + TEGRA_AUDIOCIF_EXPAND_ONE << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, + TEGRA_AUDIOCIF_CTRL_EXPAND_LFSR = + TEGRA_AUDIOCIF_EXPAND_LFSR << TEGRA_AUDIOCIF_CTRL_EXPAND_SHIFT, + + TEGRA_AUDIOCIF_STEREO_CONV_CH0 = 0, + TEGRA_AUDIOCIF_STEREO_CONV_CH1 = 1, + TEGRA_AUDIOCIF_STEREO_CONV_AVG = 2, + + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT = 4, + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_MASK = + 3 << TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH0 = + TEGRA_AUDIOCIF_STEREO_CONV_CH0 << + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_CH1 = + TEGRA_AUDIOCIF_STEREO_CONV_CH1 << + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_AVG = + TEGRA_AUDIOCIF_STEREO_CONV_AVG << + TEGRA_AUDIOCIF_CTRL_STEREO_CONV_SHIFT, + + TEGRA_AUDIOCIF_CTRL_REPLICATE = 3, + + TEGRA_AUDIOCIF_DIRECTION_TX = 0, + TEGRA_AUDIOCIF_DIRECTION_RX = 1, + + TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT = 2, + TEGRA_AUDIOCIF_CTRL_DIRECTION_MASK = + 1 << TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, + TEGRA_AUDIOCIF_CTRL_DIRECTION_TX = + TEGRA_AUDIOCIF_DIRECTION_TX << + TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, + TEGRA_AUDIOCIF_CTRL_DIRECTION_RX = + TEGRA_AUDIOCIF_DIRECTION_RX << + TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT, + + TEGRA_AUDIOCIF_TRUNCATE_ROUND = 0, + TEGRA_AUDIOCIF_TRUNCATE_CHOP = 1, + + TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT = 1, + TEGRA_AUDIOCIF_CTRL_TRUNCATE_MASK = + 1 << TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, + TEGRA_AUDIOCIF_CTRL_TRUNCATE_ROUND = + TEGRA_AUDIOCIF_TRUNCATE_ROUND << + TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, + TEGRA_AUDIOCIF_CTRL_TRUNCATE_CHOP = + TEGRA_AUDIOCIF_TRUNCATE_CHOP << + TEGRA_AUDIOCIF_CTRL_TRUNCATE_SHIFT, + + TEGRA_AUDIOCIF_MONO_CONV_ZERO = 0, + TEGRA_AUDIOCIF_MONO_CONV_COPY = 1, + + TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT = 0, + TEGRA_AUDIOCIF_CTRL_MONO_CONV_MASK = + 1 << TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, + TEGRA_AUDIOCIF_CTRL_MONO_CONV_ZERO = + TEGRA_AUDIOCIF_MONO_CONV_ZERO << + TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, + TEGRA_AUDIOCIF_CTRL_MONO_CONV_COPY = + TEGRA_AUDIOCIF_MONO_CONV_COPY << + TEGRA_AUDIOCIF_CTRL_MONO_CONV_SHIFT, + + /* Registers within TEGRA_AUDIO_CLUSTER_BASE */ + + TEGRA_AHUB_CHANNEL_CTRL = 0x0, + TEGRA_AHUB_CHANNEL_CTRL_STRIDE = 0x20, + TEGRA_AHUB_CHANNEL_CTRL_COUNT = 4, + TEGRA_AHUB_CHANNEL_CTRL_TX_EN = 1 << 31, + TEGRA_AHUB_CHANNEL_CTRL_RX_EN = 1 << 30, + TEGRA_AHUB_CHANNEL_CTRL_LOOPBACK = 1 << 29, + + TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT = 16, + TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US = 0xff, + TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK = + TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << + TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT, + + TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT = 8, + TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US = 0xff, + TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK = + TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << + TEGRA_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT, + + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN = 1 << 6, + + TEGRA_PACK_8_4 = 2, + TEGRA_PACK_16 = 3, + + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT = 4, + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US = 3, + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK = + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_8_4 = + TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 = + TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT, + + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_EN = 1 << 2, + + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT = 0, + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US = 3, + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK = + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_8_4 = + TEGRA_PACK_8_4 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, + TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_16 = + TEGRA_PACK_16 << TEGRA_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT, + + /* TEGRA_AHUB_CHANNEL_CLEAR */ + + TEGRA_AHUB_CHANNEL_CLEAR = 0x4, + TEGRA_AHUB_CHANNEL_CLEAR_STRIDE = 0x20, + TEGRA_AHUB_CHANNEL_CLEAR_COUNT = 4, + TEGRA_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET = 1 << 31, + TEGRA_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET = 1 << 30, + + TEGRA_AHUB_CHANNEL_STATUS = 0x8, + TEGRA_AHUB_CHANNEL_STATUS_STRIDE = 0x20, + TEGRA_AHUB_CHANNEL_STATUS_COUNT = 4, + TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT = 24, + TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US = 0xff, + TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK = + TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << + TEGRA_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT, + TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT = 16, + TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US = 0xff, + TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK = + TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << + TEGRA_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT, + TEGRA_AHUB_CHANNEL_STATUS_TX_TRIG = 1 << 1, + TEGRA_AHUB_CHANNEL_STATUS_RX_TRIG = 1 << 0, + + TEGRA_AHUB_CHANNEL_TXFIFO = 0xc, + TEGRA_AHUB_CHANNEL_TXFIFO_STRIDE = 0x20, + TEGRA_AHUB_CHANNEL_TXFIFO_COUNT = 4, + + TEGRA_AHUB_CHANNEL_RXFIFO = 0x10, + TEGRA_AHUB_CHANNEL_RXFIFO_STRIDE = 0x20, + TEGRA_AHUB_CHANNEL_RXFIFO_COUNT = 4, + + TEGRA_AHUB_CIF_TX_CTRL = 0x14, + TEGRA_AHUB_CIF_TX_CTRL_STRIDE = 0x20, + TEGRA_AHUB_CIF_TX_CTRL_COUNT = 4, + /* Uses field from TEGRA_AUDIOCIF_CTRL_* */ + + TEGRA_AHUB_CIF_RX_CTRL = 0x18, + TEGRA_AHUB_CIF_RX_CTRL_STRIDE = 0x20, + TEGRA_AHUB_CIF_RX_CTRL_COUNT = 4, + /* Uses field from TEGRA_AUDIOCIF_CTRL_* */ + + TEGRA_AHUB_CONFIG_LINK_CTRL = 0x80, + TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT = 28, + TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US = 0xf, + TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK = + TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << + TEGRA_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT, + TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT = 16, + TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US = 0xfff, + TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK = + TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << + TEGRA_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT, + TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT = 4, + TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US = 0xfff, + TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK = + TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << + TEGRA_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT, + TEGRA_AHUB_CONFIG_LINK_CTRL_CG_EN = 1 << 2, + TEGRA_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR = 1 << 1, + TEGRA_AHUB_CONFIG_LINK_CTRL_SOFT_RESET = 1 << 0, + + TEGRA_AHUB_MISC_CTRL = 0x84, + TEGRA_AHUB_MISC_CTRL_AUDIO_ACTIVE = 1 << 31, + TEGRA_AHUB_MISC_CTRL_AUDIO_CG_EN = 1 << 8, + TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT = 0, + TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK = + 0x1f << TEGRA_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT, + + TEGRA_AHUB_APBDMA_LIVE_STATUS = 0x88, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL = 1 << 31, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL = 1 << 30, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL = 1 << 29, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL = 1 << 28, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL = 1 << 27, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL = 1 << 26, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL = 1 << 25, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL = 1 << 24, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY = 1 << 23, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY = 1 << 22, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY = 1 << 21, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY = 1 << 20, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY = 1 << 19, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY = 1 << 18, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY = 1 << 17, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY = 1 << 16, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL = 1 << 15, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL = 1 << 14, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL = 1 << 13, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL = 1 << 12, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL = 1 << 11, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL = 1 << 10, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL = 1 << 9, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL = 1 << 8, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY = 1 << 7, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY = 1 << 6, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY = 1 << 5, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY = 1 << 4, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY = 1 << 3, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY = 1 << 2, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY = 1 << 1, + TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY = 1 << 0, + + TEGRA_AHUB_I2S_LIVE_STATUS = 0x8c, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL = 1 << 29, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL = 1 << 28, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL = 1 << 27, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL = 1 << 26, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL = 1 << 25, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL = 1 << 24, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL = 1 << 23, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL = 1 << 22, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL = 1 << 21, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL = 1 << 20, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED = 1 << 19, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED = 1 << 18, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED = 1 << 17, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED = 1 << 16, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED = 1 << 15, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED = 1 << 14, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED = 1 << 13, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED = 1 << 12, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED = 1 << 11, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED = 1 << 10, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY = 1 << 9, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY = 1 << 8, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY = 1 << 7, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY = 1 << 6, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY = 1 << 5, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY = 1 << 4, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY = 1 << 3, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY = 1 << 2, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY = 1 << 1, + TEGRA_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY = 1 << 0, + + TEGRA_AHUB_DAM_LIVE_STATUS = 0x90, + TEGRA_AHUB_DAM_LIVE_STATUS_STRIDE = 0x8, + TEGRA_AHUB_DAM_LIVE_STATUS_COUNT = 3, + TEGRA_AHUB_DAM_LIVE_STATUS_TX_ENABLED = 1 << 26, + TEGRA_AHUB_DAM_LIVE_STATUS_RX1_ENABLED = 1 << 25, + TEGRA_AHUB_DAM_LIVE_STATUS_RX0_ENABLED = 1 << 24, + TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL = 1 << 15, + TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL = 1 << 9, + TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL = 1 << 8, + TEGRA_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY = 1 << 7, + TEGRA_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY = 1 << 1, + TEGRA_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY = 1 << 0, + + TEGRA_AHUB_SPDIF_LIVE_STATUS = 0xa8, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED = 1 << 11, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED = 1 << 10, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED = 1 << 9, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED = 1 << 8, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL = 1 << 7, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL = 1 << 6, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL = 1 << 5, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL = 1 << 4, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY = 1 << 3, + TEGRA_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY = 1 << 2, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY = 1 << 1, + TEGRA_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY = 1 << 0, + + TEGRA_AHUB_I2S_INT_MASK = 0xb0, + TEGRA_AHUB_DAM_INT_MASK = 0xb4, + TEGRA_AHUB_SPDIF_INT_MASK = 0xbc, + TEGRA_AHUB_APBIF_INT_MASK = 0xc0, + TEGRA_AHUB_I2S_INT_STATUS = 0xc8, + TEGRA_AHUB_DAM_INT_STATUS = 0xcc, + TEGRA_AHUB_SPDIF_INT_STATUS = 0xd4, + TEGRA_AHUB_APBIF_INT_STATUS = 0xd8, + TEGRA_AHUB_I2S_INT_SOURCE = 0xe0, + TEGRA_AHUB_DAM_INT_SOURCE = 0xe4, + TEGRA_AHUB_SPDIF_INT_SOURCE = 0xec, + TEGRA_AHUB_APBIF_INT_SOURCE = 0xf0, + TEGRA_AHUB_I2S_INT_SET = 0xf8, + TEGRA_AHUB_DAM_INT_SET = 0xfc, + TEGRA_AHUB_SPDIF_INT_SET = 0x100, + TEGRA_AHUB_APBIF_INT_SET = 0x104, + + TEGRA_AHUB_AUDIO_RX = 0x0, + TEGRA_AHUB_AUDIO_RX_STRIDE = 0x4, + TEGRA_AHUB_AUDIO_RX_COUNT = 17, +}; + +#endif /* _TEGRA_I2C_H_ */ diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig index 506a60a7c7b..cdd8d0f046c 100644 --- a/drivers/sound/Kconfig +++ b/drivers/sound/Kconfig @@ -31,6 +31,15 @@ config I2S_SAMSUNG option provides an implementation for sound_init() and sound_play(). +config I2S_TEGRA + bool "Enable I2C support for Nvidia Tegra SoCs" + depends on I2S + select TEGRA124_DMA + help + Nvidia Tegra SoCs support several I2S interfaces for sending audio + data to an audio codec. This option enables support for this, + using one of the available audio codec drivers. + config SOUND_MAX98088 bool "Support Maxim max98088 audio codec" depends on I2S diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index 238f33bbb40..98d4f13688e 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SOUND) += sound-uclass.o obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o obj-$(CONFIG_I2S_SAMSUNG) += samsung_sound.o +obj-$(CONFIG_I2S_TEGRA) += tegra_ahub.o obj-$(CONFIG_SOUND_WM8994) += wm8994.o obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o diff --git a/drivers/sound/tegra_ahub.c b/drivers/sound/tegra_ahub.c new file mode 100644 index 00000000000..c71fce9bb1c --- /dev/null +++ b/drivers/sound/tegra_ahub.c @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0+159 +/* + * Take from dc tegra_ahub.c + * + * Copyright 2018 Google LLC + */ + +#define LOG_CATEGORY UCLASS_MISC + +#include +#include +#include +#include +#include +#include +#include +#include "tegra_i2s_priv.h" + +struct tegra_ahub_priv { + struct apbif_regs *apbif_regs; + struct xbar_regs *xbar_regs; + u32 full_mask; + int capacity_words; /* FIFO capacity in words */ + + /* + * This is unset intially, but is set by tegra_ahub_ioctl() called + * from the misc_ioctl() in tegra_sound_probe() + */ + struct udevice *i2s; + struct udevice *dma; +}; + +static int tegra_ahub_xbar_enable_i2s(struct xbar_regs *regs, int i2s_id) +{ + /* + * Enables I2S as the receiver of APBIF by writing APBIF_TX0 (0x01) to + * the rx0 register + */ + switch (i2s_id) { + case 0: + writel(1, ®s->i2s0_rx0); + break; + case 1: + writel(1, ®s->i2s1_rx0); + break; + case 2: + writel(1, ®s->i2s2_rx0); + break; + case 3: + writel(1, ®s->i2s3_rx0); + break; + case 4: + writel(1, ®s->i2s4_rx0); + break; + default: + log_err("Invalid I2S component id: %d\n", i2s_id); + return -EINVAL; + } + return 0; +} + +static int tegra_ahub_apbif_is_full(struct udevice *dev) +{ + struct tegra_ahub_priv *priv = dev_get_priv(dev); + + return readl(&priv->apbif_regs->apbdma_live_stat) & priv->full_mask; +} + +/** + * tegra_ahub_wait_for_space() - Wait for space in the FIFO + * + * @return 0 if OK, -ETIMEDOUT if no space was available in time + */ +static int tegra_ahub_wait_for_space(struct udevice *dev) +{ + int i = 100000; + ulong start; + + /* Busy-wait initially, since this should take almost no time */ + while (i--) { + if (!tegra_ahub_apbif_is_full(dev)) + return 0; + } + + /* Failed, so do a slower loop for 100ms */ + start = get_timer(0); + while (tegra_ahub_apbif_is_full(dev)) { + if (get_timer(start) > 100) + return -ETIMEDOUT; + } + + return 0; +} + +static int tegra_ahub_apbif_send(struct udevice *dev, int offset, + const void *buf, int len) +{ + struct tegra_ahub_priv *priv = dev_get_priv(dev); + const u32 *data = (const u32 *)buf; + ssize_t written = 0; + + if (len % sizeof(*data)) { + log_err("Data size (%zd) must be aligned to %zd.\n", len, + sizeof(*data)); + return -EFAULT; + } + while (written < len) { + int ret = tegra_ahub_wait_for_space(dev); + + if (ret) + return ret; + + writel(*data++, &priv->apbif_regs->channel0_txfifo); + written += sizeof(*data); + } + + return written; +} + +static void tegra_ahub_apbif_set_cif(struct udevice *dev, u32 value) +{ + struct tegra_ahub_priv *priv = dev_get_priv(dev); + + writel(value, &priv->apbif_regs->channel0_cif_tx0_ctrl); +} + +static void tegra_ahub_apbif_enable_channel0(struct udevice *dev, + int fifo_threshold) +{ + struct tegra_ahub_priv *priv = dev_get_priv(dev); + + u32 ctrl = TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_EN | + TEGRA_AHUB_CHANNEL_CTRL_TX_PACK_16 | + TEGRA_AHUB_CHANNEL_CTRL_TX_EN; + + fifo_threshold--; /* fifo_threshold starts from 1 */ + ctrl |= (fifo_threshold << TEGRA_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT); + writel(ctrl, &priv->apbif_regs->channel0_ctrl); +} + +static u32 tegra_ahub_get_cif(bool is_receive, uint channels, + uint bits_per_sample, uint fifo_threshold) +{ + uint audio_bits = (bits_per_sample >> 2) - 1; + u32 val; + + channels--; /* Channels in CIF starts from 1 */ + fifo_threshold--; /* FIFO threshold starts from 1 */ + /* Assume input and output are always using same channel / bits */ + val = channels << TEGRA_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT | + channels << TEGRA_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT | + audio_bits << TEGRA_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT | + audio_bits << TEGRA_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT | + fifo_threshold << TEGRA_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT | + (is_receive ? TEGRA_AUDIOCIF_DIRECTION_RX << + TEGRA_AUDIOCIF_CTRL_DIRECTION_SHIFT : 0); + + return val; +} + +static int tegra_ahub_enable(struct udevice *dev) +{ + struct tegra_ahub_priv *priv = dev_get_priv(dev); + struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(priv->i2s); + u32 cif_ctrl = 0; + int ret; + + /* We use APBIF channel0 as a sender */ + priv->full_mask = TEGRA_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL; + priv->capacity_words = 8; + + /* + * FIFO is inactive until (fifo_threshold) of words are sent. For + * better performance, we want to set it to half of capacity. + */ + u32 fifo_threshold = priv->capacity_words / 2; + + /* + * Setup audio client interface (ACIF): APBIF (channel0) as sender and + * I2S as receiver + */ + cif_ctrl = tegra_ahub_get_cif(true, uc_priv->channels, + uc_priv->bitspersample, fifo_threshold); + tegra_i2s_set_cif_tx_ctrl(priv->i2s, cif_ctrl); + + cif_ctrl = tegra_ahub_get_cif(false, uc_priv->channels, + uc_priv->bitspersample, fifo_threshold); + tegra_ahub_apbif_set_cif(dev, cif_ctrl); + tegra_ahub_apbif_enable_channel0(dev, fifo_threshold); + + ret = tegra_ahub_xbar_enable_i2s(priv->xbar_regs, uc_priv->id); + if (ret) + return ret; + log_debug("ahub: channels=%d, bitspersample=%d, cif_ctrl=%x, fifo_threshold=%d, id=%d\n", + uc_priv->channels, uc_priv->bitspersample, cif_ctrl, + fifo_threshold, uc_priv->id); + + return 0; +} + +static int tegra_ahub_ioctl(struct udevice *dev, unsigned long request, + void *buf) +{ + struct tegra_ahub_priv *priv = dev_get_priv(dev); + + if (request != AHUB_MISCOP_SET_I2S) + return -ENOSYS; + + priv->i2s = *(struct udevice **)buf; + log_debug("i2s set to '%s'\n", priv->i2s->name); + + return tegra_ahub_enable(dev); +} + +static int tegra_ahub_probe(struct udevice *dev) +{ + struct tegra_ahub_priv *priv = dev_get_priv(dev); + ulong addr; + + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) { + log_debug("Invalid apbif address\n"); + return -EINVAL; + } + priv->apbif_regs = (struct apbif_regs *)addr; + + addr = dev_read_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) { + log_debug("Invalid xbar address\n"); + return -EINVAL; + } + priv->xbar_regs = (struct xbar_regs *)addr; + log_debug("ahub apbif_regs=%p, xbar_regs=%p\n", priv->apbif_regs, + priv->xbar_regs); + + return 0; +} + +static struct misc_ops tegra_ahub_ops = { + .write = tegra_ahub_apbif_send, + .ioctl = tegra_ahub_ioctl, +}; + +static const struct udevice_id tegra_ahub_ids[] = { + { .compatible = "nvidia,tegra124-ahub" }, + { } +}; + +U_BOOT_DRIVER(tegra_ahub) = { + .name = "tegra_ahub", + .id = UCLASS_MISC, + .of_match = tegra_ahub_ids, + .ops = &tegra_ahub_ops, + .probe = tegra_ahub_probe, + .priv_auto_alloc_size = sizeof(struct tegra_ahub_priv), +}; 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Thu, 27 Dec 2018 12:25:17 -0800 (PST) Date: Thu, 27 Dec 2018 13:24:43 -0700 In-Reply-To: <20181227202446.229042-1-sjg@chromium.org> Message-Id: <20181227202446.229042-9-sjg@chromium.org> Mime-Version: 1.0 References: <20181227202446.229042-1-sjg@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog From: Simon Glass To: U-Boot Mailing List Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH 08/11] tegra: sound: Add an I2S driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a driver which supports transmitting digital sound to an audio codec. This uses fixed parameters as a device-tree binding is not currently defined. Signed-off-by: Simon Glass --- arch/arm/include/asm/arch-tegra/tegra_i2s.h | 206 ++++++++++++++++++++ drivers/sound/Makefile | 2 +- drivers/sound/tegra_i2s.c | 124 ++++++++++++ drivers/sound/tegra_i2s_priv.h | 29 +++ 4 files changed, 360 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-tegra/tegra_i2s.h create mode 100644 drivers/sound/tegra_i2s.c create mode 100644 drivers/sound/tegra_i2s_priv.h diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2s.h b/arch/arm/include/asm/arch-tegra/tegra_i2s.h new file mode 100644 index 00000000000..9319383f7c1 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/tegra_i2s.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * tegra_i2s.h - Definitions for Tegra124 I2S driver. + * Note, some structures (ex, CIF) are different in Tegra114. + * + * NVIDIA Tegra I2S controller + * Modified from dc tegra_regs.h + * + * Copyright 2018 Google LLC + * + * Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved. + */ + +#ifndef _TEGRA_I2S_H_ +#define _TEGRA_I2S_H_ + +struct i2s_ctlr { + u32 ctrl; /* I2S_CTRL_0, 0x00 */ + u32 timing; /* I2S_TIMING_0, 0x04 */ + u32 offset; /* I2S_OFFSET_0, 0x08 */ + u32 ch_ctrl; /* I2S_CH_CTRL_0, 0x0C */ + u32 slot_ctrl; /* I2S_SLOT_CTRL_0, 0x10 */ + u32 cif_tx_ctrl; /* I2S_CIF_TX_CTRL_0, 0x14 */ + u32 cif_rx_ctrl; /* I2S_CIF_RX_CTRL_0, 0x18 */ + u32 flowctl; /* I2S_FLOWCTL_0, 0x1C */ + u32 tx_step; /* I2S_TX_STEP_0, 0x20 */ + u32 flow_status; /* I2S_FLOW_STATUS_0, 0x24 */ + u32 flow_total; /* I2S_FLOW_TOTAL_0, 0x28 */ + u32 flow_over; /* I2S_FLOW_OVER_0, 0x2C */ + u32 flow_under; /* I2S_FLOW_UNDER_0, 0x30 */ + u32 reserved[12]; /* RESERVED, 0x34 - 0x60 */ + u32 slot_ctrl2; /* I2S_SLOT_CTRL2_0, 0x64*/ +}; + +enum { + I2S_CTRL_XFER_EN_TX = 1 << 31, + I2S_CTRL_XFER_EN_RX = 1 << 30, + I2S_CTRL_CG_EN = 1 << 29, + I2S_CTRL_SOFT_RESET = 1 << 28, + I2S_CTRL_TX_FLOWCTL_EN = 1 << 27, + + I2S_CTRL_OBS_SEL_SHIFT = 24, + I2S_CTRL_OBS_SEL_MASK = 7 << I2S_CTRL_OBS_SEL_SHIFT, + + I2S_FRAME_FORMAT_LRCK = 0, + I2S_FRAME_FORMAT_FSYNC = 1, + + I2S_CTRL_FRAME_FORMAT_SHIFT = 12, + I2S_CTRL_FRAME_FORMAT_MASK = 7 << I2S_CTRL_FRAME_FORMAT_SHIFT, + I2S_CTRL_FRAME_FORMAT_LRCK = I2S_FRAME_FORMAT_LRCK << + I2S_CTRL_FRAME_FORMAT_SHIFT, + I2S_CTRL_FRAME_FORMAT_FSYNC = I2S_FRAME_FORMAT_FSYNC << + I2S_CTRL_FRAME_FORMAT_SHIFT, + + I2S_CTRL_MASTER_ENABLE = 1 << 10, + + I2S_LRCK_LEFT_LOW = 0, + I2S_LRCK_RIGHT_LOW = 1, + + I2S_CTRL_LRCK_SHIFT = 9, + I2S_CTRL_LRCK_MASK = 1 << I2S_CTRL_LRCK_SHIFT, + I2S_CTRL_LRCK_L_LOW = I2S_LRCK_LEFT_LOW << I2S_CTRL_LRCK_SHIFT, + I2S_CTRL_LRCK_R_LOW = I2S_LRCK_RIGHT_LOW << I2S_CTRL_LRCK_SHIFT, + + I2S_CTRL_LPBK_ENABLE = 1 << 8, + + I2S_BIT_CODE_LINEAR = 0, + I2S_BIT_CODE_ULAW = 1, + I2S_BIT_CODE_ALAW = 2, + + I2S_CTRL_BIT_CODE_SHIFT = 4, + I2S_CTRL_BIT_CODE_MASK = 3 << I2S_CTRL_BIT_CODE_SHIFT, + I2S_CTRL_BIT_CODE_LINEAR = I2S_BIT_CODE_LINEAR << + I2S_CTRL_BIT_CODE_SHIFT, + I2S_CTRL_BIT_CODE_ULAW = I2S_BIT_CODE_ULAW << I2S_CTRL_BIT_CODE_SHIFT, + I2S_CTRL_BIT_CODE_ALAW = I2S_BIT_CODE_ALAW << I2S_CTRL_BIT_CODE_SHIFT, + + I2S_BITS_8 = 1, + I2S_BITS_12 = 2, + I2S_BITS_16 = 3, + I2S_BITS_20 = 4, + I2S_BITS_24 = 5, + I2S_BITS_28 = 6, + I2S_BITS_32 = 7, + + /* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */ + I2S_CTRL_BIT_SIZE_SHIFT = 0, + I2S_CTRL_BIT_SIZE_MASK = 7 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_8 = I2S_BITS_8 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_12 = I2S_BITS_12 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_16 = I2S_BITS_16 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_20 = I2S_BITS_20 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_24 = I2S_BITS_24 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_28 = I2S_BITS_28 << I2S_CTRL_BIT_SIZE_SHIFT, + I2S_CTRL_BIT_SIZE_32 = I2S_BITS_32 << I2S_CTRL_BIT_SIZE_SHIFT, + + I2S_TIMING_NON_SYM_ENABLE = 1 << 12, + I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT = 0, + I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US = 0x7ff, + I2S_TIMING_CHANNEL_BIT_COUNT_MASK = + I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << + I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT, + + I2S_OFFSET_RX_DATA_OFFSET_SHIFT = 16, + I2S_OFFSET_RX_DATA_OFFSET_MASK_US = 0x7ff, + I2S_OFFSET_RX_DATA_OFFSET_MASK = I2S_OFFSET_RX_DATA_OFFSET_MASK_US << + I2S_OFFSET_RX_DATA_OFFSET_SHIFT, + I2S_OFFSET_TX_DATA_OFFSET_SHIFT = 0, + I2S_OFFSET_TX_DATA_OFFSET_MASK_US = 0x7ff, + I2S_OFFSET_TX_DATA_OFFSET_MASK = I2S_OFFSET_TX_DATA_OFFSET_MASK_US << + I2S_OFFSET_TX_DATA_OFFSET_SHIFT, + + /* FSYNC width - 1 in bit clocks */ + I2S_CH_CTRL_FSYNC_WIDTH_SHIFT = 24, + I2S_CH_CTRL_FSYNC_WIDTH_MASK_US = 0xff, + I2S_CH_CTRL_FSYNC_WIDTH_MASK = I2S_CH_CTRL_FSYNC_WIDTH_MASK_US << + I2S_CH_CTRL_FSYNC_WIDTH_SHIFT, + + I2S_HIGHZ_NO = 0, + I2S_HIGHZ_YES = 1, + I2S_HIGHZ_ON_HALF_BIT_CLK = 2, + + I2S_CH_CTRL_HIGHZ_CTRL_SHIFT = 12, + I2S_CH_CTRL_HIGHZ_CTRL_MASK = 3 << I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, + I2S_CH_CTRL_HIGHZ_CTRL_NO = I2S_HIGHZ_NO << + I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, + I2S_CH_CTRL_HIGHZ_CTRL_YES = I2S_HIGHZ_YES << + I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, + I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK = I2S_HIGHZ_ON_HALF_BIT_CLK << + I2S_CH_CTRL_HIGHZ_CTRL_SHIFT, + + I2S_MSB_FIRST = 0, + I2S_LSB_FIRST = 1, + + I2S_CH_CTRL_RX_BIT_ORDER_SHIFT = 10, + I2S_CH_CTRL_RX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_RX_BIT_ORDER_SHIFT, + I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST << + I2S_CH_CTRL_RX_BIT_ORDER_SHIFT, + I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST << + I2S_CH_CTRL_RX_BIT_ORDER_SHIFT, + I2S_CH_CTRL_TX_BIT_ORDER_SHIFT = 9, + I2S_CH_CTRL_TX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_TX_BIT_ORDER_SHIFT, + I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST << + I2S_CH_CTRL_TX_BIT_ORDER_SHIFT, + I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST << + I2S_CH_CTRL_TX_BIT_ORDER_SHIFT, + + I2S_POS_EDGE = 0, + I2S_NEG_EDGE = 1, + + I2S_CH_CTRL_EGDE_CTRL_SHIFT = 8, + I2S_CH_CTRL_EGDE_CTRL_MASK = 1 << I2S_CH_CTRL_EGDE_CTRL_SHIFT, + I2S_CH_CTRL_EGDE_CTRL_POS_EDGE = I2S_POS_EDGE << + I2S_CH_CTRL_EGDE_CTRL_SHIFT, + I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE = I2S_NEG_EDGE << + I2S_CH_CTRL_EGDE_CTRL_SHIFT, + + /* Sample size is # bits from BIT_SIZE minus this field */ + I2S_CH_CTRL_RX_MASK_BITS_SHIFT = 4, + I2S_CH_CTRL_RX_MASK_BITS_MASK_US = 7, + I2S_CH_CTRL_RX_MASK_BITS_MASK = I2S_CH_CTRL_RX_MASK_BITS_MASK_US << + I2S_CH_CTRL_RX_MASK_BITS_SHIFT, + + I2S_CH_CTRL_TX_MASK_BITS_SHIFT = 0, + I2S_CH_CTRL_TX_MASK_BITS_MASK_US = 7, + I2S_CH_CTRL_TX_MASK_BITS_MASK = I2S_CH_CTRL_TX_MASK_BITS_MASK_US << + I2S_CH_CTRL_TX_MASK_BITS_SHIFT, + + /* Number of slots in frame, minus 1 */ + I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT = 16, + I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US = 7, + I2S_SLOT_CTRL_TOTAL_SLOTS_MASK = I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US << + I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT, + + /* TDM mode slot enable bitmask */ + I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT = 8, + I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK = + 0xff << I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT, + + I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT = 0, + I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK = 0xff << + I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT, + + I2S_FILTER_LINEAR = 0, + I2S_FILTER_QUAD = 1, + + I2S_FLOWCTL_FILTER_SHIFT = 31, + I2S_FLOWCTL_FILTER_MASK = 1 << I2S_FLOWCTL_FILTER_SHIFT, + I2S_FLOWCTL_FILTER_LINEAR = I2S_FILTER_LINEAR << + I2S_FLOWCTL_FILTER_SHIFT, + I2S_FLOWCTL_FILTER_QUAD = I2S_FILTER_QUAD << I2S_FLOWCTL_FILTER_SHIFT, + + I2S_TX_STEP_SHIFT = 0, + I2S_TX_STEP_MASK_US = 0xffff, + I2S_TX_STEP_MASK = I2S_TX_STEP_MASK_US << I2S_TX_STEP_SHIFT, + + I2S_FLOW_STATUS_UNDERFLOW = 1 << 31, + I2S_FLOW_STATUS_OVERFLOW = 1 << 30, + I2S_FLOW_STATUS_MONITOR_INT_EN = 1 << 4, + I2S_FLOW_STATUS_COUNTER_CLR = 1 << 3, + I2S_FLOW_STATUS_MONITOR_CLR = 1 << 2, + I2S_FLOW_STATUS_COUNTER_EN = 1 << 1, + I2S_FLOW_STATUS_MONITOR_EN = 1 << 0, +}; + +#endif /* _TEGRA_I2C_H_ */ diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index 98d4f13688e..d444c28578a 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -10,7 +10,7 @@ obj-$(CONFIG_SOUND) += sound-uclass.o obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o obj-$(CONFIG_I2S_SAMSUNG) += samsung_sound.o -obj-$(CONFIG_I2S_TEGRA) += tegra_ahub.o +obj-$(CONFIG_I2S_TEGRA) += tegra_ahub.o tegra_i2s.o obj-$(CONFIG_SOUND_WM8994) += wm8994.o obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o diff --git a/drivers/sound/tegra_i2s.c b/drivers/sound/tegra_i2s.c new file mode 100644 index 00000000000..200d005fb6b --- /dev/null +++ b/drivers/sound/tegra_i2s.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google LLC + * Written by Simon Glass + */ +#define LOG_CATEGORY UCLASS_I2S +#define LOG_DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include "tegra_i2s_priv.h" + +int tegra_i2s_set_cif_tx_ctrl(struct udevice *dev, u32 value) +{ + struct i2s_uc_priv *priv = dev_get_uclass_priv(dev); + struct i2s_ctlr *regs = (struct i2s_ctlr *)priv->base_address; + + writel(value, ®s->cif_tx_ctrl); + + return 0; +} + +static void tegra_i2s_transmit_enable(struct i2s_ctlr *regs, int on) +{ + clrsetbits_le32(®s->ctrl, I2S_CTRL_XFER_EN_TX, + on ? I2S_CTRL_XFER_EN_TX : 0); +} + +static int i2s_tx_init(struct i2s_uc_priv *pi2s_tx) +{ + struct i2s_ctlr *regs = (struct i2s_ctlr *)pi2s_tx->base_address; + u32 audio_bits = (pi2s_tx->bitspersample >> 2) - 1; + u32 ctrl = readl(®s->ctrl); + + /* Set format to LRCK / Left Low */ + ctrl &= ~(I2S_CTRL_FRAME_FORMAT_MASK | I2S_CTRL_LRCK_MASK); + ctrl |= I2S_CTRL_FRAME_FORMAT_LRCK; + ctrl |= I2S_CTRL_LRCK_L_LOW; + + /* Disable all transmission until we are ready to transfer */ + ctrl &= ~(I2S_CTRL_XFER_EN_TX | I2S_CTRL_XFER_EN_RX); + + /* Serve as master */ + ctrl |= I2S_CTRL_MASTER_ENABLE; + + /* Configure audio bits size */ + ctrl &= ~I2S_CTRL_BIT_SIZE_MASK; + ctrl |= audio_bits << I2S_CTRL_BIT_SIZE_SHIFT; + writel(ctrl, ®s->ctrl); + + /* Timing in LRCK mode: */ + writel(pi2s_tx->bitspersample, ®s->timing); + + /* I2S mode has [TX/RX]_DATA_OFFSET both set to 1 */ + writel(((1 << I2S_OFFSET_RX_DATA_OFFSET_SHIFT) | + (1 << I2S_OFFSET_TX_DATA_OFFSET_SHIFT)), ®s->offset); + + /* FSYNC_WIDTH = 2 clocks wide, TOTAL_SLOTS = 2 slots per fsync */ + writel((2 - 1) << I2S_CH_CTRL_FSYNC_WIDTH_SHIFT, ®s->ch_ctrl); + writel((2 - 1), ®s->slot_ctrl); + + return 0; +} + +static int tegra_i2s_tx_data(struct udevice *dev, void *data, uint data_size) +{ + struct i2s_uc_priv *priv = dev_get_uclass_priv(dev); + struct i2s_ctlr *regs = (struct i2s_ctlr *)priv->base_address; + int ret; + + tegra_i2s_transmit_enable(regs, 1); + ret = misc_write(dev_get_parent(dev), 0, data, data_size); + tegra_i2s_transmit_enable(regs, 0); + if (ret < 0) + return ret; + else if (ret < data_size) + return -EIO; + + return 0; +} + +static int tegra_i2s_probe(struct udevice *dev) +{ + struct i2s_uc_priv *priv = dev_get_uclass_priv(dev); + ulong base; + + base = dev_read_addr(dev); + if (base == FDT_ADDR_T_NONE) { + debug("%s: Missing i2s base\n", __func__); + return -EINVAL; + } + priv->base_address = base; + priv->id = 1; + priv->audio_pll_clk = 4800000; + priv->samplingrate = 48000; + priv->bitspersample = 16; + priv->channels = 2; + priv->rfs = 256; + priv->bfs = 32; + + return i2s_tx_init(priv); +} + +static const struct i2s_ops tegra_i2s_ops = { + .tx_data = tegra_i2s_tx_data, +}; + +static const struct udevice_id tegra_i2s_ids[] = { + { .compatible = "nvidia,tegra124-i2s" }, + { } +}; + +U_BOOT_DRIVER(tegra_i2s) = { + .name = "tegra_i2s", + .id = UCLASS_I2S, + .of_match = tegra_i2s_ids, + .probe = tegra_i2s_probe, + .ops = &tegra_i2s_ops, +}; diff --git a/drivers/sound/tegra_i2s_priv.h b/drivers/sound/tegra_i2s_priv.h new file mode 100644 index 00000000000..7cd3fc808c8 --- /dev/null +++ b/drivers/sound/tegra_i2s_priv.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 Google LLC + * Written by Simon Glass + */ + +#ifndef __TEGRA_I2S_PRIV_H +#define __TEGRA_I2S_PRIV_H + +enum { + /* Set i2s device (in buf) */ + AHUB_MISCOP_SET_I2S, +}; + +/* + * tegra_i2s_set_cif_tx_ctrl() - Set the I2C port to send to + * + * The CIF is not really part of I2S -- it's for Audio Hub to control + * the interface between I2S and Audio Hub. However since it's put in + * the I2S registers domain instead of the Audio Hub, we need to export + * this as a function. + * + * @dev: I2S device + * @value: Value to write to CIF_TX_CTRL register + * @return 0 + */ +int tegra_i2s_set_cif_tx_ctrl(struct udevice *dev, u32 value); + +#endif From patchwork Thu Dec 27 20:24:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1018997 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="iQRJ6U1S"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43QhHL3ZKnz9s55 for ; Fri, 28 Dec 2018 07:28:14 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2AE18C21DD7; Thu, 27 Dec 2018 20:27:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B2784C21E15; Thu, 27 Dec 2018 20:25:26 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 00CDBC21D56; Thu, 27 Dec 2018 20:25:20 +0000 (UTC) Received: from mail-qt1-f200.google.com (mail-qt1-f200.google.com [209.85.160.200]) by lists.denx.de (Postfix) with ESMTPS id 824C0C21E15 for ; Thu, 27 Dec 2018 20:25:20 +0000 (UTC) Received: by mail-qt1-f200.google.com with SMTP id q3so25698243qtq.15 for ; Thu, 27 Dec 2018 12:25:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=//RobbfnBKaOAwVXbzXNEUxQSw1fLdwte3k/gAzrdjE=; b=iQRJ6U1Sq7Bs67R29kbEd9MRqg4ikd4Qg8vN5CsvCg7CnhClIKOJp8XCzDO6MeYGfl GTyIA3AcmgCY9iOAxFOb8yY53c5uajFRxOL8KAzYxs7kIu/QxsyKap7uC9njKw6bszWN VK/w/FoDCaEFvtWqOVLYq8CD8pAobs4GDg9P4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=//RobbfnBKaOAwVXbzXNEUxQSw1fLdwte3k/gAzrdjE=; b=jASdfPQuTSUZEDC+v+BuL6d2DdUWr5xXfpOllCsbUZuYcoeVp/ayyvkRRadNZbM147 wJTaWJyPhy3rklzim1ccLT20wFQt8IrgRkuUDzsil7K+ChlNxDvzXMl+7lOWqnAr+fQF v46pvNCgycM/Mw0jrdVg0wWZtOawecAcpY9nX6ycIePbWuXfbEJlgpSczA8OzG/ZyyEf iYb1E4FUnfHdH6oCbKVEEdzYNJJD7+brSX9obdD8ogFXgpBGea+GnpWn11GrByQHkcmA y/LgdTDfRWN2EXWGJ3rmanovu0tbXNUNYQOIk3Giq/zjOHDu1Of9krHa/VvvyZ2Ci6NW PUSQ== X-Gm-Message-State: AA+aEWax03cML4d9RXQrQjCoicJbpP0GzTsQbFQu9t8dqvIWjWENKCrz RqDsEVkUJuAEeFq+AdUo9HeRHpMLOaDMll1k X-Google-Smtp-Source: AFSGD/V6NHDhhSw+6PKXuStpE5uiD22aVr/B3l54yuZPhYoeBsJv/uGtP8YP9JI2nkQzJS9w+FOnUuViEXanlBxp X-Received: by 2002:ac8:2345:: with SMTP id b5mr17995036qtb.41.1545942319635; Thu, 27 Dec 2018 12:25:19 -0800 (PST) Date: Thu, 27 Dec 2018 13:24:44 -0700 In-Reply-To: <20181227202446.229042-1-sjg@chromium.org> Message-Id: <20181227202446.229042-10-sjg@chromium.org> Mime-Version: 1.0 References: <20181227202446.229042-1-sjg@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog From: Simon Glass To: U-Boot Mailing List Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH 09/11] sound: tegra: Add a sound driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a sound driver for tegra devices. This connects the audio hub, I2S controller and audio codec to allow sound output. Signed-off-by: Simon Glass --- drivers/sound/Makefile | 2 +- drivers/sound/tegra_sound.c | 100 ++++++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 drivers/sound/tegra_sound.c diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index d444c28578a..6925f0b6ec2 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -10,7 +10,7 @@ obj-$(CONFIG_SOUND) += sound-uclass.o obj-$(CONFIG_I2S_SAMSUNG) += samsung-i2s.o obj-$(CONFIG_SOUND_SANDBOX) += sandbox.o obj-$(CONFIG_I2S_SAMSUNG) += samsung_sound.o -obj-$(CONFIG_I2S_TEGRA) += tegra_ahub.o tegra_i2s.o +obj-$(CONFIG_I2S_TEGRA) += tegra_ahub.o tegra_i2s.o tegra_sound.o obj-$(CONFIG_SOUND_WM8994) += wm8994.o obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o diff --git a/drivers/sound/tegra_sound.c b/drivers/sound/tegra_sound.c new file mode 100644 index 00000000000..7c2ed53f5a7 --- /dev/null +++ b/drivers/sound/tegra_sound.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 Google, LLC + * Written by Simon Glass + */ + +#define LOG_CATEGORY UCLASS_I2S + +#include +#include +#include +#include +#include +#include +#include +#include "tegra_i2s_priv.h" + +static int tegra_sound_setup(struct udevice *dev) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct i2s_uc_priv *i2c_priv = dev_get_uclass_priv(uc_priv->i2s); + int ret; + + if (uc_priv->setup_done) + return -EALREADY; + ret = audio_codec_set_params(uc_priv->codec, i2c_priv->id, + i2c_priv->samplingrate, + i2c_priv->samplingrate * i2c_priv->rfs, + i2c_priv->bitspersample, + i2c_priv->channels); + if (ret) + return ret; + uc_priv->setup_done = true; + + return 0; +} + +static int tegra_sound_play(struct udevice *dev, void *data, uint data_size) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + + return i2s_tx_data(uc_priv->i2s, data, data_size); +} + +static int tegra_sound_probe(struct udevice *dev) +{ + struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct gpio_desc en_gpio; + struct udevice *ahub; + int ret; + + ret = gpio_request_by_name(dev, "codec-enable-gpio", 0, &en_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + ret = uclass_get_device_by_phandle(UCLASS_AUDIO_CODEC, dev, + "nvidia,audio-codec", + &uc_priv->codec); + if (ret) { + log_debug("Failed to probe audio codec\n"); + return ret; + } + ret = uclass_get_device_by_phandle(UCLASS_I2S, dev, + "nvidia,i2s-controller", + &uc_priv->i2s); + if (ret) { + log_debug("Cannot find i2s: %d\n", ret); + return ret; + } + + /* Set up the audio hub, telling it the currect i2s to use */ + ahub = dev_get_parent(uc_priv->i2s); + ret = misc_ioctl(ahub, AHUB_MISCOP_SET_I2S, &uc_priv->i2s); + if (ret) { + log_debug("Cannot set i2c: %d\n", ret); + return ret; + } + + log_debug("Probed sound '%s' with codec '%s' and i2s '%s'\n", dev->name, + uc_priv->codec->name, uc_priv->i2s->name); + + return 0; +} + +static const struct sound_ops tegra_sound_ops = { + .setup = tegra_sound_setup, + .play = tegra_sound_play, +}; + +static const struct udevice_id tegra_sound_ids[] = { + { .compatible = "nvidia,tegra-audio-max98090-nyan-big" }, + { } +}; + +U_BOOT_DRIVER(tegra_sound) = { + .name = "tegra_sound", + .id = UCLASS_SOUND, + .of_match = tegra_sound_ids, + .probe = tegra_sound_probe, + .ops = &tegra_sound_ops, +}; From patchwork Thu Dec 27 20:24:45 2018 Content-Type: text/plain; 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With this, 'sound play 1000 400' emits a simple beep. Signed-off-by: Simon Glass --- configs/nyan-big_defconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index ae6d76dfb20..b91da5b36d6 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_BOOTSTAGE=y CONFIG_BOOTSTAGE_STASH=y CONFIG_BOOTSTAGE_STASH_ADDR=0x83000000 CONFIG_SYS_STDIO_DEREGISTER=y +CONFIG_LOG_DEFAULT_LEVEL=7 CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SYS_PROMPT="Tegra124 (Nyan-big) # " # CONFIG_CMD_IMI is not set @@ -31,6 +32,8 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_NFS is not set CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y CONFIG_CMD_BOOTSTAGE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y @@ -58,12 +61,15 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_TEGRA=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y +CONFIG_SOUND=y +CONFIG_I2S=y +CONFIG_I2S_TEGRA=y +CONFIG_SOUND_MAX98090=y CONFIG_TEGRA114_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="NVIDIA" CONFIG_USB_GADGET_VENDOR_NUM=0x0955 From patchwork Thu Dec 27 20:24:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1019003 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="B3CIYzM7"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43QhMP48tgz9s8J for ; Fri, 28 Dec 2018 07:31:45 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 41009C21E16; Thu, 27 Dec 2018 20:29:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A762CC21E57; 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b=DtYVr1jdyGE35eMEggufnPvyX8au75WdwH7lsihWn4Y/oyQIPchqLGlLgapZR9T3+F HInUzR7m1L4WIGELgpcOX8T1s0cA+gO+ZvWVhYuIuGEvxtegx0USQg+P30+/ix4/Z6lq 5UZPQIl1DVN2qePCTSGzSSmjJO+8YGhxxT7a5LcoCnaCt9nV02CAHXrv3i2FMkGbZJSA PmP/D+ES78gM5T6z4M3y9+Oj76EMg95qADsg2ekS600Oq3VpO58vKT/342c9QzZ1AFVa hBtDswQGK1jx+WmTUm4Vc+xU8/IFbQi2Xj5YkhfEzvfValGLfQH+aPASIqEz+ipG0wOL FO8A== X-Gm-Message-State: AA+aEWZ76QlaQJBQnHLN0lR+j7S1ycRtaK1bevGyq96BvoCOMVsokKl/ WS6bt6SubSUYQNNiAltavuNLNKgai+BvuRip X-Google-Smtp-Source: AFSGD/V4EBAovPkYGEdru9+v2JTbQJ0Q2EkBjc7bCQYyt9EAH1O1A25s/0XZgKRW9UmHfYPB1gFPxOOUBtVTcAnG X-Received: by 2002:a24:46d5:: with SMTP id j204mr18590902itb.38.1545942322635; Thu, 27 Dec 2018 12:25:22 -0800 (PST) Date: Thu, 27 Dec 2018 13:24:46 -0700 In-Reply-To: <20181227202446.229042-1-sjg@chromium.org> Message-Id: <20181227202446.229042-12-sjg@chromium.org> Mime-Version: 1.0 References: <20181227202446.229042-1-sjg@chromium.org> X-Mailer: git-send-email 2.20.1.415.g653613c723-goog From: Simon Glass To: U-Boot Mailing List Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH 11/11] tegra: nyan: Add a README X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a short note about how to boot U-Boot on Nyan-big using tegrarcm. Signed-off-by: Simon Glass --- board/nvidia/nyan-big/README | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 board/nvidia/nyan-big/README diff --git a/board/nvidia/nyan-big/README b/board/nvidia/nyan-big/README new file mode 100644 index 00000000000..0e53d8d92fe --- /dev/null +++ b/board/nvidia/nyan-big/README @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2018 Google LLC +# Written by Simon Glass + +U-Boot on Nyan +============== + +Nyan-big is supported by mainline U-Boot. This device is based on Tegra124. +To build it, use the nyan-big config. + +To boot it, connect a USB A-A cable from your computer to the back USB port. +Connect a servo board. Then with t20_rec and warn_rst held down: + + sudo tegrarcm --bct cbootimage-configs/tegra124/nvidia/norrin/PM370_Hynix_2GB_H5TC4G63AFR_PBA_924MHz_01212014.bct + --bootloader u-boot-dtb-tegra.bin --loadaddr 0x80108000 + +The norrin config is close enough that it works well with Nyan.