From patchwork Wed Dec 26 10:34:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 1018632 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Uox+rtqk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43Pq9H1Wmyz9s9G for ; Wed, 26 Dec 2018 21:34:58 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726193AbeLZKe5 (ORCPT ); Wed, 26 Dec 2018 05:34:57 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:5365 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726177AbeLZKe5 (ORCPT ); Wed, 26 Dec 2018 05:34:57 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 26 Dec 2018 02:34:48 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 26 Dec 2018 02:34:56 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 26 Dec 2018 02:34:56 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 26 Dec 2018 10:34:55 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 26 Dec 2018 10:34:55 +0000 Received: from linux.nvidia.com (Not Verified[10.24.34.185]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 26 Dec 2018 02:34:54 -0800 From: Sameer Pujar To: , , CC: , , Sameer Pujar Subject: [PATCH] ALSA: hda/tegra: clear pending irq handlers Date: Wed, 26 Dec 2018 16:04:49 +0530 Message-ID: <1545820489-13292-1-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1545820488; bh=NaCIl8U1MGN6E4PPDIp9gLIUpCVjI6O15sE79xQBMcM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:Content-Type; b=Uox+rtqkwiRgHheE9xKUejeHljtNTp/LuWwlkrFDzQUCOFBNd8j9FhJPmU6xHqcJp Uu5Wzv+Aij2dQHLqEiFSVqnHdSGhsLh7vjnD1T31smNtRCHBBuTqGhdYJEhO+W+Cwl M6tDX4eJ0gCO1YD20kibZVL8voX+/z4NGtnVPUhU6Gg7WiRNBzG+s1XaHOZnei4fPZ vcIeB6XGRtEkHXYB/tuKDlKQ72pf05WQCOuLOyoTIahWX39gbqADuK61bRKdFSWnzU EveANr5VUNxJVnTYMz/oY4Z2eJie209yl47YQOR5rBw35Uo97vR9uDSOos6oeaEUj6 3BIQLm44xa4AA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Even after disabling interrupts on the module, it could be possible that irq handlers are still running. System hang is seen during suspend path. It was found that, there were pending writes on the HDA bus and clock was disabled by that time. Above mentioned issue is fixed by clearing any pending irq handlers before disabling clocks and returning from hda suspend. Suggested-by: Mohan Kumar Suggested-by: Dara Ramesh Signed-off-by: Sameer Pujar --- sound/pci/hda/hda_tegra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/pci/hda/hda_tegra.c b/sound/pci/hda/hda_tegra.c index 83befd8..97a176d 100644 --- a/sound/pci/hda/hda_tegra.c +++ b/sound/pci/hda/hda_tegra.c @@ -234,10 +234,12 @@ static int hda_tegra_suspend(struct device *dev) struct snd_card *card = dev_get_drvdata(dev); struct azx *chip = card->private_data; struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); + struct hdac_bus *bus = azx_bus(chip); snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); azx_stop_chip(chip); + synchronize_irq(bus->irq); azx_enter_link_reset(chip); hda_tegra_disable_clocks(hda);