From patchwork Fri Dec 21 08:08:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 1017392 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-492961-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=suse.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="PLJcpUaN"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43Lh8W4grVz9sDN for ; Fri, 21 Dec 2018 19:08:27 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:to:cc:subject:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=C9mrRkgAFroHePHj H8r0Go86mdHKw4Eu89/XQH9cXUAUGAu1XpzSO1eJc+FLIPy+54wVFTRT7/YaNvqT zie9mS88cH7Rypiklmq2t2mRd1JxmV2fnICUd/VeGbyznCmUCza58N2ZGoAu7C65 O0uc29ulyCe5oRP/pQcDxBEwo5U= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:to:cc:subject:mime-version:content-type :content-transfer-encoding; s=default; bh=p6PNaj90lMNlphVFklH5i3 FI6qk=; b=PLJcpUaNOBgPAWqV/UP5s36fr3oBYVGM7FIZ9adMcovzRfkM9N6cRF ZmrHKHofqBwva3ysO6k8iMWwvM1RdZYTp3E4DG19fsv6x8QqFPH5wFohDZvZRHr+ FUBFBV0RvbGVEWFiHBY9grhdpVvGuu4yO+7TJjhl+nfyyNymqTKqU= Received: (qmail 16206 invoked by alias); 21 Dec 2018 08:08:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16196 invoked by uid 89); 21 Dec 2018 08:08:19 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 spammy=helping, sae, symmetric, UD:immintrin.h X-HELO: prv1-mh.provo.novell.com Received: from prv1-mh.provo.novell.com (HELO prv1-mh.provo.novell.com) (137.65.248.33) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 21 Dec 2018 08:08:16 +0000 Received: from INET-PRV1-MTA by prv1-mh.provo.novell.com with Novell_GroupWise; Fri, 21 Dec 2018 01:08:14 -0700 Message-Id: <5C1C9F6D0200007800208632@prv1-mh.provo.novell.com> Date: Fri, 21 Dec 2018 01:08:13 -0700 From: "Jan Beulich" To: Cc: "Kirill Yukhin" , , Subject: [PATCH] x86-64: {,V}CVTSI2Sx are ambiguous without suffix Mime-Version: 1.0 Content-Disposition: inline For 64-bit these should not be emitted without suffix in AT&T mode (as being ambiguous that way); the suffixes are benign for 32-bit. For consistency also omit the suffix in Intel mode for {,V}CVTSI2SxQ. The omission has originally (prior to rev 260691) lead to wrong code being generated for the 64-bit unsigned-to-float/double conversions (as gas guesses an L suffix instead of the required Q one when the operand is in memory). In all remaining cases (being changed here) the omission would "just" lead to warnings with future gas versions. Since rex64suffix so far has been used also on {,V}CVTSx2SI (but not on VCVTSx2USI, as gas doesn't permit suffixes there), testsuite adjustments are also necessary for their test cases. Rather than making thinks check for the L suffixes in 32-bit cases, make things symmetric with VCVTSx2USI and drop the redundant suffixes instead, dropping the Q suffix expectations at the same time from the 64-bit cases. In order for related test cases to actually test what they're supposed to test, add (seemingly unrelated) a few empty "asm volatile()". Presumably there are more where constant propagation voids the intended effect of the tests, but these are ones helping make sure the assembler actually still assembles correctly the output after the changes here. gcc/ 2018-12-21 Jan Beulich * config/i386/i386.md (rex64suffix): Add L suffix for SI. * config/i386/sse.md (sse_cvtss2si, sse_cvtss2si_2, sse_cvttss2si, sse2_cvtsd2si, sse2_cvtsd2si_2, sse2_cvttsd2si): Drop . (cvtusi232, sse2_cvtsi2sd): Add {l}. (sse2_cvtsi2sdq): Make q conditional upon AT&T syntax. gcc/testsuite/ 2018-12-21 Jan Beulich * gcc.target/i386/avx512f-vcvtsd2si64-1.c, gcc.target/i386/avx512f-vcvtss2si64-1.c gcc.target/i386/avx512f-vcvttsd2si64-1.c gcc.target/i386/avx512f-vcvttss2si64-1.c: Drop q suffix expectation. * gcc.target/i386/avx512f-vcvtsi2ss-1.c, gcc.target/i386/avx512f-vcvtusi2sd-1.c, gcc.target/i386/avx512f-vcvtusi2ss-1.c: Expect l suffix. * gcc.target/i386/avx512f-vcvtusi2sd-2.c, gcc.target/i386/avx512f-vcvtusi2sd64-2.c, gcc.target/i386/avx512f-vcvtusi2ss-2.c, gcc.target/i386/avx512f-vcvtusi2ss64-2.c: Add asm volatile(). --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1162,7 +1162,7 @@ [(QI "V64QI") (HI "V32HI") (SI "V16SI") (DI "V8DI") (SF "V16SF") (DF "V8DF")]) ;; Instruction suffix for REX 64bit operators. -(define_mode_attr rex64suffix [(SI "") (DI "{q}")]) +(define_mode_attr rex64suffix [(SI "{l}") (DI "{q}")]) (define_mode_attr rex64namesuffix [(SI "") (DI "q")]) ;; This mode iterator allows :P to be used for patterns that operate on --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -4720,7 +4720,7 @@ (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE" - "%vcvtss2si\t{%1, %0|%0, %k1}" + "%vcvtss2si\t{%1, %0|%0, %k1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "bdver1_decode" "double,double") @@ -4733,7 +4733,7 @@ (unspec:SWI48 [(match_operand:SF 1 "nonimmediate_operand" "v,m")] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE" - "%vcvtss2si\t{%1, %0|%0, %k1}" + "%vcvtss2si\t{%1, %0|%0, %k1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") @@ -4749,7 +4749,7 @@ (match_operand:V4SF 1 "" "v,") (parallel [(const_int 0)]))))] "TARGET_SSE" - "%vcvttss2si\t{%1, %0|%0, %k1}" + "%vcvttss2si\t{%1, %0|%0, %k1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") @@ -4767,7 +4767,7 @@ (match_operand:VF_128 1 "register_operand" "v") (const_int 1)))] "TARGET_AVX512F && " - "vcvtusi2\t{%2, %1, %0|%0, %1, %2}" + "vcvtusi2{l}\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseicvt") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -5026,9 +5026,9 @@ (const_int 1)))] "TARGET_SSE2" "@ - cvtsi2sd\t{%2, %0|%0, %2} - cvtsi2sd\t{%2, %0|%0, %2} - vcvtsi2sd\t{%2, %1, %0|%0, %1, %2}" + cvtsi2sd{l}\t{%2, %0|%0, %2} + cvtsi2sd{l}\t{%2, %0|%0, %2} + vcvtsi2sd{l}\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,direct,*") @@ -5048,9 +5048,9 @@ (const_int 1)))] "TARGET_SSE2 && TARGET_64BIT" "@ - cvtsi2sdq\t{%2, %0|%0, %2} - cvtsi2sdq\t{%2, %0|%0, %2} - vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}" + cvtsi2sd{q}\t{%2, %0|%0, %2} + cvtsi2sd{q}\t{%2, %0|%0, %2} + vcvtsi2sd{q}\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,direct,*") @@ -5119,7 +5119,7 @@ (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2" - "%vcvtsd2si\t{%1, %0|%0, %q1}" + "%vcvtsd2si\t{%1, %0|%0, %q1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "bdver1_decode" "double,double") @@ -5133,7 +5133,7 @@ (unspec:SWI48 [(match_operand:DF 1 "nonimmediate_operand" "v,m")] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2" - "%vcvtsd2si\t{%1, %0|%0, %q1}" + "%vcvtsd2si\t{%1, %0|%0, %q1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") @@ -5149,7 +5149,7 @@ (match_operand:V2DF 1 "" "v,") (parallel [(const_int 0)]))))] "TARGET_SSE2" - "%vcvttsd2si\t{%1, %0|%0, %q1}" + "%vcvttsd2si\t{%1, %0|%0, %q1}" [(set_attr "type" "sseicvt") (set_attr "athlon_decode" "double,vector") (set_attr "amdfam10_decode" "double,double") --- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si64-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtsd2si64-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-O2 -mavx512f" } */ -/* { dg-final { scan-assembler-times "vcvtsd2siq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsd2si\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ #include --- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2ss-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtsi2ss-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mavx512f -O2" } */ -/* { dg-final { scan-assembler-times "vcvtsi2ss\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtsi2ssl\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ #include --- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si64-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtss2si64-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-O2 -mavx512f" } */ -/* { dg-final { scan-assembler-times "vcvtss2siq\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtss2si\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ #include --- a/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvttsd2si64-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-O2 -mavx512f" } */ -/* { dg-final { scan-assembler-times "vcvttsd2siq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttsd2siq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttsd2si\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttsd2si\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ #include --- a/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvttss2si64-1.c @@ -1,7 +1,7 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-O2 -mavx512f" } */ -/* { dg-final { scan-assembler-times "vcvttss2siq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvttss2siq\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttss2si\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvttss2si\[ \\t\]+\[^\{\n\]*\{sae\}\[^\n\]*%xmm\[0-9\]+.{6}(?:\n|\[ \\t\]+#)" 1 } } */ #include --- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-1.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-mavx512f -O2" } */ -/* { dg-final { scan-assembler-times "vcvtusi2sd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtusi2sdl\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ #include --- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd-2.c @@ -22,7 +22,9 @@ avx512f_test (void) s1.x = _mm_set_pd (-24.43, -43.35); s2 = 0xFEDCA987; + asm volatile ("" : "+m" (s2)); res.x = _mm_cvtu32_sd (s1.x, s2); + asm volatile ("" : "+m" (s2)); compute_vcvtusi2sd (s1.a, s2, res_ref); --- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd64-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2sd64-2.c @@ -22,7 +22,9 @@ avx512f_test (void) s1.x = _mm_set_pd (-24.43, -43.35); s2 = 0xFEDCBA9876543210; + asm volatile ("" : "+m" (s2)); res.x = _mm_cvtu64_sd (s1.x, s2); + asm volatile ("" : "+m" (s2)); compute_vcvtusi2sd (s1.a, s2, res_ref); --- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-1.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mavx512f -O2" } */ -/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ -/* { dg-final { scan-assembler-times "vcvtusi2ss\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtusi2ssl\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtusi2ssl\[ \\t\]+\[^%\n\]*%e\[^\{\n\]*\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ #include --- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss-2.c @@ -24,7 +24,9 @@ avx512f_test (void) s1.x = _mm_set_ps (-24.43, 68.346, -43.35, 546.46); s2 = 0xFEDCA987; + asm volatile ("" : "+m" (s2)); res.x = _mm_cvtu32_ss (s1.x, s2); + asm volatile ("" : "+m" (s2)); compute_vcvtusi2ss (s1.a, s2, res_ref); --- a/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss64-2.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-vcvtusi2ss64-2.c @@ -24,7 +24,9 @@ avx512f_test (void) s1.x = _mm_set_ps (-24.43, 68.346, -43.35, 546.46); s2 = 0xFEDCBA9876543210; + asm volatile ("" : "+m" (s2)); res.x = _mm_cvtu64_ss (s1.x, s2); + asm volatile ("" : "+m" (s2)); compute_vcvtusi2ss (s1.a, s2, res_ref);