From patchwork Wed Dec 19 03:11:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 1015806 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-492780-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="C3Cp4eWW"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43KKgc1z22z9s3Z for ; Wed, 19 Dec 2018 14:12:09 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=drN38ilfXHXtMcAE2EV60gdmm8p0SYAj92XUwzJpt+Ejy0Hd5Y JMlOuVM8fGpArSl7HVhL36OyeKMCWePwu61sMisTJY3CG+7QRGAVoSdl9pR9xIjt pxg1a0FeR5G/vd+thGQTUYf0uvsE+PciWnY6ParUw/slE6ioEoqlZtV/Q= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=QwMcMcPRb0qzy3q20ibeBDgc1sM=; b=C3Cp4eWWxhrJMQtmBsMw Vv991N1BHZFI9WMHjjWgXs/vBMe8cbrTfdpqIHrorDDW0n8Wvyc9eu81TZqIXhtA PfJI37ODepZW/Q7qHuvz1M7CEj1DWZz42R96kTVrsuL3nKdTmtcf6+M1BnR5Wizr yW/ZUfZ9xKuZss4X0W6R/yA= Received: (qmail 15977 invoked by alias); 19 Dec 2018 03:12:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15966 invoked by uid 89); 19 Dec 2018 03:12:00 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-27.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_LOW, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=H*Ad:D*huawei.com, mandatory, zhang, Zhang X-HELO: huawei.com Received: from szxga05-in.huawei.com (HELO huawei.com) (45.249.212.191) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 19 Dec 2018 03:11:58 +0000 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 3A34EDA32D3F8; Wed, 19 Dec 2018 11:11:53 +0800 (CST) Received: from localhost.localdomain (10.67.212.132) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.408.0; Wed, 19 Dec 2018 11:11:47 +0800 From: Shaokun Zhang To: CC: , , , , , , , "Shaokun Zhang" Subject: [PATCH] [aarch64] Revert support for ARMv8.2 in tsv110 Date: Wed, 19 Dec 2018 11:11:33 +0800 Message-ID: <1545189093-47026-1-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 X-IsSubscribed: yes For HiSilicon's tsv110 cpu core, it supports some v8_4A features, but some mandatory features are not implemented. Revert to ARMv8.2 that all mandatory features are supported. --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64-cores.def | 6 +++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e9f5baa6557c..842876b0ae90 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-12-19 Shaokun Zhang + + * config/aarch64/aarch64-cores.def (tsv110) : Revert support for ARMv8.2 + in tsv110. + 2018-12-18 Vladimir Makarov PR rtl-optimization/87759 diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 74be5dbf2595..20f4924e084d 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -96,10 +96,10 @@ AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 AARCH64_CORE("cortex-a76", cortexa76, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1) AARCH64_CORE("ares", ares, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, cortexa72, 0x41, 0xd0c, -1) -/* ARMv8.4-A Architecture Processors. */ - /* HiSilicon ('H') cores. */ -AARCH64_CORE("tsv110", tsv110, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110, 0x48, 0xd01, -1) +AARCH64_CORE("tsv110", tsv110, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2, tsv110, 0x48, 0xd01, -1) + +/* ARMv8.4-A Architecture Processors. */ /* Qualcomm ('Q') cores. */ AARCH64_CORE("saphira", saphira, saphira, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira, 0x51, 0xC01, -1)