From patchwork Tue Dec 18 19:06:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivien Didelot X-Patchwork-Id: 1015568 X-Patchwork-Delegate: linville@tuxdriver.com Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ckHiEeaf"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43K6vr0x80z9s4s for ; Wed, 19 Dec 2018 06:07:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726746AbeLRTHD (ORCPT ); Tue, 18 Dec 2018 14:07:03 -0500 Received: from mail-qt1-f196.google.com ([209.85.160.196]:42099 "EHLO mail-qt1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726652AbeLRTHC (ORCPT ); Tue, 18 Dec 2018 14:07:02 -0500 Received: by mail-qt1-f196.google.com with SMTP id d19so19418533qtq.9 for ; Tue, 18 Dec 2018 11:07:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nwyVGjOuj9Sg4W0qeON0imb6Eq4qE1aGRgf5W+oAQnE=; b=ckHiEeafBfT5OftOys7pQ+j9j4sytdn3drVZ8apGS3jyiQJ0V4cA7TGLYaKuybejXL bMl6u0v8uX8cwEPBGPzcUL7s2QD/alkb34KO/T0FR3meMpE9HPChM/+5OUKhpum5Yc1y DhHT0nDc73u/lcFgHytx4E/vvv5oQSe4oNzj9u7kb70Fz+ne6evo722r0N8ira0QuHmj vIACgmeaQnIFAxRwRpZe1Qvl8l3AXqSabThEMOAx9j6bqq2bH/CPLejxqYnxhYpyUuGW 17RPB8fVcEuVUf5sO8vJzuJAdrZQP7Lp402o/Y0XXY1BjwJBDN/WPGcTKqPactMUuNd3 DqvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nwyVGjOuj9Sg4W0qeON0imb6Eq4qE1aGRgf5W+oAQnE=; b=C6zYIIcflxRv3T2mEMis6lP0+vjDRT7LBBl2KvpnEM7rUUzhqg8toI6cmbaETLFQPS lKhTcKCcv5gjhVY7OeRRAb0hDkc31ToMO6XWRmAz2D5RE3Yw+7BUI1Avl5cKfYjN68Xl GqEtQytxAcA70IVRQy1oUZzSrrOEzLmKrME2xJaoft8AVdolQOBE3eM+xSb908IdFwt5 CzJA9fydVH1BGXUm+K1zzl18RNePR+MeoR40/f0m8B9TLIr3EOx3SRSZXwMfkQmaJyQM a28xuLPa3lc+Ytu4s1t232DDyWVtvUBdqmxBTq+ytfyiEomXXpM8OCPzTJBL+QY8CGMa F+tQ== X-Gm-Message-State: AA+aEWaRUS8rZDoFt+UBT7E7VRzedbPUxRnt0NXHJ1JUNTIisF6YMG1l 6negQoGk1POGvqs6UXFfRpNMPRijWJQ= X-Google-Smtp-Source: AFSGD/XsYVWPPqI4S2zQHM5oFmw30klgAO68sc9ksQNk4HtE205c7CFBEVce0V/DcP86jQQXxc1xFQ== X-Received: by 2002:ac8:1a92:: with SMTP id x18mr7435115qtj.179.1545160020389; Tue, 18 Dec 2018 11:07:00 -0800 (PST) Received: from localhost (modemcable249.105-163-184.mc.videotron.ca. [184.163.105.249]) by smtp.gmail.com with ESMTPSA id 7sm669368qka.38.2018.12.18.11.06.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 11:06:59 -0800 (PST) From: Vivien Didelot To: netdev@vger.kernel.org Cc: Chris Healy , Vivien Didelot , "John W . Linville" , f.fainelli@gmail.com, andrew@lunn.ch Subject: [PATCH v2 1/7] ethtool: dsa: add pretty dump Date: Tue, 18 Dec 2018 14:06:35 -0500 Message-Id: <20181218190641.31883-2-vivien.didelot@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181218190641.31883-1-vivien.didelot@gmail.com> References: <20181218190641.31883-1-vivien.didelot@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch adds the preliminary bits for pretty dumping the registers of the "dsa" kernel drivers. This patch does not pretty dump anything yet. Following patches will add support for the "mv88e6xxx" DSA driver. Signed-off-by: Vivien Didelot --- Makefile.am | 2 +- dsa.c | 12 ++++++++++++ ethtool.c | 1 + internal.h | 3 +++ 4 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 dsa.c diff --git a/Makefile.am b/Makefile.am index 14f79b6..468eed1 100644 --- a/Makefile.am +++ b/Makefile.am @@ -9,7 +9,7 @@ ethtool_SOURCES = ethtool.c ethtool-copy.h internal.h net_tstamp-copy.h \ rxclass.c if ETHTOOL_ENABLE_PRETTY_DUMP ethtool_SOURCES += \ - amd8111e.c de2104x.c e100.c e1000.c et131x.c igb.c \ + amd8111e.c de2104x.c dsa.c e100.c e1000.c et131x.c igb.c \ fec_8xx.c ibm_emac.c ixgb.c ixgbe.c natsemi.c \ pcnet32.c realtek.c tg3.c marvell.c vioc.c \ smsc911x.c at76c50x-usb.c sfc.c stmmac.c \ diff --git a/dsa.c b/dsa.c new file mode 100644 index 0000000..83396b5 --- /dev/null +++ b/dsa.c @@ -0,0 +1,12 @@ +#include +#include + +#include "internal.h" + +int dsa_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) +{ + /* DSA per-driver register dump */ + + /* Fallback to hexdump */ + return 1; +} diff --git a/ethtool.c b/ethtool.c index 2f7e96b..f1f1ec2 100644 --- a/ethtool.c +++ b/ethtool.c @@ -1166,6 +1166,7 @@ static const struct { { "vmxnet3", vmxnet3_dump_regs }, { "fjes", fjes_dump_regs }, { "lan78xx", lan78xx_dump_regs }, + { "dsa", dsa_dump_regs }, #endif }; diff --git a/internal.h b/internal.h index b239dc7..84b0f9c 100644 --- a/internal.h +++ b/internal.h @@ -354,4 +354,7 @@ int fjes_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); /* MICROCHIP LAN78XX USB ETHERNET Controller */ int lan78xx_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); +/* Distributed Switch Architecture */ +int dsa_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs); + #endif /* ETHTOOL_INTERNAL_H__ */ From patchwork Tue Dec 18 19:06:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivien Didelot X-Patchwork-Id: 1015569 X-Patchwork-Delegate: linville@tuxdriver.com Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NiFvbGmo"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43K6vt39grz9rxp for ; Wed, 19 Dec 2018 06:07:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726788AbeLRTHF (ORCPT ); Tue, 18 Dec 2018 14:07:05 -0500 Received: from mail-qt1-f194.google.com ([209.85.160.194]:35696 "EHLO mail-qt1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726536AbeLRTHC (ORCPT ); Tue, 18 Dec 2018 14:07:02 -0500 Received: by mail-qt1-f194.google.com with SMTP id v11so19481732qtc.2 for ; Tue, 18 Dec 2018 11:07:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3YuT0NKixSBxQ9RVcjV0S9FAjxMPDaKFK8u+DYpndYY=; b=NiFvbGmoaOviDSKHCsgWhUgAPDBXjaO/o4nvMweyiC5+ri735rc86SYt/8KWOomYCX 6EPKVdB3faHGYxlODEk5vilMgSkfPAeejMusf/9/iiM1GTndKJ+aF6eCeYMnk6goL8Ia IWDz3GvcKUKfrskQwt1GKFJEjTBoDKM1G8YBVA7FiKF9dNW9vNoQYOTMmF6VmDZ0pKfH QWX/P1KYBqk8SvNScq/4Mo6H/sACe++zVGip6ysBB1KVLwvTyu7KexX92JSbW5vLNBtj HSoRYckFfMub/Iy/yc1tW6l5TY5yosYGi1fz073BUOEBYlnKMlXodr9AfjjkXfBVbIVF hksQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3YuT0NKixSBxQ9RVcjV0S9FAjxMPDaKFK8u+DYpndYY=; b=DtCzMfCISd5POV6+ybgRVE1rOMpp/eA1CWrYUDdKj7VVxfsHeTkCPrDZkpr8hRXT4z gABaAuROY3qPi0ZnrlZjl2ExZMWz00/NOOF56D9ri83dPjchlss4BPH1BPJxq6/ZUlbU jVNzj+DNBML41l5mAvQNs5a01nkK900WxOtmVz1xJfTUgciDNcS9LWV7j/zNTplXIo52 R5Sb6YQA8FUX8uJ6qZGPHp7nyS8G5za3UUhAznzsmS/JKrhRIduLi1XaP5BMTZbpI/x4 kfBTMeCWUauKOe0gxKERw7HYLPq1o7O2NDrWsujv6mviKMC6GT2XxY48kkVrLPMO9IAP 08lQ== X-Gm-Message-State: AA+aEWYZ2tJ14zIU0H9alQUVUlLVgpEV/AqxcakRdZspnsQ5zvDKO/hJ MJ5Avgynx6PNVeZ7Sx1+XQpatVSpPv4= X-Google-Smtp-Source: AFSGD/VxF70kjv8x2w5HJpwOEKSFohuLCMU9IeO9fFn5PGi3wHIH782VJtpf8q7cJRiVX6vKkGffig== X-Received: by 2002:a0c:c584:: with SMTP id a4mr18361690qvj.227.1545160021866; Tue, 18 Dec 2018 11:07:01 -0800 (PST) Received: from localhost (modemcable249.105-163-184.mc.videotron.ca. [184.163.105.249]) by smtp.gmail.com with ESMTPSA id v32sm648783qta.37.2018.12.18.11.07.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 11:07:01 -0800 (PST) From: Vivien Didelot To: netdev@vger.kernel.org Cc: Chris Healy , Vivien Didelot , "John W . Linville" , f.fainelli@gmail.com, andrew@lunn.ch Subject: [PATCH v2 2/7] ethtool: dsa: mv88e6xxx: add pretty dump Date: Tue, 18 Dec 2018 14:06:36 -0500 Message-Id: <20181218190641.31883-3-vivien.didelot@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181218190641.31883-1-vivien.didelot@gmail.com> References: <20181218190641.31883-1-vivien.didelot@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The mv88e6xxx DSA driver supports many Marvell devices all using 32 registers of 16 bits. However each devices have a slightly different register definition. This patch adds the boilerplate for providing an optional function per mv88e6xxx switch. It does not pretty dump anything yet. Signed-off-by: Vivien Didelot --- dsa.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/dsa.c b/dsa.c index 83396b5..5de60b2 100644 --- a/dsa.c +++ b/dsa.c @@ -3,9 +3,86 @@ #include "internal.h" +/* Macros and dump functions for the 16-bit mv88e6xxx per-port registers */ + +#define REG(_reg, _name, _val) \ + printf("%.02u: %-38.38s 0x%.4x\n", _reg, _name, _val) + +#define FIELD(_name, _fmt, ...) \ + printf(" %-36.36s " _fmt "\n", _name, ##__VA_ARGS__) + +#define FIELD_BITMAP(_name, _val) \ + FIELD(_name, "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", \ + ((_val) & 0x0001) ? "0 " : "", \ + ((_val) & 0x0002) ? "1 " : "", \ + ((_val) & 0x0004) ? "2 " : "", \ + ((_val) & 0x0008) ? "3 " : "", \ + ((_val) & 0x0010) ? "4 " : "", \ + ((_val) & 0x0020) ? "5 " : "", \ + ((_val) & 0x0040) ? "6 " : "", \ + ((_val) & 0x0080) ? "7 " : "", \ + ((_val) & 0x0100) ? "8 " : "", \ + ((_val) & 0x0200) ? "9 " : "", \ + ((_val) & 0x0400) ? "10 " : "", \ + ((_val) & 0x0800) ? "11 " : "", \ + ((_val) & 0x1000) ? "12 " : "", \ + ((_val) & 0x2000) ? "13 " : "", \ + ((_val) & 0x4000) ? "14 " : "", \ + ((_val) & 0x8000) ? "15 " : "") + +struct dsa_mv88e6xxx_switch { + void (*dump)(int reg, u16 val); + const char *name; + u16 id; +}; + +static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = { +}; + +static int dsa_mv88e6xxx_dump_regs(struct ethtool_regs *regs) +{ + const struct dsa_mv88e6xxx_switch *sw = NULL; + const u16 *data = (u16 *)regs->data; + u16 id; + int i; + + /* Marvell chips have 32 per-port 16-bit registers */ + if (regs->len < 32 * 2) + return 1; + + id = regs->version & 0xfff0; + + for (i = 0; i < ARRAY_SIZE(dsa_mv88e6xxx_switches); i++) { + if (id == dsa_mv88e6xxx_switches[i].id) { + sw = &dsa_mv88e6xxx_switches[i]; + break; + } + } + + if (!sw) + return 1; + + printf("%s Switch Port Registers\n", sw->name); + printf("------------------------------\n"); + + for (i = 0; i < 32; i++) + if (sw->dump) + sw->dump(i, data[i]); + else + REG(i, "", data[i]); + + return 0; +} + +#undef FIELD_BITMAP +#undef FIELD +#undef REG + int dsa_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs) { /* DSA per-driver register dump */ + if (!dsa_mv88e6xxx_dump_regs(regs)) + return 0; /* Fallback to hexdump */ return 1; From patchwork Tue Dec 18 19:06:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivien Didelot X-Patchwork-Id: 1015571 X-Patchwork-Delegate: linville@tuxdriver.com Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Yg75N1tF"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43K6vy4yMFz9rxp for ; Wed, 19 Dec 2018 06:07:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726828AbeLRTHJ (ORCPT ); Tue, 18 Dec 2018 14:07:09 -0500 Received: from mail-qk1-f196.google.com ([209.85.222.196]:41453 "EHLO mail-qk1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726652AbeLRTHF (ORCPT ); Tue, 18 Dec 2018 14:07:05 -0500 Received: by mail-qk1-f196.google.com with SMTP id 189so10154191qkj.8 for ; Tue, 18 Dec 2018 11:07:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=puL4T/b/sSthaJjWm5wM4EjIZFVGYFzvCDlA7dgvtjk=; b=Yg75N1tFauvqo5ziJuHR7pIgqGZTlvnwJ/9kPUJR3Xj+K3g2pD5VsFeZ2UZyx86wv+ 9zVDkE8rDmXD/t3GyGPm7wOBz4120ie/VBRL+HGUyktJo1kQp1baeBaQxfokIyYpcR45 X6dwhFqoz/c/cTE+I8Dgwrv+BYlDgHpZ/qjRkuQwSc/2A+0aLaNb8Z0H2Dx+4D53NsEm YXNYXNppPihHRBWF/1buvhtveVAIYQAEPx8csP/pRXazv5G3AdgfqhtORaTpO3c46Aso 1L6PZZnYFvBoyJ5hSG/sV0s3O70jCdOxF0WiZAt8xq5cEByl3s5wEdjVrHCspFvZgWbF 5BJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=puL4T/b/sSthaJjWm5wM4EjIZFVGYFzvCDlA7dgvtjk=; b=CQBUVSQ7TjsD2b3EcdhARtoRf3iqzrpYA69jC2bUfIXOK8fRyMO58uTaUOdmEIe2DC 5g9yzQZUqp+QNCZNQ/ympfEyF2Uz0O7d3n24m3Z2KzJsOQk5gGGbMWt8Dzye4g8M9CN5 lI7ayfN/l+uvWp6x7qWIsSiCab/ZwYHz3OsRRo9bDUbCWpWFXST9Okhb4A4e7KLtOJ2V AK5Wr1W/N/XVcaK0uMHLRKMgM6cQMf9sTx1aRcqSyph8M6K4eC3LgFjanxPEoU6LLGU0 VffA7f2Iz1pFCmc0x4s1OfRgxOBbIxjyIsrKzJmZI2FtaWbkFoT8bsTMuNtrqcL8+Id7 uvvA== X-Gm-Message-State: AA+aEWal3qlVHbfVVR3Q+WjRLb0nadI6m5TlKt127A2DRUo5itLvF6D5 MjpZw8B6zrO4k4NxfR5E3x74lnXfgC8= X-Google-Smtp-Source: AFSGD/X2QlORfYPJjnDkkB00QlaKLFmEFpUXkaLm6fTLr8xl1jy53lUADXc+EQ81sYcBvKDPRD+0hg== X-Received: by 2002:a37:8781:: with SMTP id j123mr17167096qkd.68.1545160023141; Tue, 18 Dec 2018 11:07:03 -0800 (PST) Received: from localhost (modemcable249.105-163-184.mc.videotron.ca. [184.163.105.249]) by smtp.gmail.com with ESMTPSA id b20sm719414qkb.17.2018.12.18.11.07.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 11:07:02 -0800 (PST) From: Vivien Didelot To: netdev@vger.kernel.org Cc: Chris Healy , Vivien Didelot , "John W . Linville" , f.fainelli@gmail.com, andrew@lunn.ch Subject: [PATCH v2 3/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6185 Date: Tue, 18 Dec 2018 14:06:37 -0500 Message-Id: <20181218190641.31883-4-vivien.didelot@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181218190641.31883-1-vivien.didelot@gmail.com> References: <20181218190641.31883-1-vivien.didelot@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch adds support for pretty dump the port registers of the 88E6185 switch. Signed-off-by: Vivien Didelot --- dsa.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/dsa.c b/dsa.c index 5de60b2..c7e3dd1 100644 --- a/dsa.c +++ b/dsa.c @@ -30,6 +30,66 @@ ((_val) & 0x4000) ? "14 " : "", \ ((_val) & 0x8000) ? "15 " : "") +static void dsa_mv88e6185(int reg, u16 val) +{ + switch (reg) { + case 0: + REG(reg, "Port Status", val); + break; + case 1: + REG(reg, "PCS Control", val); + break; + case 3: + REG(reg, "Switch Identifier", val); + break; + case 4: + REG(reg, "Port Control", val); + break; + case 5: + REG(reg, "Port Control 1", val); + break; + case 6: + REG(reg, "Port Base VLAN Map (Header)", val); + break; + case 7: + REG(reg, "Default VLAN ID & Priority", val); + break; + case 8: + REG(reg, "Port Control 2", val); + break; + case 9: + REG(reg, "Rate Control", val); + break; + case 10: + REG(reg, "Rate Control 2", val); + break; + case 11: + REG(reg, "Port Association Vector", val); + break; + case 16: + REG(reg, "InDiscardsLo Frame Counter", val); + break; + case 17: + REG(reg, "InDiscardsHi Frame Counter", val); + break; + case 18: + REG(reg, "InFiltered Frame Counter", val); + break; + case 19: + REG(reg, "OutFiltered Frame Counter", val); + break; + case 24: + REG(reg, "Tag Remap 0-3", val); + break; + case 25: + REG(reg, "Tag Remap 4-7", val); + break; + default: + REG(reg, "Reserved", val); + break; + } +}; + struct dsa_mv88e6xxx_switch { void (*dump)(int reg, u16 val); const char *name; @@ -37,6 +97,7 @@ struct dsa_mv88e6xxx_switch { }; static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = { + { .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 }, }; static int dsa_mv88e6xxx_dump_regs(struct ethtool_regs *regs) From patchwork Tue Dec 18 19:06:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivien Didelot X-Patchwork-Id: 1015570 X-Patchwork-Delegate: linville@tuxdriver.com Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gowtFjHa"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43K6vv70Qdz9rxp for ; Wed, 19 Dec 2018 06:07:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726811AbeLRTHH (ORCPT ); Tue, 18 Dec 2018 14:07:07 -0500 Received: from mail-qt1-f196.google.com ([209.85.160.196]:44776 "EHLO mail-qt1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726777AbeLRTHG (ORCPT ); Tue, 18 Dec 2018 14:07:06 -0500 Received: by mail-qt1-f196.google.com with SMTP id n32so19400276qte.11 for ; Tue, 18 Dec 2018 11:07:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/kFSpkB8URedeCGFXpNhSqrRFJDcGuO8XAaji4Fd1ko=; b=gowtFjHa2B1r3wfy1rBxrvLrLZBNUvBiPs1AJqWOE3s0gRqwhzI2KFjR+81yzQDEiB EMbdHmgS9uwMITfVyCn47urlLzxIqFZWt9M6+3bf3CdvBigldnhIrx6Xiogs3RftDzcR 69v6mFn2tTExT0f9XioHH4RoFJQ0V211a1w4hkeX+wumBstGk3pNrdwLTvrrJObaIXS0 3y31obbPhYwOOSkh4f9IbYkLokzAmF5yu98IlyHFFVfXZFxyroK42BJhXr6VX1XVEIlG M3Oy+B6HiKzO0Xy4ey0bjs9BrsRkd0PvTvAWJYBWNpEH8RWI9P5cW4BS+Cir5opSRlN0 IoQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/kFSpkB8URedeCGFXpNhSqrRFJDcGuO8XAaji4Fd1ko=; b=ZhDtk71hwrlkYsa/Yzbpr0qsu64PamfF4wMggSLln5jMj7hW/kZDAt6xvQEOFPWSai ooKCfOsJrS3uMZDIKQ5VJRPQFlCflwJ0uzS1YQt+TSxHgYeKZkooU0Ojxg2WOSaJ2oI7 M62So5jSzrLGcirblogd1MAAoN851hr9mloyKycxg4ubgQkU7ogJye8VHDqevp8Pq9bj X7xQ7uObOqVhouT7ghBoKtgXNcwjsSWryoCaintY4wYSLik/iWxsGTp7GEbSjWEvZVTb tKZaEMQPPpwLml5EVnxt7qHV3/sixqPuS70NAbAadNiyk4UDg7iBPmLNrz5ZDggkEXlU HtuA== X-Gm-Message-State: AA+aEWavbGjrfZDuz5u+RjMvZY2270wv1XSZsgLnsvoGK6pjxVR/GtAL +zDmpsM3NKCod5B7qIedovpMfC77SBM= X-Google-Smtp-Source: AFSGD/Ukl7m6PDRYMPxHPv7sjTXeddQoyafpQ6Ymkbou8rkQW/w4DMzk9NJNqlJFUjrOedyHqKi10g== X-Received: by 2002:ac8:3a64:: with SMTP id w91mr18894554qte.70.1545160024399; Tue, 18 Dec 2018 11:07:04 -0800 (PST) Received: from localhost (modemcable249.105-163-184.mc.videotron.ca. [184.163.105.249]) by smtp.gmail.com with ESMTPSA id y2sm357963qtb.88.2018.12.18.11.07.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 11:07:03 -0800 (PST) From: Vivien Didelot To: netdev@vger.kernel.org Cc: Chris Healy , Vivien Didelot , "John W . Linville" , f.fainelli@gmail.com, andrew@lunn.ch Subject: [PATCH v2 4/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6161 Date: Tue, 18 Dec 2018 14:06:38 -0500 Message-Id: <20181218190641.31883-5-vivien.didelot@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181218190641.31883-1-vivien.didelot@gmail.com> References: <20181218190641.31883-1-vivien.didelot@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch adds support for pretty dump the port registers of the 88E6161 and 88E6123 switches, which both share the same datasheet. Signed-off-by: Vivien Didelot --- dsa.c | 164 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/dsa.c b/dsa.c index c7e3dd1..ab21d01 100644 --- a/dsa.c +++ b/dsa.c @@ -30,6 +30,168 @@ ((_val) & 0x4000) ? "14 " : "", \ ((_val) & 0x8000) ? "15 " : "") +static void dsa_mv88e6161(int reg, u16 val) +{ + switch (reg) { + case 0: + REG(reg, "Port Status", val); + FIELD("Pause Enabled", "%u", !!(val & 0x8000)); + FIELD("My Pause", "%u", !!(val & 0x4000)); + FIELD("Half-duplex Flow Control", "%u", !!(val & 0x2000)); + FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000)); + FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down"); + FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half"); + FIELD("Speed", "%s", + (val & 0x0300) == 0x0000 ? "10 Mbps" : + (val & 0x0300) == 0x0100 ? "100 Mbps" : + (val & 0x0300) == 0x0200 ? "1000 Mbps" : + (val & 0x0300) == 0x0300 ? "Reserved" : "?"); + FIELD("Auto-Media Detect Disable", "%u", !!(val & 0x0040)); + FIELD("Transmitter Paused", "%u", !!(val & 0x0020)); + FIELD("Flow Control", "%u", !!(val & 0x0010)); + FIELD("Config Duplex", "%s", val & 0x0008 ? "Full" : "Half"); + FIELD("Config Mode", "0x%x", val & 0x0007); + break; + case 1: + REG(reg, "PCS Control", val); + FIELD("Flow Control's Forced value", "%u", !!(val & 0x0080)); + FIELD("Force Flow Control", "%u", !!(val & 0x0040)); + FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down"); + FIELD("Force Link", "%u", !!(val & 0x0010)); + FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half"); + FIELD("Force Duplex", "%u", !!(val & 0x0004)); + FIELD("Force Speed", "%s", + (val & 0x0003) == 0x0000 ? "10 Mbps" : + (val & 0x0003) == 0x0001 ? "100 Mbps" : + (val & 0x0003) == 0x0002 ? "1000 Mbps" : + (val & 0x0003) == 0x0003 ? "Not forced" : "?"); + break; + case 2: + REG(reg, "Jamming Control", val); + break; + case 3: + REG(reg, "Switch Identifier", val); + break; + case 4: + REG(reg, "Port Control", val); + FIELD("Source Address Filtering controls", "%s", + (val & 0xc000) == 0x0000 ? "Disabled" : + (val & 0xc000) == 0x4000 ? "Drop On Lock" : + (val & 0xc000) == 0x8000 ? "Drop On Unlock" : + (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?"); + FIELD("Egress Mode", "%s", + (val & 0x3000) == 0x0000 ? "Unmodified" : + (val & 0x3000) == 0x1000 ? "Untagged" : + (val & 0x3000) == 0x2000 ? "Tagged" : + (val & 0x3000) == 0x3000 ? "Reserved" : "?"); + FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800)); + FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400)); + FIELD("Frame Mode", "%s", + (val & 0x0300) == 0x0000 ? "Normal" : + (val & 0x0300) == 0x0100 ? "DSA" : + (val & 0x0300) == 0x0200 ? "Provider" : + (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?"); + FIELD("VLAN Tunnel", "%u", !!(val & 0x0080)); + FIELD("TagIfBoth", "%u", !!(val & 0x0040)); + FIELD("Initial Priority assignment", "%s", + (val & 0x0030) == 0x0000 ? "Defaults" : + (val & 0x0030) == 0x0010 ? "Tag Priority" : + (val & 0x0030) == 0x0020 ? "IP Priority" : + (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?"); + FIELD("Egress Flooding mode", "%s", + (val & 0x000c) == 0x0000 ? "No unknown DA" : + (val & 0x000c) == 0x0004 ? "No unknown multicast DA" : + (val & 0x000c) == 0x0008 ? "No unknown unicast DA" : + (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?"); + FIELD("Port State", "%s", + (val & 0x0003) == 0x0000 ? "Disabled" : + (val & 0x0003) == 0x0001 ? "Blocking/Listening" : + (val & 0x0003) == 0x0002 ? "Learning" : + (val & 0x0003) == 0x0003 ? "Forwarding" : "?"); + break; + case 5: + REG(reg, "Port Control 1", val); + FIELD("Message Port", "%u", !!(val & 0x8000)); + FIELD("Trunk Port", "%u", !!(val & 0x4000)); + FIELD("Trunk ID", "%u", (val & 0x0f00) >> 8); + FIELD("FID[5:4]", "0x%.2x", (val & 0x0003) << 4); + break; + case 6: + REG(reg, "Port Base VLAN Map (Header)", val); + FIELD("FID[3:0]", "0x%.2x", (val & 0xf000) >> 12); + FIELD_BITMAP("VLANTable", val & 0x003f); + break; + case 7: + REG(reg, "Default VLAN ID & Priority", val); + FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13); + FIELD("Force to use Default VID", "%u", !!(val & 0x1000)); + FIELD("Default VLAN Identifier", "%u", val & 0x0fff); + break; + case 8: + REG(reg, "Port Control 2", val); + FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000)); + FIELD("Jumbo Mode", "%s", + (val & 0x3000) == 0x0000 ? "1522" : + (val & 0x3000) == 0x1000 ? "2048" : + (val & 0x3000) == 0x2000 ? "10240" : + (val & 0x3000) == 0x3000 ? "Reserved" : "?"); + FIELD("802.1QMode", "%s", + (val & 0x0c00) == 0x0000 ? "Disabled" : + (val & 0x0c00) == 0x0400 ? "Fallback" : + (val & 0x0c00) == 0x0800 ? "Check" : + (val & 0x0c00) == 0x0c00 ? "Secure" : "?"); + FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200)); + FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100)); + FIELD("Map using DA hits", "%u", !!(val & 0x0080)); + FIELD("ARP Mirror enable", "%u", !!(val & 0x0040)); + FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020)); + FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010)); + break; + case 9: + REG(reg, "Egress Rate Control", val); + break; + case 10: + REG(reg, "Egress Rate Control 2", val); + break; + case 11: + REG(reg, "Port Association Vector", val); + break; + case 12: + REG(reg, "Port ATU Control", val); + break; + case 13: + REG(reg, "Priority Override", val); + break; + case 15: + REG(reg, "PortEType", val); + break; + case 16: + REG(reg, "InDiscardsLo Frame Counter", val); + break; + case 17: + REG(reg, "InDiscardsHi Frame Counter", val); + break; + case 18: + REG(reg, "InFiltered Frame Counter", val); + break; + case 19: + REG(reg, "OutFiltered Frame Counter", val); + break; + case 24: + REG(reg, "Tag Remap 0-3", val); + break; + case 25: + REG(reg, "Tag Remap 4-7", val); + break; + case 27: + REG(reg, "Queue Counters", val); + break; + default: + REG(reg, "Reserved", val); + break; + } +} + static void dsa_mv88e6185(int reg, u16 val) { switch (reg) { @@ -97,6 +259,8 @@ struct dsa_mv88e6xxx_switch { }; static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = { + { .id = 0x1210, .name = "88E6123 ", .dump = dsa_mv88e6161 }, + { .id = 0x1610, .name = "88E6161 ", .dump = dsa_mv88e6161 }, { .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 }, }; From patchwork Tue Dec 18 19:06:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivien Didelot X-Patchwork-Id: 1015572 X-Patchwork-Delegate: linville@tuxdriver.com Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="kYONDuUX"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43K6vz5WHZz9rxp for ; Wed, 19 Dec 2018 06:07:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726850AbeLRTHK (ORCPT ); Tue, 18 Dec 2018 14:07:10 -0500 Received: from mail-qt1-f196.google.com ([209.85.160.196]:35719 "EHLO mail-qt1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726777AbeLRTHJ (ORCPT ); Tue, 18 Dec 2018 14:07:09 -0500 Received: by mail-qt1-f196.google.com with SMTP id v11so19482138qtc.2 for ; Tue, 18 Dec 2018 11:07:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6M1Zc1Nv8Lva8EZczIRv0BHrCeXxBzM3EExJRMfERO0=; b=kYONDuUXv13hzgmUiSvytB2FNIHnvERvLTBg+sC622SapXkzqyFgal76WkvPTp6ikM ngGSAUUjBSZdpsg50JkUF5q4v2sm56q/EGj5m3y4bXbCWCHe/X9nRx4+FU2BLVzjNxiO Qh/vruxXDBQLlwgGDk1C3TP9iuu6RUo7o4lUjVS1SwWgOhOx4QafBXZW+iETyKetzjm/ vUIGJx27ffsLZQS+He8Gt8APmOh4tS9teuA0N1MrIOvzA0cAMe78ITweWyHKzJfAYikl lFDcGdhJX1a7H5mVZzBypkKvXBaaJ5vO8VhKdn1aWYSxaBCaWDiRE/BGZU6xkGLIiPCh ByEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6M1Zc1Nv8Lva8EZczIRv0BHrCeXxBzM3EExJRMfERO0=; b=B1fzDixPNMWSn/HqsAMzPvxUbG/MRKItae0LlS2vkJVVkmZ5k3dLnXslJOL4rpuLtd neQUDu/ErFIi4hA863p5p6autRSyuqFgg3xzV39QRAIbdAvNSprQZ0Dn+n5yx51sybhA 3vYZTFFY7PLafsljHjHFRbXB0yuykK+fcFw9LT9tk9cOUJzawF35Mr7YaMnBDH+H3gT5 Q7FLDoNtMn1QP4VWc9q3CKxdMNyJomliVVIjPe5iKeRP2DbhDy7tbMMlTURemWTIr8U9 Ie6yRksqo3PsIbbRDasmsCvoYhpg7RUl3rgPhl8rtwP8MqpMQM+fDEdXtABJCY73Pmou 3bOA== X-Gm-Message-State: AA+aEWYTVKZtJy2lE0SVUG092TAN9d3OaVJqKyPvBYk6NFQGs5DjOCkp Fk30mwCbWZf6QF5hrwxCw4Juuhv362Y= X-Google-Smtp-Source: AFSGD/W7rheksW0hkqjB7Fs5TY3Da6XCdv5XG0r6RitajAGycqUrs1c/i3AtSTjI7WOx4gMERzvj1A== X-Received: by 2002:ac8:839:: with SMTP id u54mr18378545qth.313.1545160026152; Tue, 18 Dec 2018 11:07:06 -0800 (PST) Received: from localhost (modemcable249.105-163-184.mc.videotron.ca. [184.163.105.249]) by smtp.gmail.com with ESMTPSA id p47sm669135qta.36.2018.12.18.11.07.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 11:07:05 -0800 (PST) From: Vivien Didelot To: netdev@vger.kernel.org Cc: Chris Healy , Vivien Didelot , "John W . Linville" , f.fainelli@gmail.com, andrew@lunn.ch Subject: [PATCH v2 5/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6352 Date: Tue, 18 Dec 2018 14:06:39 -0500 Message-Id: <20181218190641.31883-6-vivien.didelot@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181218190641.31883-1-vivien.didelot@gmail.com> References: <20181218190641.31883-1-vivien.didelot@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch adds support for pretty dump the port registers of the 88E6172, 88E6176, 88E6240 and 88E6352 switches, which all share the same datasheet. Signed-off-by: Vivien Didelot --- dsa.c | 175 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) diff --git a/dsa.c b/dsa.c index ab21d01..09a48c6 100644 --- a/dsa.c +++ b/dsa.c @@ -252,6 +252,177 @@ static void dsa_mv88e6185(int reg, u16 val) } }; +static void dsa_mv88e6352(int reg, u16 val) +{ + switch (reg) { + case 0: + REG(reg, "Port Status", val); + FIELD("Pause Enabled", "%u", !!(val & 0x8000)); + FIELD("My Pause", "%u", !!(val & 0x4000)); + FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000)); + FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down"); + FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half"); + FIELD("Speed", "%s", + (val & 0x0300) == 0x0000 ? "10 Mbps" : + (val & 0x0300) == 0x0100 ? "100 or 200 Mbps" : + (val & 0x0300) == 0x0200 ? "1000 Mbps" : + (val & 0x0300) == 0x0300 ? "Reserved" : "?"); + FIELD("EEE Enabled", "%u", !!(val & 0x0040)); + FIELD("Transmitter Paused", "%u", !!(val & 0x0020)); + FIELD("Flow Control", "%u", !!(val & 0x0010)); + FIELD("Config Mode", "0x%x", val & 0x000f); + break; + case 1: + REG(reg, "Physical Control", val); + FIELD("RGMII Receive Timing Control", "%s", val & 0x8000 ? "Delay" : "Default"); + FIELD("RGMII Transmit Timing Control", "%s", val & 0x4000 ? "Delay" : "Default"); + FIELD("200 BASE Mode", "%s", val & 0x1000 ? "200" : "100"); + FIELD("Flow Control's Forced value", "%u", !!(val & 0x0080)); + FIELD("Force Flow Control", "%u", !!(val & 0x0040)); + FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down"); + FIELD("Force Link", "%u", !!(val & 0x0010)); + FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half"); + FIELD("Force Duplex", "%u", !!(val & 0x0004)); + FIELD("Force Speed", "%s", + (val & 0x0003) == 0x0000 ? "10 Mbps" : + (val & 0x0003) == 0x0001 ? "100 or 200 Mbps" : + (val & 0x0003) == 0x0002 ? "1000 Mbps" : + (val & 0x0003) == 0x0003 ? "Not forced" : "?"); + break; + case 2: + REG(reg, "Jamming Control", val); + break; + case 3: + REG(reg, "Switch Identifier", val); + break; + case 4: + REG(reg, "Port Control", val); + FIELD("Source Address Filtering controls", "%s", + (val & 0xc000) == 0x0000 ? "Disabled" : + (val & 0xc000) == 0x4000 ? "Drop On Lock" : + (val & 0xc000) == 0x8000 ? "Drop On Unlock" : + (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?"); + FIELD("Egress Mode", "%s", + (val & 0x3000) == 0x0000 ? "Unmodified" : + (val & 0x3000) == 0x1000 ? "Untagged" : + (val & 0x3000) == 0x2000 ? "Tagged" : + (val & 0x3000) == 0x3000 ? "Reserved" : "?"); + FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800)); + FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400)); + FIELD("Frame Mode", "%s", + (val & 0x0300) == 0x0000 ? "Normal" : + (val & 0x0300) == 0x0100 ? "DSA" : + (val & 0x0300) == 0x0200 ? "Provider" : + (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?"); + FIELD("VLAN Tunnel", "%u", !!(val & 0x0080)); + FIELD("TagIfBoth", "%u", !!(val & 0x0040)); + FIELD("Initial Priority assignment", "%s", + (val & 0x0030) == 0x0000 ? "Defaults" : + (val & 0x0030) == 0x0010 ? "Tag Priority" : + (val & 0x0030) == 0x0020 ? "IP Priority" : + (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?"); + FIELD("Egress Flooding mode", "%s", + (val & 0x000c) == 0x0000 ? "No unknown DA" : + (val & 0x000c) == 0x0004 ? "No unknown multicast DA" : + (val & 0x000c) == 0x0008 ? "No unknown unicast DA" : + (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?"); + FIELD("Port State", "%s", + (val & 0x0003) == 0x0000 ? "Disabled" : + (val & 0x0003) == 0x0001 ? "Blocking/Listening" : + (val & 0x0003) == 0x0002 ? "Learning" : + (val & 0x0003) == 0x0003 ? "Forwarding" : "?"); + break; + case 5: + REG(reg, "Port Control 1", val); + FIELD("Message Port", "%u", !!(val & 0x8000)); + FIELD("Trunk Port", "%u", !!(val & 0x4000)); + FIELD("Trunk ID", "%u", (val & 0x0f00) >> 8); + FIELD("FID[11:4]", "0x%.3x", (val & 0x00ff) << 4); + break; + case 6: + REG(reg, "Port Base VLAN Map (Header)", val); + FIELD("FID[3:0]", "0x%.3x", (val & 0xf000) >> 12); + FIELD_BITMAP("VLANTable", val & 0x007f); + break; + case 7: + REG(reg, "Default VLAN ID & Priority", val); + FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13); + FIELD("Force to use Default VID", "%u", !!(val & 0x1000)); + FIELD("Default VLAN Identifier", "%u", val & 0x0fff); + break; + case 8: + REG(reg, "Port Control 2", val); + FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000)); + FIELD("Jumbo Mode", "%s", + (val & 0x3000) == 0x0000 ? "1522" : + (val & 0x3000) == 0x1000 ? "2048" : + (val & 0x3000) == 0x2000 ? "10240" : + (val & 0x3000) == 0x3000 ? "Reserved" : "?"); + FIELD("802.1QMode", "%s", + (val & 0x0c00) == 0x0000 ? "Disabled" : + (val & 0x0c00) == 0x0400 ? "Fallback" : + (val & 0x0c00) == 0x0800 ? "Check" : + (val & 0x0c00) == 0x0c00 ? "Secure" : "?"); + FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200)); + FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100)); + FIELD("Map using DA hits", "%u", !!(val & 0x0080)); + FIELD("ARP Mirror enable", "%u", !!(val & 0x0040)); + FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020)); + FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010)); + FIELD("Use Default Queue Priority", "%u", !!(val & 0x0008)); + FIELD("Default Queue Priority", "0x%x", (val & 0x0006) >> 1); + break; + case 9: + REG(reg, "Egress Rate Control", val); + break; + case 10: + REG(reg, "Egress Rate Control 2", val); + break; + case 11: + REG(reg, "Port Association Vector", val); + break; + case 12: + REG(reg, "Port ATU Control", val); + break; + case 13: + REG(reg, "Override", val); + break; + case 14: + REG(reg, "Policy Control", val); + break; + case 15: + REG(reg, "Port Ether Type", val); + break; + case 16: + REG(reg, "InDiscardsLo Frame Counter", val); + break; + case 17: + REG(reg, "InDiscardsHi Frame Counter", val); + break; + case 18: + REG(reg, "InFiltered/TcamCtr Frame Counter", val); + break; + case 19: + REG(reg, "Rx Frame Counter", val); + break; + case 22: + REG(reg, "LED Control", val); + break; + case 24: + REG(reg, "Tag Remap 0-3", val); + break; + case 25: + REG(reg, "Tag Remap 4-7", val); + break; + case 27: + REG(reg, "Queue Counters", val); + break; + default: + REG(reg, "Reserved", val); + break; + } +}; + struct dsa_mv88e6xxx_switch { void (*dump)(int reg, u16 val); const char *name; @@ -261,7 +432,11 @@ struct dsa_mv88e6xxx_switch { static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = { { .id = 0x1210, .name = "88E6123 ", .dump = dsa_mv88e6161 }, { .id = 0x1610, .name = "88E6161 ", .dump = dsa_mv88e6161 }, + { .id = 0x1720, .name = "88E6172 ", .dump = dsa_mv88e6352 }, + { .id = 0x1760, .name = "88E6176 ", .dump = dsa_mv88e6352 }, { .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 }, + { .id = 0x2400, .name = "88E6240 ", .dump = dsa_mv88e6352 }, + { .id = 0x3520, .name = "88E6352 ", .dump = dsa_mv88e6352 }, }; static int dsa_mv88e6xxx_dump_regs(struct ethtool_regs *regs) From patchwork Tue Dec 18 19:06:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivien Didelot X-Patchwork-Id: 1015574 X-Patchwork-Delegate: linville@tuxdriver.com Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="IiZl068N"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43K6w50L9kz9rxp for ; Wed, 19 Dec 2018 06:07:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726904AbeLRTHP (ORCPT ); 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[184.163.105.249]) by smtp.gmail.com with ESMTPSA id k62sm333651qte.86.2018.12.18.11.07.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 11:07:07 -0800 (PST) From: Vivien Didelot To: netdev@vger.kernel.org Cc: Chris Healy , Vivien Didelot , "John W . Linville" , f.fainelli@gmail.com, andrew@lunn.ch Subject: [PATCH v2 6/7] ethtool: dsa: mv88e6xxx: add pretty dump for 88E6390 Date: Tue, 18 Dec 2018 14:06:40 -0500 Message-Id: <20181218190641.31883-7-vivien.didelot@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181218190641.31883-1-vivien.didelot@gmail.com> References: <20181218190641.31883-1-vivien.didelot@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch adds support for pretty dump the port registers of the 88E6190, 88E6290, 88E6390, 88E6190X and 88E6390X switches, which all share the same datasheet. Signed-off-by: Vivien Didelot --- dsa.c | 182 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/dsa.c b/dsa.c index 09a48c6..9f50927 100644 --- a/dsa.c +++ b/dsa.c @@ -423,6 +423,183 @@ static void dsa_mv88e6352(int reg, u16 val) } }; +static void dsa_mv88e6390(int reg, u16 val) +{ + switch (reg) { + case 0: + REG(reg, "Port Status", val); + FIELD("Transmit Pause Enable bit", "%u", !!(val & 0x8000)); + FIELD("Receive Pause Enable bit", "%u", !!(val & 0x4000)); + FIELD("802.3 PHY Detected", "%u", !!(val & 0x1000)); + FIELD("Link Status", "%s", val & 0x0800 ? "Up" : "Down"); + FIELD("Duplex", "%s", val & 0x0400 ? "Full" : "Half"); + FIELD("Speed", "%s", + (val & 0x0300) == 0x0000 ? "10 Mbps" : + (val & 0x0300) == 0x0100 ? "100 or 200 Mbps" : + (val & 0x0300) == 0x0200 ? "1000 Mbps" : + (val & 0x0300) == 0x0300 ? "10 Gb or 2500 Mbps" : "?"); + FIELD("Duplex Fixed", "%u", !!(val & 0x0080)); + FIELD("EEE Enabled", "%u", !!(val & 0x0040)); + FIELD("Transmitter Paused", "%u", !!(val & 0x0020)); + FIELD("Flow Control", "%u", !!(val & 0x0010)); + FIELD("Config Mode", "0x%x", val & 0x000f); + break; + case 1: + REG(reg, "Physical Control", val); + FIELD("RGMII Receive Timing Control", "%s", val & 0x8000 ? "Delay" : "Default"); + FIELD("RGMII Transmit Timing Control", "%s", val & 0x4000 ? "Delay" : "Default"); + FIELD("Force Speed", "%u", !!(val & 0x2000)); + FIELD("Alternate Speed Mode", "%s", val & 0x1000 ? "Alternate" : "Normal"); + FIELD("MII PHY Mode", "%s", val & 0x0800 ? "PHY" : "MAC"); + FIELD("EEE force value", "%u", !!(val & 0x0200)); + FIELD("Force EEE", "%u", !!(val & 0x0100)); + FIELD("Link's Forced value", "%s", val & 0x0020 ? "Up" : "Down"); + FIELD("Force Link", "%u", !!(val & 0x0010)); + FIELD("Duplex's Forced value", "%s", val & 0x0008 ? "Full" : "Half"); + FIELD("Force Duplex", "%u", !!(val & 0x0004)); + FIELD("Force Speed", "%s", + (val & 0x0003) == 0x0000 ? "10 Mbps" : + (val & 0x0003) == 0x0001 ? "100 or 200 Mbps" : + (val & 0x0003) == 0x0002 ? "1000 Mbps" : + (val & 0x0003) == 0x0003 ? "10 Gb or 2500 Mbps" : "?"); + break; + case 2: + REG(reg, "Flow Control", val); + break; + case 3: + REG(reg, "Switch Identifier", val); + break; + case 4: + REG(reg, "Port Control", val); + FIELD("Source Address Filtering controls", "%s", + (val & 0xc000) == 0x0000 ? "Disabled" : + (val & 0xc000) == 0x4000 ? "Drop On Lock" : + (val & 0xc000) == 0x8000 ? "Drop On Unlock" : + (val & 0xc000) == 0xc000 ? "Drop to CPU" : "?"); + FIELD("Egress Mode", "%s", + (val & 0x3000) == 0x0000 ? "Unmodified" : + (val & 0x3000) == 0x1000 ? "Untagged" : + (val & 0x3000) == 0x2000 ? "Tagged" : + (val & 0x3000) == 0x3000 ? "Reserved" : "?"); + FIELD("Ingress & Egress Header Mode", "%u", !!(val & 0x0800)); + FIELD("IGMP and MLD Snooping", "%u", !!(val & 0x0400)); + FIELD("Frame Mode", "%s", + (val & 0x0300) == 0x0000 ? "Normal" : + (val & 0x0300) == 0x0100 ? "DSA" : + (val & 0x0300) == 0x0200 ? "Provider" : + (val & 0x0300) == 0x0300 ? "Ether Type DSA" : "?"); + FIELD("VLAN Tunnel", "%u", !!(val & 0x0080)); + FIELD("TagIfBoth", "%u", !!(val & 0x0040)); + FIELD("Initial Priority assignment", "%s", + (val & 0x0030) == 0x0000 ? "Defaults" : + (val & 0x0030) == 0x0010 ? "Tag Priority" : + (val & 0x0030) == 0x0020 ? "IP Priority" : + (val & 0x0030) == 0x0030 ? "Tag & IP Priority" : "?"); + FIELD("Egress Flooding mode", "%s", + (val & 0x000c) == 0x0000 ? "No unknown DA" : + (val & 0x000c) == 0x0004 ? "No unknown multicast DA" : + (val & 0x000c) == 0x0008 ? "No unknown unicast DA" : + (val & 0x000c) == 0x000c ? "Allow unknown DA" : "?"); + FIELD("Port State", "%s", + (val & 0x0003) == 0x0000 ? "Disabled" : + (val & 0x0003) == 0x0001 ? "Blocking/Listening" : + (val & 0x0003) == 0x0002 ? "Learning" : + (val & 0x0003) == 0x0003 ? "Forwarding" : "?"); + break; + case 5: + REG(reg, "Port Control 1", val); + FIELD("Message Port", "%u", !!(val & 0x8000)); + FIELD("LAG Port", "%u", !!(val & 0x4000)); + FIELD("VTU Page", "%u", !!(val & 0x2000)); + FIELD("LAG ID", "%u", (val & 0x0f00) >> 8); + FIELD("FID[11:4]", "0x%.3x", (val & 0x00ff) << 4); + break; + case 6: + REG(reg, "Port Base VLAN Map (Header)", val); + FIELD("FID[3:0]", "0x%.3x", (val & 0xf000) >> 12); + FIELD("Force Mapping", "%u", !!(val & 0x0800)); + FIELD_BITMAP("VLANTable", val & 0x007ff); + break; + case 7: + REG(reg, "Default VLAN ID & Priority", val); + FIELD("Default Priority", "0x%x", (val & 0xe000) >> 13); + FIELD("Force to use Default VID", "%u", !!(val & 0x1000)); + FIELD("Default VLAN Identifier", "%u", val & 0x0fff); + break; + case 8: + REG(reg, "Port Control 2", val); + FIELD("Force good FCS in the frame", "%u", !!(val & 0x8000)); + FIELD("Allow bad FCS", "%u", !!(val & 0x4000)); + FIELD("Jumbo Mode", "%s", + (val & 0x3000) == 0x0000 ? "1522" : + (val & 0x3000) == 0x1000 ? "2048" : + (val & 0x3000) == 0x2000 ? "10240" : + (val & 0x3000) == 0x3000 ? "Reserved" : "?"); + FIELD("802.1QMode", "%s", + (val & 0x0c00) == 0x0000 ? "Disabled" : + (val & 0x0c00) == 0x0400 ? "Fallback" : + (val & 0x0c00) == 0x0800 ? "Check" : + (val & 0x0c00) == 0x0c00 ? "Secure" : "?"); + FIELD("Discard Tagged Frames", "%u", !!(val & 0x0200)); + FIELD("Discard Untagged Frames", "%u", !!(val & 0x0100)); + FIELD("Map using DA hits", "%u", !!(val & 0x0080)); + FIELD("ARP Mirror enable", "%u", !!(val & 0x0040)); + FIELD("Egress Monitor Source Port", "%u", !!(val & 0x0020)); + FIELD("Ingress Monitor Source Port", "%u", !!(val & 0x0010)); + FIELD("Allow VID of Zero", "%u", !!(val & 0x0008)); + FIELD("Default Queue Priority", "0x%x", val & 0x0007); + break; + case 9: + REG(reg, "Egress Rate Control", val); + break; + case 10: + REG(reg, "Egress Rate Control 2", val); + break; + case 11: + REG(reg, "Port Association Vector", val); + break; + case 12: + REG(reg, "Port ATU Control", val); + break; + case 13: + REG(reg, "Override", val); + break; + case 14: + REG(reg, "Policy Control", val); + break; + case 15: + REG(reg, "Port Ether Type", val); + break; + case 22: + REG(reg, "LED Control", val); + break; + case 23: + REG(reg, "IP Priority Mapping Table", val); + break; + case 24: + REG(reg, "IEEE Priority Mapping Table", val); + break; + case 25: + REG(reg, "Port Control 3", val); + break; + case 27: + REG(reg, "Queue Counters", val); + break; + case 28: + REG(reg, "Queue Control", val); + break; + case 30: + REG(reg, "Cut Through Control", val); + break; + case 31: + REG(reg, "Debug Counters", val); + break; + default: + REG(reg, "Reserved", val); + break; + } +}; + struct dsa_mv88e6xxx_switch { void (*dump)(int reg, u16 val); const char *name; @@ -430,13 +607,18 @@ struct dsa_mv88e6xxx_switch { }; static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = { + { .id = 0x0a00, .name = "88E6190X", .dump = dsa_mv88e6390 }, + { .id = 0x0a10, .name = "88E6390X", .dump = dsa_mv88e6390 }, { .id = 0x1210, .name = "88E6123 ", .dump = dsa_mv88e6161 }, { .id = 0x1610, .name = "88E6161 ", .dump = dsa_mv88e6161 }, { .id = 0x1720, .name = "88E6172 ", .dump = dsa_mv88e6352 }, { .id = 0x1760, .name = "88E6176 ", .dump = dsa_mv88e6352 }, + { .id = 0x1900, .name = "88E6190 ", .dump = dsa_mv88e6390 }, { .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 }, { .id = 0x2400, .name = "88E6240 ", .dump = dsa_mv88e6352 }, + { .id = 0x2900, .name = "88E6290 ", .dump = dsa_mv88e6390 }, { .id = 0x3520, .name = "88E6352 ", .dump = dsa_mv88e6352 }, + { .id = 0x3900, .name = "88E6390 ", .dump = dsa_mv88e6390 }, }; static int dsa_mv88e6xxx_dump_regs(struct ethtool_regs *regs) From patchwork Tue Dec 18 19:06:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivien Didelot X-Patchwork-Id: 1015573 X-Patchwork-Delegate: linville@tuxdriver.com Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JWFNqqyI"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43K6w21ZMMz9rxp for ; Wed, 19 Dec 2018 06:07:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726887AbeLRTHN (ORCPT ); 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[184.163.105.249]) by smtp.gmail.com with ESMTPSA id l12sm351715qkk.40.2018.12.18.11.07.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Dec 2018 11:07:08 -0800 (PST) From: Vivien Didelot To: netdev@vger.kernel.org Cc: Chris Healy , Vivien Didelot , "John W . Linville" , f.fainelli@gmail.com, andrew@lunn.ch Subject: [PATCH v2 7/7] ethtool: dsa: mv88e6xxx: add pretty dump for others Date: Tue, 18 Dec 2018 14:06:41 -0500 Message-Id: <20181218190641.31883-8-vivien.didelot@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181218190641.31883-1-vivien.didelot@gmail.com> References: <20181218190641.31883-1-vivien.didelot@gmail.com> MIME-Version: 1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch adds basic pretty dump for the remaining mv88e6xxx switches supported by the kernel DSA driver. Signed-off-by: Vivien Didelot --- dsa.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/dsa.c b/dsa.c index 9f50927..02a10dd 100644 --- a/dsa.c +++ b/dsa.c @@ -607,17 +607,31 @@ struct dsa_mv88e6xxx_switch { }; static const struct dsa_mv88e6xxx_switch dsa_mv88e6xxx_switches[] = { + { .id = 0x04a0, .name = "88E6085 ", .dump = NULL }, + { .id = 0x0950, .name = "88E6095 ", .dump = NULL }, + { .id = 0x0990, .name = "88E6097 ", .dump = NULL }, { .id = 0x0a00, .name = "88E6190X", .dump = dsa_mv88e6390 }, { .id = 0x0a10, .name = "88E6390X", .dump = dsa_mv88e6390 }, + { .id = 0x1060, .name = "88E6131 ", .dump = NULL }, + { .id = 0x1150, .name = "88E6320 ", .dump = NULL }, { .id = 0x1210, .name = "88E6123 ", .dump = dsa_mv88e6161 }, { .id = 0x1610, .name = "88E6161 ", .dump = dsa_mv88e6161 }, + { .id = 0x1650, .name = "88E6165 ", .dump = NULL }, + { .id = 0x1710, .name = "88E6171 ", .dump = NULL }, { .id = 0x1720, .name = "88E6172 ", .dump = dsa_mv88e6352 }, + { .id = 0x1750, .name = "88E6175 ", .dump = NULL }, { .id = 0x1760, .name = "88E6176 ", .dump = dsa_mv88e6352 }, { .id = 0x1900, .name = "88E6190 ", .dump = dsa_mv88e6390 }, + { .id = 0x1910, .name = "88E6191 ", .dump = NULL }, { .id = 0x1a70, .name = "88E6185 ", .dump = dsa_mv88e6185 }, { .id = 0x2400, .name = "88E6240 ", .dump = dsa_mv88e6352 }, { .id = 0x2900, .name = "88E6290 ", .dump = dsa_mv88e6390 }, + { .id = 0x3100, .name = "88E6321 ", .dump = NULL }, + { .id = 0x3400, .name = "88E6141 ", .dump = NULL }, + { .id = 0x3410, .name = "88E6341 ", .dump = NULL }, { .id = 0x3520, .name = "88E6352 ", .dump = dsa_mv88e6352 }, + { .id = 0x3710, .name = "88E6350 ", .dump = NULL }, + { .id = 0x3750, .name = "88E6351 ", .dump = NULL }, { .id = 0x3900, .name = "88E6390 ", .dump = dsa_mv88e6390 }, };