From patchwork Thu Dec 13 09:34:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1012697 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Rph6AINk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43FpRz4Kc2z9s1c for ; Thu, 13 Dec 2018 20:34:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727481AbeLMJey (ORCPT ); Thu, 13 Dec 2018 04:34:54 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8111 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727063AbeLMJey (ORCPT ); Thu, 13 Dec 2018 04:34:54 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 01:34:47 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:34:52 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 13 Dec 2018 01:34:52 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:34:51 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:34:51 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 13 Dec 2018 01:34:51 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , , Joseph Lo Subject: [PATCH V2 01/21] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Date: Thu, 13 Dec 2018 17:34:18 +0800 Message-ID: <20181213093438.29621-2-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com> References: <20181213093438.29621-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693687; bh=rFGSZ0H3Wp9DaEGcVopw2NZQbBN0zr5+WWCzFUB5efw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=Rph6AINkioD+OWK5CQFJLeKcThEead0L71EmGOoFmmHjTAshbqIQerRYj/puoSIjA I1vGXvg5DBScTceJA+sqjqJbCAKqTK3pSpRjy/6p2FuP+HGomGpPGX0zwW+m3yj/wa ht9ZZuxmmqknGYKqAGN+xbasenuvKpNc95VbpoIc7mvWzu88yGImIrx5N3UOMlOkNx Ny6Ty24qPxb9+l6Au0p8ussgw5B2ptkYJCRmVIEUyWB27TvOe4xfSbJhv8XTTS0lUV W9paDq1QoarLVuxFoibbjMkOn4GK1VAFeWQVwX3n7zZVmp0FI76UyOFaEOqWp87Lm8 gbm6Ieqejm7OQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Peter De Schrijver Add new properties to configure the DFLL PWM regulator support. Cc: devicetree@vger.kernel.org Signed-off-by: Peter De Schrijver Signed-off-by: Joseph Lo --- *V2: - update the binding strings and descriptions for nvidia,pwm-tristate-microvolts nvidia,pwm-min-microvolts nvidia,pwm-voltage-step-microvolts --- .../bindings/clock/nvidia,tegra124-dfll.txt | 79 ++++++++++++++++++- 1 file changed, 77 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index dff236f524a7..38e8cc8c70a8 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -8,7 +8,6 @@ the fast CPU cluster. It consists of a free-running voltage controlled oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop control module that will automatically adjust the VDD_CPU voltage by communicating with an off-chip PMIC either via an I2C bus or via PWM signals. -Currently only the I2C mode is supported by these bindings. Required properties: - compatible : should be "nvidia,tegra124-dfll" @@ -45,10 +44,31 @@ Required properties for the control loop parameters: Optional properties for the control loop parameters: - nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM. +Optional properties for mode selection: +- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C. + Required properties for I2C mode: - nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode. -Example: +Required properties for PWM mode: +- nvidia,pwm-period: period of PWM square wave in microseconds. +- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM + control is disabled and the PWM output is tristated. Note that this voltage is + configured in hardware, typically via a resistor divider. +- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control + is enabled and PWM output is low. Hence, this is the minimum output voltage + that the regulator supports when PWM control is enabled. +- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts + corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th + duty cycle would be: nvidia,pwm-min-microvolts + + nvidia,pwm-voltage-step-microvolts * 2. +- pinctrl-0: I/O pad configuration when PWM control is enabled. +- pinctrl-1: I/O pad configuration when PWM control is disabled. +- pinctrl-names: must include the following entries: + - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled. + - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled. + +Example for I2C: clock@70110000 { compatible = "nvidia,tegra124-dfll"; @@ -76,3 +96,58 @@ clock@70110000 { nvidia,i2c-fs-rate = <400000>; }; + +Example for PWM: + +clock@70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, + <&tegra_car TEGRA210_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>;; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + + nvidia,sample-rate = <25000>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + + nvidia,pwm-min-microvolts = <708000>; /* 708mV */ + nvidia,pwm-period = <2500>; /* 2.5us */ + nvidia,pwm-to-pmic; + nvidia,pwm-tristate-microvolts = <1000000>; + nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */ + + pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; + pinctrl-0 = <&dvfs_pwm_active_state>; + pinctrl-1 = <&dvfs_pwm_inactive_state>; +}; + +/* pinmux nodes added for completeness. Binding doc can be found in: + * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt + */ + +pinmux: pinmux@700008d4 { + dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; + dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_pbb1 { + nvidia,pins = "dvfs_pwm_pbb1"; + nvidia,tristate = ; + }; + }; +}; From patchwork Thu Dec 13 09:34:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1012699 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="bsthADgs"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43FpS11Wdjz9s7T for ; Thu, 13 Dec 2018 20:34:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727556AbeLMJez (ORCPT ); Thu, 13 Dec 2018 04:34:55 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18372 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727063AbeLMJez (ORCPT ); Thu, 13 Dec 2018 04:34:55 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 01:34:52 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:34:54 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 13 Dec 2018 01:34:54 -0800 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:34:54 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:34:54 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:34:54 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 13 Dec 2018 01:34:54 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Subject: [PATCH V2 02/21] dt-bindings: clock: tegra124-dfll: add Tegra210 support Date: Thu, 13 Dec 2018 17:34:19 +0800 Message-ID: <20181213093438.29621-3-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com> References: <20181213093438.29621-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693692; bh=HPd9k/RqD/oYinbslvgkUCjjWklYotdyJZJNQ7VTT4c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=bsthADgsMbo9e+V3tsmT15wavl3lDkio7h6wDDazbCMkC06ssaRrle585jkUsJ74H 2Wyb0/qVgsNxOvLb8FU7KGBF6uK8GE9rBov/6Bi0p5kYqnKkpN5DwQ2aGoEZPJJlOh Lvs3rzNLdz4Z7saErGL5srNLqXcR6Sam3Q90CrocMBkhLUkqS52mU42MJczrmGulf8 jEombjKlmLrAAr2JZPRTSYhxu3SB6wwuc5NqwR/nz+Ozuf5UXlNdnEcFEtxYNW3pVm cBLLr8O6nf6GlBKdeCoTQxqLNq1SkWgjByAZJwl4oOXTk/2aK5wosvKsqU+JatnSP9 5iWQ9TVyilRtw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Tegra210 support for DFLL clock. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- *V2: - add ack tag --- .../devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index 38e8cc8c70a8..8a38c8e78acf 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -10,7 +10,9 @@ control module that will automatically adjust the VDD_CPU voltage by communicating with an off-chip PMIC either via an I2C bus or via PWM signals. Required properties: -- compatible : should be "nvidia,tegra124-dfll" +- compatible : should be one of: + - "nvidia,tegra124-dfll": for Tegra124 + - "nvidia,tegra210-dfll": for Tegra210 - reg : Defines the following set of registers, in the order listed: - registers for the DFLL control logic. - registers for the I2C output logic. From patchwork Thu Dec 13 09:34:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1012701 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="MQFGEqGh"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43FpS30C9Yz9s6w for ; Thu, 13 Dec 2018 20:34:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727629AbeLMJe6 (ORCPT ); Thu, 13 Dec 2018 04:34:58 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1326 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727063AbeLMJe5 (ORCPT ); Thu, 13 Dec 2018 04:34:57 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 01:34:53 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:34:57 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 13 Dec 2018 01:34:57 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:34:56 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:34:56 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 13 Dec 2018 01:34:56 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Subject: [PATCH V2 03/21] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Date: Thu, 13 Dec 2018 17:34:20 +0800 Message-ID: <20181213093438.29621-4-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com> References: <20181213093438.29621-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693693; bh=q0UMDemwz5MCXWMdMFgDi5JSy2ea57JJxHGTiEJ/RfE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=MQFGEqGhEVeAXndVNGRcj0VKidCRV7QkRlHCGKB4giT/+tbflnHuTJSFmXf2XmO8J 6XGO/0xCU6CldBP12AB+dWm0zbjoH394T8D1KlypIuRbQMlHbUqdoLcLwPf2l7mQdS jBa8nlNgNHTcWc5DKO7KM3d5ZiBAUY76ArRgC3OtU+g9S4vnzRlhs+omyL9dRHXrUo MFVR3wTGkzHlC+VEN5J0WyzhjlfVnFKr3A8FS4LoUlYrk4Jt1fKH/SKepTHtVd4ew0 kTEbWl9OAJo3ml+41CzfFYFlmGHH73G9fjboWOwIS12IFkPmZvmYAf5lmvUM5l+vsl lDkPVXvtvguCw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Tegra124 cpufreq driver works only with DFLL clock, which is a hardware-based frequency/voltage controller. The driver doesn't need to control the regulator itself. Hence remove that. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- *V2: - add ack tag --- .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt index b1669fbfb740..031545a29caf 100644 --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt @@ -13,7 +13,6 @@ Required properties: - pll_x: Fast PLL clocksource. - pll_p: Auxiliary PLL used during fast PLL rate changes. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. -- vdd-cpu-supply: Regulator for CPU voltage Optional properties: - clock-latency: Specify the possible maximum transition latency for clock, @@ -37,7 +36,6 @@ cpus { <&dfll>; clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; - vdd-cpu-supply: <&vdd_cpu>; }; <...> From patchwork Thu Dec 13 09:34:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1012703 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Qs789xBR"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43FpS565b7z9s6w for ; Thu, 13 Dec 2018 20:35:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727718AbeLMJfA (ORCPT ); Thu, 13 Dec 2018 04:35:00 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18375 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727063AbeLMJfA (ORCPT ); Thu, 13 Dec 2018 04:35:00 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 01:34:56 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:34:59 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 13 Dec 2018 01:34:59 -0800 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:34:59 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:34:59 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:34:59 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 13 Dec 2018 01:34:58 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo , Subject: [PATCH V2 04/21] dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties Date: Thu, 13 Dec 2018 17:34:21 +0800 Message-ID: <20181213093438.29621-5-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181213093438.29621-1-josephl@nvidia.com> References: <20181213093438.29621-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693696; bh=VCHfLBMx8Da+rXf9UJ2gOo/OyDqKfHHAnbMGMXXz5zg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=Qs789xBR42uTWacv9XeSy2dHEAuoDiWvf6INDPUlzU4Lx8IfStATIZsHqorqRu/Wh Ulj/N7T1wCLLVrpLjeoU2dkNnBz+4PJIRjYu6rY2JZ6TDBNNuHoK3/mM/EXSrYNmLP geerU+PoSgC8EcjRuIXdN77qAmU9H0sI1GaZxeFw8RXNx+3d7c5QroZUfyQ4JltrrL 2AVIjjAunxJjLuqQUkZR5Adfkaj7YyzjZpe9CY71UmXpkdgXG47ghcQLGcuYWDFpNN u3BN4ByFpyJaqTW5NxAHpUSeE7i1EOTZwEnRL70a7N4FMehGauuj/6rbD+W4sNwpDd xc5EI5A1xlgAQ== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The cpu_lp clock property is only needed when the CPUfreq driver supports CPU cluster switching. But it was not a design for this driver and it didn't handle that as well. So removing this property. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter --- *V2: - add ack tag --- .../devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt index 031545a29caf..03196d5ea515 100644 --- a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra124-cpufreq.txt @@ -9,7 +9,6 @@ Required properties: See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: - cpu_g: Clock mux for the fast CPU cluster. - - cpu_lp: Clock mux for the low-power CPU cluster. - pll_x: Fast PLL clocksource. - pll_p: Auxiliary PLL used during fast PLL rate changes. - dfll: Fast DFLL clocksource that also automatically scales CPU voltage. @@ -30,11 +29,10 @@ cpus { reg = <0>; clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, - <&tegra_car TEGRA124_CLK_CCLK_LP>, <&tegra_car TEGRA124_CLK_PLL_X>, <&tegra_car TEGRA124_CLK_PLL_P>, <&dfll>; - clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; clock-latency = <300000>; };