From patchwork Wed Dec 12 12:04:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGFsIFZva8OhxI0=?= X-Patchwork-Id: 1011899 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=ysoft.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ysoft.com header.i=@ysoft.com header.b="aPGVlJTP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43FFqq1Kbyz9s5c for ; Wed, 12 Dec 2018 23:05:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727421AbeLLME6 (ORCPT ); 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Wed, 12 Dec 2018 12:04:50 +0000 From: =?utf-8?b?Vm9rw6HEjSBNaWNoYWw=?= To: Thierry Reding , Rob Herring CC: Mark Rutland , "devicetree@vger.kernel.org" , "linux-pwm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Lukasz Majewski , Fabio Estevam , =?utf-8?q?Lothar_Wa=C3=9Fmann?= , Linus Walleij , =?utf-8?q?Uwe_Kleine-K=C3=B6?= =?utf-8?q?nig?= , =?utf-8?b?Vm9rw6HEjSBNaWNo?= =?utf-8?q?al?= Subject: [RFC PATCH v4 1/2] dt-bindings: pwm: imx: Allow switching PWM output between PWM and GPIO Thread-Topic: [RFC PATCH v4 1/2] dt-bindings: pwm: imx: Allow switching PWM output between PWM and GPIO Thread-Index: AQHUkhLi3MZ2+5IH1USqgPsrvECLRw== Date: Wed, 12 Dec 2018 12:04:50 +0000 Message-ID: <1544616263-82642-2-git-send-email-michal.vokac@ysoft.com> References: <1544616263-82642-1-git-send-email-michal.vokac@ysoft.com> In-Reply-To: <1544616263-82642-1-git-send-email-michal.vokac@ysoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0022.eurprd07.prod.outlook.com (2603:10a6:203:51::32) To DB7PR04MB4667.eurprd04.prod.outlook.com (2603:10a6:5:37::13) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Michal.Vokac@ysoft.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB7PR04MB4121; H:DB7PR04MB4667.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: ysoft.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: FOgYmwtErX31oHVxLFaIuV76YGTRDJHwUelrhwUOI80PdyUALnqw9eUDpwmW9456Bx0QfxlS2iYewX6YCZ6t8qVFLX0XcS2J9Q79un4sCs7FofKsMb6nSIOrSClX1Jm67n84UDmyLpSdve673NoFHLa2q+4Y3XFUuTPH8jXiaHVnkfhhgH4Q+hwKd1lKeMu6eAbwzMhKPLbwQe7xl5cPRfZevrckQNARsAeux3Y5yQqSBBeFbZCSn4Rp/uLnrV+RaaSRLVPqenvK0ltP/zC5RT7qu6vtOp2W+FQ5AMjSqBPpRzo+0gvDOHJ7AczZhlHw spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: MIME-Version: 1.0 X-OriginatorOrg: ysoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0c7f3202-4d3b-4875-577f-08d6602a0493 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Dec 2018 12:04:50.3893 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b5839965-430f-4be2-b282-d7a3149f2b37 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4121 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Output of the PWM block on i.MX SoCs is always low when the block is disabled. This can cause issues when inverted PWM polarity is needed. With inverted polarity a duty cycle = 0% corresponds to high level on the output. Now, when PWM is disabled its output instantly goes low which corresponds to duty cycle = 100%. To get a truly inverted PWM output two pinctrl states of the PWM pin can be used. Configure the pin to GPIO function when PWM is disabled and switch back to PWM function whenever non-zero duty cycle is needed. Reviewed-by: Rob Herring Signed-off-by: Michal Vokáč --- Changes in v4: - Add R-by from Rob. Changes in v3: - Slightly different description of the pinctrl and pwm-gpio. Changes in v2: - Do not use the "default" pinctrl state for GPIO. - Use two new "pwm" and "gpio" pinctrl states. - Add a new pwm-gpios signal. Documentation/devicetree/bindings/pwm/imx-pwm.txt | 49 +++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt index c61bdf8..2a555b6 100644 --- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt @@ -14,6 +14,16 @@ See the clock consumer binding, Documentation/devicetree/bindings/clock/clock-bindings.txt - interrupts: The interrupt for the pwm controller +Optional properties: +- pinctrl: For i.MX27 and newer SoCs. Use "pwm" and "gpio" specific pinctrls + instead of the "default" to configure the PWM pin to GPIO and PWM function. + It allows control over the pin output level when the PWM block is disabled. + This is useful if you use the PWM for single purpose and you need inverted + polarity of the PWM signal. See "Inverted PWM output" section bellow. +- pwm-gpios: Specify the GPIO pin that will act as the PWM output. This should + be the same pin as is used for normal PWM output. See "Inverted PWM output" + section bellow. + Example: pwm1: pwm@53fb4000 { @@ -25,3 +35,42 @@ pwm1: pwm@53fb4000 { clock-names = "ipg", "per"; interrupts = <61>; }; + +Inverted PWM output +------------------- + +The i.MX SoC has such limitation that whenever a pin is configured as a PWM +output, the output level on the pin is always low when the PWM block is +disabled. The low output level is actively driven by the output stage of the +PWM block and it does not matter what polarity a PWM client (e.g. backlight) +requested. + +To gain control of the output level in PWM disabled state two pinctrl states +can be used. A "pwm" state and a "gpio" state. In the pwm state the pin is +configured as a normal PWM output. In the gpio state the pin is configured as +a GPIO input. In the gpio state the output level is controlled by the pull-up +setting. This setup assures that the PWM output is at the required level that +corresponds to duty cycle = 0 when PWM is disabled. + +Example: + +&pwm1 { + pinctrl-names = "pwm", "gpio"; + pinctrl-0 = <&pinctrl_backlight_pwm>; + pinctrl-1 = <&pinctrl_backlight_gpio>; + pwm-gpios = <&gpio1 9 GPIO_ACTIVE_LOW> +} + +pinctrl_backlight_gpio: pwm1grp-gpio { + fsl,pins = < + /* GPIO with 100kOhm pull-up */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb000 + >; +}; + +pinctrl_backlight_pwm: pwm1grp-pwm { + fsl,pins = < + /* PWM output */ + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; +}; From patchwork Wed Dec 12 12:04:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGFsIFZva8OhxI0=?= X-Patchwork-Id: 1011897 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=ysoft.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ysoft.com header.i=@ysoft.com header.b="GC1w9bCy"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43FFqm2kJwz9s5c for ; Wed, 12 Dec 2018 23:05:08 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727437AbeLLMFC (ORCPT ); Wed, 12 Dec 2018 07:05:02 -0500 Received: from mail-eopbgr10042.outbound.protection.outlook.com ([40.107.1.42]:2323 "EHLO EUR02-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727326AbeLLMFB (ORCPT ); Wed, 12 Dec 2018 07:05:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ysoft.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=b+I31AhgTuWyV+rK6j7iY7ASSG6AQb57N/al32nl934=; b=GC1w9bCyH8iUgeyJ5l+z2/UCfs8dhT7skaK8qL1VUTlKTpQqFe/F8/BJbHxt74i/3B1Pk5xE7ljaljOn7AbItYtKtF68jjrL8g6SwA5FSKt4sAMzQUGVYu1Bd6163vmDyg/NpsGkCo2KyDWUnah+pgUuW8pFenkZ8yavKALMomI= Received: from DB7PR04MB4667.eurprd04.prod.outlook.com (52.135.139.13) by DB7PR04MB4121.eurprd04.prod.outlook.com (52.135.130.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1425.18; Wed, 12 Dec 2018 12:04:51 +0000 Received: from DB7PR04MB4667.eurprd04.prod.outlook.com ([fe80::2561:ec02:4e5e:f490]) by DB7PR04MB4667.eurprd04.prod.outlook.com ([fe80::2561:ec02:4e5e:f490%3]) with mapi id 15.20.1425.016; Wed, 12 Dec 2018 12:04:51 +0000 From: =?utf-8?b?Vm9rw6HEjSBNaWNoYWw=?= To: Thierry Reding , Rob Herring CC: Mark Rutland , "devicetree@vger.kernel.org" , "linux-pwm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Lukasz Majewski , Fabio Estevam , =?utf-8?q?Lothar_Wa=C3=9Fmann?= , Linus Walleij , =?utf-8?q?Uwe_Kleine-K=C3=B6?= =?utf-8?q?nig?= , =?utf-8?b?Vm9rw6HEjSBNaWNo?= =?utf-8?q?al?= Subject: [RFC PATCH v4 2/2] pwm: imx: Configure output to GPIO in disabled state Thread-Topic: [RFC PATCH v4 2/2] pwm: imx: Configure output to GPIO in disabled state Thread-Index: AQHUkhLirFnKXujZwEq6KFuGhzIyhg== Date: Wed, 12 Dec 2018 12:04:51 +0000 Message-ID: <1544616263-82642-3-git-send-email-michal.vokac@ysoft.com> References: <1544616263-82642-1-git-send-email-michal.vokac@ysoft.com> In-Reply-To: <1544616263-82642-1-git-send-email-michal.vokac@ysoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0022.eurprd07.prod.outlook.com (2603:10a6:203:51::32) To DB7PR04MB4667.eurprd04.prod.outlook.com (2603:10a6:5:37::13) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Michal.Vokac@ysoft.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB7PR04MB4121; H:DB7PR04MB4667.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: ysoft.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: d9hhcOGuirLG4NRtuJXD2qBkz5DtSu1awqd54Gej9Zoo0XNPJ+IbOS4j7j37KtdqXr1HY4+li2w5pgnr4GnJ2OshA1Jf38XxSYJu4g5OS9CE6rP9cSi3LGlPc5YW8PntfZ3Y6ns7BjX7VvoymlCBv0JYmLEo5gzKeAPx8ExUJmcsONkNeUip7+VHaVwrCa9zlwHgoqpcecxVwcjixGT4FZS5AbiSw4YI6AWrXsa13nL00lRoJ9GfJMGoFiQT/W/99efHDJ0wY07U0adR82bGAuf7Qivs+4pWaT9ZKo306xn9lJYCtowDjQpDsIH54mN9 spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: <9F579DD93FFB0646BEA8CB848C771C29@eurprd04.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: ysoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: bd9dc6fa-592e-4e08-2a3b-08d6602a0525 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Dec 2018 12:04:51.3420 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b5839965-430f-4be2-b282-d7a3149f2b37 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4121 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Normally the PWM output is held LOW when PWM is disabled. This can cause problems when inverted PWM signal polarity is needed. With this behavior the connected circuit is fed by 100% duty cycle instead of being shut-off. Allow users to define a "pwm" and a "gpio" pinctrl states. The pwm pinctrl state is selected when PWM is enabled and the gpio pinctrl state is selected when PWM is disabled. In the gpio state the new pwm-gpios GPIO is configured as input and the internal pull-up resistor is used to pull the output level high. If all the pinctrl states and the pwm-gpios GPIO are not correctly specified in DT the PWM work as usual. As an example, with this patch a PWM controlled backlight with inversed signal polarity can be used in full brightness range. Without this patch the backlight can not be turned off as brightness = 0 disables the PWM and that in turn set PWM output LOW, that is full brightness. Inverted output of the PWM with "default" and with "pwm"+"gpio" pinctrl: +--------------+------------+---------------+----------- +-------------+ | After reset | Bootloader | PWM probe | PWM | PWM | | 100k pull-up | | | enable 30% | disable | +--------------+------------+---------------+------------+-------------+ | pinctrl | none | default | default | default | | out H __________________ __ __ | | out L \_________________/ \_/ \_/\____________ | | ^ ^ ^ | +--------------+------------+---------------+------------+-------------+ | pinctrl | none | gpio | pwm | gpio | | out H __________________________________ __ __ _____________ | | out L \_/ \_/ \_/ | | ^ ^ ^ | +----------------------------------------------------------------------+ Signed-off-by: Michal Vokáč --- Changes in v4: - Get the pinctrl first, if OK only then get the GPIO. (Uwe) - Use the non-optional variant of devm_gpiod_get(). - Align function arguments to the opening parentheses. (Uwe) Changes in v3: - Commit message update. - Minor fix in code comment (Uwe) - Align function arguments to the opening parentheses. (Uwe) - Do not test devm_pinctrl_get for NULL. (Thierry) - Convert all messages to dev_dbg() (Thierry) - Do not actively drive the pin in gpio state. Configure it as input and rely solely on the internal pull-up. (Thierry) Changes in v2: - Utilize the "pwm" and "gpio" pinctrl states. - Use the pwm-gpios signal to drive the output in "gpio" pinctrl state. - Select the right pinctrl state in probe. drivers/pwm/pwm-imx.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 1d5242c..b8782fe 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -12,10 +12,12 @@ #include #include #include +#include #include #include #include #include +#include /* i.MX1 and i.MX21 share the same PWM function block: */ @@ -52,10 +54,52 @@ struct imx_chip { void __iomem *mmio_base; struct pwm_chip chip; + + struct pinctrl *pinctrl; + struct pinctrl_state *pinctrl_pins_gpio; + struct pinctrl_state *pinctrl_pins_pwm; + struct gpio_desc *pwm_gpiod; }; #define to_imx_chip(chip) container_of(chip, struct imx_chip, chip) +static int imx_pwm_init_pinctrl_info(struct imx_chip *imx_chip, + struct platform_device *pdev) +{ + imx_chip->pinctrl = devm_pinctrl_get(&pdev->dev); + if (IS_ERR(imx_chip->pinctrl)) { + dev_dbg(&pdev->dev, "can not get pinctrl\n"); + return PTR_ERR(imx_chip->pinctrl); + } + + imx_chip->pinctrl_pins_pwm = pinctrl_lookup_state(imx_chip->pinctrl, + "pwm"); + imx_chip->pinctrl_pins_gpio = pinctrl_lookup_state(imx_chip->pinctrl, + "gpio"); + + if (IS_ERR(imx_chip->pinctrl_pins_pwm) || + IS_ERR(imx_chip->pinctrl_pins_gpio)) { + dev_dbg(&pdev->dev, "pinctrl information incomplete\n"); + goto out; + } + + imx_chip->pwm_gpiod = devm_gpiod_get(&pdev->dev, "pwm", GPIOD_IN); + if (PTR_ERR(imx_chip->pwm_gpiod) == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (IS_ERR(imx_chip->pwm_gpiod)) { + dev_dbg(&pdev->dev, "GPIO information incomplete\n"); + goto out; + } + + return 0; + +out: + devm_pinctrl_put(imx_chip->pinctrl); + imx_chip->pinctrl = NULL; + + return 0; +} + static int imx_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { @@ -216,7 +260,25 @@ static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm, cr |= MX3_PWMCR_POUTC; writel(cr, imx->mmio_base + MX3_PWMCR); + + /* + * If we are in charge of pinctrl then switch output to + * the PWM signal. + */ + if (imx->pinctrl) + pinctrl_select_state(imx->pinctrl, + imx->pinctrl_pins_pwm); } else if (cstate.enabled) { + /* + * PWM block will be disabled. Normally its output will be set + * low no matter what output polarity is configured. Let's use + * pinctrl to switch the output pin to GPIO functon and keep + * the output at the same level as for duty-cycle = 0. + */ + if (imx->pinctrl) + pinctrl_select_state(imx->pinctrl, + imx->pinctrl_pins_gpio); + writel(0, imx->mmio_base + MX3_PWMCR); clk_disable_unprepare(imx->clk_per); @@ -263,6 +325,7 @@ static int imx_pwm_probe(struct platform_device *pdev) const struct of_device_id *of_id = of_match_device(imx_pwm_dt_ids, &pdev->dev); const struct imx_pwm_data *data; + struct pwm_state cstate; struct imx_chip *imx; struct resource *r; int ret = 0; @@ -294,6 +357,10 @@ static int imx_pwm_probe(struct platform_device *pdev) imx->chip.of_pwm_n_cells = 3; } + ret = imx_pwm_init_pinctrl_info(imx, pdev); + if (ret) + return ret; + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); imx->mmio_base = devm_ioremap_resource(&pdev->dev, r); if (IS_ERR(imx->mmio_base)) @@ -303,6 +370,24 @@ static int imx_pwm_probe(struct platform_device *pdev) if (ret < 0) return ret; + if (imx->pinctrl) { + /* + * Update cstate after pwmchip_add() call as the core might + * call the get_state() function to read the PWM registers + * to get the actual HW state. + */ + pwm_get_state(imx->chip.pwms, &cstate); + if (cstate.enabled) { + dev_dbg(&pdev->dev, + "PWM entered probe in enabled state\n"); + pinctrl_select_state(imx->pinctrl, + imx->pinctrl_pins_pwm); + } else { + pinctrl_select_state(imx->pinctrl, + imx->pinctrl_pins_gpio); + } + } + platform_set_drvdata(pdev, imx); return 0; }