From patchwork Tue Dec 11 09:34:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010916 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tlTjG5kq"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZSH30NPz9s0t for ; Tue, 11 Dec 2018 20:30:55 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0563AC2269C; Tue, 11 Dec 2018 09:30:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0F1EDC2244E; Tue, 11 Dec 2018 09:30:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0E930C22133; Tue, 11 Dec 2018 09:30:08 +0000 (UTC) Received: from mail-pf1-f193.google.com (mail-pf1-f193.google.com [209.85.210.193]) by lists.denx.de (Postfix) with ESMTPS id 644CEC22126 for ; Tue, 11 Dec 2018 09:30:07 +0000 (UTC) Received: by mail-pf1-f193.google.com with SMTP id i12so6840964pfo.7 for ; Tue, 11 Dec 2018 01:30:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=jtz8TJJPP02uY2H+u7P9RmyTGqPKE3q5STjCj4ikXWM=; b=tlTjG5kqkMB2yPzdBiLigHaJ6NcUKn8/j3gVZW+IEOruy2HZIBLrxFrd0ZxNe9TqUV Fn50XuSV8+nc5NgXuan98KuAEIU4P/GByYrl2fX+sbaPkCWxstES4dZAHasZvrL4D9Lx NQh/pxbYEogjo264mysBIrCtOEik0no4yfJSiRAC/jDbc+H3jnh+RI4Lb4IWEiMTHa4m 5uBMogqX4fZJHFXyvXxCeNALRQ3u32FAzC0P3wjWspL3gdG2cErzcfbszSuijvPActZw /VzEI7uBe+M+96uYRLK8uiC3zLNOegTMeSTGtskO0BEmimZQnloCtZFCFE6XkOQZjj8r 44vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=jtz8TJJPP02uY2H+u7P9RmyTGqPKE3q5STjCj4ikXWM=; b=mBOUfcjQOjlUKpn6mGtv8Rq/o87+yHIfiMNqDfIOurMXMcIVsf5Vn72usNjTggSuXF jKrQNRPaE0LOMxsX7++OYeAInUf9kUshLw8h/Q9O0BORvWznqAS2CYOPwOcPTZVYEsrl vuv/+6X61OolIu+VKkT6dd/mJHS89JnYajPm2Erainxl7BpB4P+9Ic9nB/oVrFxH0iQ5 /3Rla9ojqpgh6vZHIjAhRKDVg49sUMsJWbeOUZ8IG07j02vNlS5K/qEhEmbSzbJLhM43 iEPXE3Z9P+p84wayXdAmoGNYLvA+lwAzf2Qx0ScsiatuL9ZNvy+unePWVab6rwFNOhd9 0amQ== X-Gm-Message-State: AA+aEWYBjodemWMkhzO4qNclfxDCSIr98XkKL96YwTrGnnAcUPLMBwom QSQ4L0LwzkHxDbXUb7q0wbA= X-Google-Smtp-Source: AFSGD/V8TzVHk0AchTCogJakQyquvea5UoQsPlM/mOvUftdH2VY14BQ/4pTYveJqCdH18ViGza6rEA== X-Received: by 2002:a65:4ccb:: with SMTP id n11mr14235932pgt.257.1544520606033; Tue, 11 Dec 2018 01:30:06 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.04 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:05 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:37 -0800 Message-Id: <1544520901-31558-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 01/25] riscv: add Kconfig entries for the code model X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Lukas Auer RISC-V has two code models, medium low (medlow) and medium any (medany). Medlow limits addressable memory to a single 2 GiB range between the absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory to any single 2 GiB address range. By default, medlow is selected for U-Boot on both 32-bit and 64-bit systems. The -mcmodel compiler flag is selected according to the Kconfig configuration. Signed-off-by: Lukas Auer [bmeng: adjust to make medlow the default code model for U-Boot] Signed-off-by: Bin Meng --- Changes in v3: None Changes in v2: None arch/riscv/Kconfig | 18 ++++++++++++++++++ arch/riscv/Makefile | 9 ++++++++- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 732a357..6d85ac9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -44,6 +44,24 @@ config ARCH_RV64I endchoice +choice + prompt "Code Model" + default CMODEL_MEDLOW + +config CMODEL_MEDLOW + bool "medium low code model" + help + U-Boot and its statically defined symbols must lie within a single 2 GiB + address range and must lie between absolute addresses -2 GiB and +2 GiB. + +config CMODEL_MEDANY + bool "medium any code model" + help + U-Boot and its statically defined symbols must be within any single 2 GiB + address range. + +endchoice + config RISCV_ISA_C bool "Emit compressed instructions" default y diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 55d7c65..0b80eb8 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -17,8 +17,15 @@ endif ifeq ($(CONFIG_RISCV_ISA_C),y) ARCH_C = c endif +ifeq ($(CONFIG_CMODEL_MEDLOW),y) + CMODEL = medlow +endif +ifeq ($(CONFIG_CMODEL_MEDANY),y) + CMODEL = medany +endif -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) +ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ + -mcmodel=$(CMODEL) PLATFORM_CPPFLAGS += $(ARCH_FLAGS) CFLAGS_EFI += $(ARCH_FLAGS) From patchwork Tue Dec 11 09:34:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010918 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OXvijEIr"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZTX1Xk6z9s0t for ; Tue, 11 Dec 2018 20:32:00 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DA8ACC22441; Tue, 11 Dec 2018 09:31:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C9B5EC2255A; Tue, 11 Dec 2018 09:30:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2BB63C22547; Tue, 11 Dec 2018 09:30:12 +0000 (UTC) Received: from mail-pg1-f193.google.com (mail-pg1-f193.google.com [209.85.215.193]) by lists.denx.de (Postfix) with ESMTPS id 646A6C2218C for ; Tue, 11 Dec 2018 09:30:08 +0000 (UTC) Received: by mail-pg1-f193.google.com with SMTP id z10so6374605pgp.7 for ; Tue, 11 Dec 2018 01:30:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=1U49LM72ImzrbN72F6vX/e7iSCDDDiKRVipphhOY/wA=; b=OXvijEIr0rDd8g0AhNLkMMqX5xxOIWqx0bZOLnK6mgz6a+/oXbrYC6mZo3RimmATbq lykfKgFOXyJ77+CoqB7PpRsSQxlTd49NBojVNsnvbaxESMG2VxVWBdjtzVXon9FHiP1v s4fvvxQx6bFcbeLIfeTLzx6znACTnpBl09ZpMKjZ7XeKKtI14uRoK+XTeidJ5S6OjduN q+bzs1eEL3sEPSCGeNienk88FdA63Ny2xh5dwrghtsQ/Kc1UwdkmEfMAxW9r9WeR0u4z YHVO06uZ5JwVQN3kNfahieMbum1JCxKQGCy0unfvvjZ56iaeqJ6rtYbghGnJg+Hu/ore ZrzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=1U49LM72ImzrbN72F6vX/e7iSCDDDiKRVipphhOY/wA=; b=kH7kgzYCj0FgQ7HbRTn26wUN4kJfXI21SwULtzFpZUmlGlLATvGhWUryvVkv0PrEba xQWDJrjeKC9/wfE9Dn7IkwZwif01HYOP60SRss/akZJZjbMjZNHVuCTZVapmKSZgHZSr i69bHQ2fIOSxtOfuMKb4LhjUCAO6nJ7Hbpsq9gAKO6knnOquDFIjtTpAbN+l18nMzpO5 ruCGiUcxD1soAH0Zy7tU99Rd1fJ8nncSVFzqRRByJ58toMLn6CY6tc4+G/TzH0iql7r+ C/y5Hl2AXTtwzYldYXln+/SArFTWKlWEelwP2HcKSkhRHVAzTjm56+4L5/fENcKFOr1h XkmQ== X-Gm-Message-State: AA+aEWYlZU4MJhRmu+bLYwxQmjev16o9DGY9OknsQc5XsEQ53aqLeFoa d97G2MVfskx7lCH5MTjMOTU= X-Google-Smtp-Source: AFSGD/XWVN1mnqJ8Cue+ycHHDg29rtELVZWzHb9u358SDZ/PTldG9C1RmEM3PBBzBP5R9J0TjAGgZg== X-Received: by 2002:a62:8f8c:: with SMTP id n134mr15855176pfd.137.1544520607036; Tue, 11 Dec 2018 01:30:07 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.06 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:06 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:38 -0800 Message-Id: <1544520901-31558-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 02/25] dm: cpu: Add timebase frequency to the platdata X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds a timebase_freq member to the 'struct cpu_platdata', to hold the "timebase-frequency" value in the cpu or /cpus node. Signed-off-by: Bin Meng Reviewed-by: Simon Glass Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: - Use 'Hz' instead of 'HZ' include/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/cpu.h b/include/cpu.h index 367c5f4..28dd48f 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -14,6 +14,8 @@ * @device_id: Driver-defined device identifier * @family: DMTF CPU Family identifier * @id: DMTF CPU Processor identifier + * @timebase_freq: the current frequency at which the cpu timer timebase + * registers are updated (in Hz) * * This can be accessed with dev_get_parent_platdata() for any UCLASS_CPU * device. @@ -24,6 +26,7 @@ struct cpu_platdata { ulong device_id; u16 family; u32 id[2]; + u32 timebase_freq; }; /* CPU features - mostly just a placeholder for now */ From patchwork Tue Dec 11 09:34:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010919 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BQq8zcQE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZVB1fl3z9s0t for ; Tue, 11 Dec 2018 20:32:34 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CDF68C225C5; Tue, 11 Dec 2018 09:30:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EEB89C22133; Tue, 11 Dec 2018 09:30:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 36E97C223CA; Tue, 11 Dec 2018 09:30:13 +0000 (UTC) Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) by lists.denx.de (Postfix) with ESMTPS id 63608C2240B for ; Tue, 11 Dec 2018 09:30:09 +0000 (UTC) Received: by mail-pf1-f194.google.com with SMTP id c123so6868635pfb.0 for ; Tue, 11 Dec 2018 01:30:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=E/cKMJldGGvfCuk4M/GOg29dMQxiCoTSkXOXAVQCpTk=; b=BQq8zcQEesB9ufPfad2li3Dwu0JqKoSvudIMH/xDbioknmLolq9q0TpSqIs9q7qVPj pLW5Ew2uNnzaInf37+AQ0oVxnVf+5F3F8ooM4ES3l7r51yrdVQnuLvR+TSwFnoP/epcc tb1jCPcbE5GfYi3BV9UQISX2eOUZ3rF7y79SPA2QXBdUFFjtroHYs4vZm5adNEUZwDGj binuyrTkjn08UPRRSz/hr7Tr2yV5BfMWM19g1unekpYD5ZoMDNlPRD3Pj8in1u9S03YC hHDckbBWovl21MK8nCjRcNYqSxM9Ynrp7jUzzT9PfkGm0/cRVH1we67zswtiBEG7+2cP zXiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=E/cKMJldGGvfCuk4M/GOg29dMQxiCoTSkXOXAVQCpTk=; b=EdLW3oGCJvzSGXK5p5Ak82KSgNX0WJxgYC4gb1apbdQg9PbX3waj09sAmjzUZwKlis zKbdi24+bAizZ22vDeOFZm4ZY3gKTs7UvQPGimUt2PR0Gbfi2l3R8GwTJCjB5+gaO3oN n2DuiPzoAX4KdZongsjuc9UR2ZbqKcr4ACV9bFq1YHc/r+Ho3jg98O2M6MSK7hOdHUlz ONBAf7R0/u+xjOB2zdBWMjFX8QUWoEIJ1SKKNPUdsjjYZwGBMWB2QDGHoZLmDu+/VXgi aDsZy2YmnrR0vwAXmB6hRADwjAh959Z+s43JWw4bi69YubQfoE69ST/0BnOnIil+An6G 9ClQ== X-Gm-Message-State: AA+aEWb44qNYg9RfuQc2GcHBpaCEg93VthMTWBdY7dYa+nOgwxt92EwF nhMDtDB6tBVs9Jjrl9BCx9w= X-Google-Smtp-Source: AFSGD/UdDTejZHr6aZYEknXAnkkxyvm8texC5o9IhxYYre4ypsVll/Wsjr3S5o12EzcziTa2SD3Rww== X-Received: by 2002:a63:42c1:: with SMTP id p184mr13897171pga.202.1544520608021; Tue, 11 Dec 2018 01:30:08 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.07 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:07 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:39 -0800 Message-Id: <1544520901-31558-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 03/25] riscv: qemu: Create a simple-bus driver for the soc node X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" To enumerate devices on the /soc/ node, create a "simple-bus" driver to match "riscv-virtio-soc". Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: - add DM_FLAG_PRE_RELOC flag to the simple-bus driver arch/riscv/cpu/qemu/cpu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c index 25d97d0..ad2950c 100644 --- a/arch/riscv/cpu/qemu/cpu.c +++ b/arch/riscv/cpu/qemu/cpu.c @@ -4,6 +4,7 @@ */ #include +#include /* * cleanup_before_linux() is called just before we call linux @@ -19,3 +20,16 @@ int cleanup_before_linux(void) return 0; } + +/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */ +static const struct udevice_id riscv_virtio_soc_ids[] = { + { .compatible = "riscv-virtio-soc" }, + { } +}; + +U_BOOT_DRIVER(riscv_virtio_soc) = { + .name = "riscv_virtio_soc", + .id = UCLASS_SIMPLE_BUS, + .of_match = riscv_virtio_soc_ids, + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Tue Dec 11 09:34:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010932 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UjLkyHjx"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZhc3Nsnz9s4s for ; Tue, 11 Dec 2018 20:41:36 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2B871C2269B; Tue, 11 Dec 2018 09:31:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9F472C225D2; Tue, 11 Dec 2018 09:30:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 575D5C221A9; Tue, 11 Dec 2018 09:30:14 +0000 (UTC) Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by lists.denx.de (Postfix) with ESMTPS id 66299C2246B for ; Tue, 11 Dec 2018 09:30:10 +0000 (UTC) Received: by mail-pf1-f196.google.com with SMTP id c123so6868665pfb.0 for ; Tue, 11 Dec 2018 01:30:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=MFGF1TfzubpnjqnM0TzUbu1L80Q6ISnV/CWLVaq7IhQ=; b=UjLkyHjxSxuhAvfCZYRuaGQsSo0yqwEnt4FZchiqPE/dIYlSj2NEJRp5b9IS4f3r9z 4bCoQBLXBnKxMpvwbfT+bWd7tv9VwYqXwcrxPiWVvHYl8E4ZHad8CWpnXmEvYbbOfFew OIBR5PdbADmdcUa0S7NGYeBZOtn+sn1vl3g0IIzQ5g6a8wPg6KpXGEJgI5PePssJnh5E AKRIYI9ufonEQf4gM1cGr+/IUy1g098LmzVE1HnJKQPPCT1o1sgeqeHmiUnD+zkqjyO8 GRNP6Zp5SD0aIZiJIVPeKH92iNF0C862fC111S0AO7fcKR8B/K1fO1ODsWNYe++Vdmb0 6DVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=MFGF1TfzubpnjqnM0TzUbu1L80Q6ISnV/CWLVaq7IhQ=; b=Pc5+EzvtOVdu+81DryB29p8fpIbL58n7AWO5jRwLInI5weqrtBdCpP9G5dOWsCsdfh XVBCRDQrvjip9fq/jYadHleVOxjClsdRSR/DnDeN/BGWU4zTwQLPO4Eg5W5ExIOPeYOC kgf0DlrSn8f/dlEeo06qcPkwAesO3fT8tUgMdZ6m97bEgXJ5Y/Tj31L06Ka835LsyIaq Ga//VB/VNxgPU3SKWAK25xD3+seRORvHVLRGRz8DfkDAfjlZbAXdFkLlhJvt/knxgS0y ua+MVQKXouvZBQk9tHefz3WqTPofp+pDcoRvWvI7eyMmPrMX53r+2TZAG5I+nOfgdkWj qr8A== X-Gm-Message-State: AA+aEWYiBnIypwr4OgLZL7lJVcckqhql+TZLQRC44MpD0AoBXgGmjv98 Nc94HySzS6bRZm67X8brnyk= X-Google-Smtp-Source: AFSGD/WDohsLnBtBCMGQg9WkYU4dSTTXQfXHxEUpTLgH0Dn7rObnzKTutNtyiXI9hEmD6kMDqN/pyQ== X-Received: by 2002:a62:6408:: with SMTP id y8mr15535338pfb.202.1544520608990; Tue, 11 Dec 2018 01:30:08 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.08 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:08 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:40 -0800 Message-Id: <1544520901-31558-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 04/25] cpu: Add a RISC-V CPU driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds a driver for RISC-V CPU. Note the driver will bind a RISC-V timer driver if "timebase-frequency" property is present in the device tree. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: - pass NULL as the timer device to device_bind_with_driver_data() drivers/cpu/Kconfig | 6 +++ drivers/cpu/Makefile | 1 + drivers/cpu/riscv_cpu.c | 116 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 123 insertions(+) create mode 100644 drivers/cpu/riscv_cpu.c diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig index d405200..3d5729f 100644 --- a/drivers/cpu/Kconfig +++ b/drivers/cpu/Kconfig @@ -13,3 +13,9 @@ config CPU_MPC83XX select CLK_MPC83XX help Support CPU cores for SoCs of the MPC83xx series. + +config CPU_RISCV + bool "Enable RISC-V CPU driver" + depends on CPU && RISCV + help + Support CPU cores for RISC-V architecture. diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile index 858b037..be0300c 100644 --- a/drivers/cpu/Makefile +++ b/drivers/cpu/Makefile @@ -8,4 +8,5 @@ obj-$(CONFIG_CPU) += cpu-uclass.o obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o +obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o obj-$(CONFIG_SANDBOX) += cpu_sandbox.o diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c new file mode 100644 index 0000000..5e15df5 --- /dev/null +++ b/drivers/cpu/riscv_cpu.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include +#include +#include +#include + +static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size) +{ + const char *isa; + + isa = dev_read_string(dev, "riscv,isa"); + if (size < (strlen(isa) + 1)) + return -ENOSPC; + + strcpy(buf, isa); + + return 0; +} + +static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info) +{ + const char *mmu; + + dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); + + mmu = dev_read_string(dev, "mmu-type"); + if (!mmu) + info->features |= BIT(CPU_FEAT_MMU); + + return 0; +} + +static int riscv_cpu_get_count(struct udevice *dev) +{ + ofnode node; + int num = 0; + + ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { + const char *device_type; + + device_type = ofnode_read_string(node, "device_type"); + if (!device_type) + continue; + if (strcmp(device_type, "cpu") == 0) + num++; + } + + return num; +} + +static int riscv_cpu_bind(struct udevice *dev) +{ + struct cpu_platdata *plat = dev_get_parent_platdata(dev); + struct driver *drv; + int ret; + + /* save the hart id */ + plat->cpu_id = dev_read_addr(dev); + + /* first examine the property in current cpu node */ + ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); + /* if not found, then look at the parent /cpus node */ + if (ret) + dev_read_u32(dev->parent, "timebase-frequency", + &plat->timebase_freq); + + /* + * Bind riscv-timer driver on hart 0 + * + * We only instantiate one timer device which is enough for U-Boot. + * Pass the "timebase-frequency" value as the driver data for the + * timer device. + * + * Return value is not checked since it's possible that the timer + * driver is not included. + */ + if (!plat->cpu_id && plat->timebase_freq) { + drv = lists_driver_lookup_name("riscv_timer"); + if (!drv) { + debug("Cannot find the timer driver, not included?\n"); + return 0; + } + + device_bind_with_driver_data(dev, drv, "riscv_timer", + plat->timebase_freq, ofnode_null(), + NULL); + } + + return 0; +} + +static const struct cpu_ops riscv_cpu_ops = { + .get_desc = riscv_cpu_get_desc, + .get_info = riscv_cpu_get_info, + .get_count = riscv_cpu_get_count, +}; + +static const struct udevice_id riscv_cpu_ids[] = { + { .compatible = "riscv" }, + { } +}; + +U_BOOT_DRIVER(riscv_cpu) = { + .name = "riscv_cpu", + .id = UCLASS_CPU, + .of_match = riscv_cpu_ids, + .bind = riscv_cpu_bind, + .ops = &riscv_cpu_ops, + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Tue Dec 11 09:34:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010921 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ia9NjQE8"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZWh3BH0z9s0t for ; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.09 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:09 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:41 -0800 Message-Id: <1544520901-31558-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 05/25] timer: Add generic driver for RISC-V privileged architecture defined timer X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - remove 'select RISCV_CLINT' in Kconfig - do not mention the spec version number v1.10 - adjust riscv_get_time() API signature to have a return value Changes in v2: - remove the probe to syscon driver in the timer probe, to make the driver generic, and rely on platform codes to provide the API riscv_get_time(). drivers/timer/Kconfig | 7 ++++++ drivers/timer/Makefile | 1 + drivers/timer/riscv_timer.c | 56 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+) create mode 100644 drivers/timer/riscv_timer.c diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index b0e6f32..df37a79 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -126,6 +126,13 @@ config OMAP_TIMER help Select this to enable an timer for Omap devices. +config RISCV_TIMER + bool "RISC-V timer support" + depends on TIMER && RISCV + help + Select this to enable support for the timer as defined + by the RISC-V privileged architecture spec. + config ROCKCHIP_TIMER bool "Rockchip timer support" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index c4fbab2..d0bf218 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o obj-$(CONFIG_OMAP_TIMER) += omap-timer.o +obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c new file mode 100644 index 0000000..9f9f070 --- /dev/null +++ b/drivers/timer/riscv_timer.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * RISC-V privileged architecture defined generic timer driver + * + * This driver relies on RISC-V platform codes to provide the essential API + * riscv_get_time() which is supposed to return the timer counter as defined + * by the RISC-V privileged architecture spec. + * + * This driver can be used in both M-mode and S-mode U-Boot. + */ + +#include +#include +#include +#include +#include + +/** + * riscv_get_time() - get the timer counter + * + * Platform codes should provide this API in order to make this driver function. + * + * @time: the 64-bit timer count as defined by the RISC-V privileged + * architecture spec. + * @return: 0 on success, -ve on error. + */ +extern int riscv_get_time(u64 *time); + +static int riscv_timer_get_count(struct udevice *dev, u64 *count) +{ + return riscv_get_time(count); +} + +static int riscv_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + /* clock frequency was passed from the cpu driver as driver data */ + uc_priv->clock_rate = dev->driver_data; + + return 0; +} + +static const struct timer_ops riscv_timer_ops = { + .get_count = riscv_timer_get_count, +}; + +U_BOOT_DRIVER(riscv_timer) = { + .name = "riscv_timer", + .id = UCLASS_TIMER, + .probe = riscv_timer_probe, + .ops = &riscv_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Tue Dec 11 09:34:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010934 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.10 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:10 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:42 -0800 Message-Id: <1544520901-31558-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 06/25] riscv: ax25: Hide the ax25-specific Kconfig option X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" There is no need to expose RISCV_NDS to the Kconfig menu as it is an ax25-specific option. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/cpu/ax25/Kconfig | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 6c7022f..5ff9e5c 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -1,7 +1,5 @@ config RISCV_NDS - bool "AndeStar V5 ISA support" - default n + bool help - Say Y here if you plan to run U-Boot on AndeStar v5 - platforms and use some specific features which are - provided by Andes Technology AndeStar V5 Families. + Run U-Boot on AndeStar v5 platforms and use some specific features + which are provided by Andes Technology AndeStar V5 Families. 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.11 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:11 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:43 -0800 Message-Id: <1544520901-31558-8-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 07/25] riscv: Introduce a Kconfig option for machine mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Anup Patel So far we have a Kconfig option for supervisor mode. This adds an option for the machine mode. Signed-off-by: Anup Patel Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: - incorporated and reworked Anup's S-mode timer patch @ http://patchwork.ozlabs.org/patch/1006663/ arch/riscv/Kconfig | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6d85ac9..55c60e4 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -62,6 +62,22 @@ config CMODEL_MEDANY endchoice +choice + prompt "Run Mode" + default RISCV_MMODE + +config RISCV_MMODE + bool "Machine" + help + Choose this option to build U-Boot for RISC-V M-Mode. + +config RISCV_SMODE + bool "Supervisor" + help + Choose this option to build U-Boot for RISC-V S-Mode. + +endchoice + config RISCV_ISA_C bool "Emit compressed instructions" default y @@ -73,11 +89,6 @@ config RISCV_ISA_C config RISCV_ISA_A def_bool y -config RISCV_SMODE - bool "Run in S-Mode" - help - Enable this option to build U-Boot for RISC-V S-Mode - config 32BIT bool From patchwork Tue Dec 11 09:34:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010922 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Lo0R41sr"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZZN5tFZz9s0t for ; Tue, 11 Dec 2018 20:36:12 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 89326C22133; Tue, 11 Dec 2018 09:33:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3C376C222B7; Tue, 11 Dec 2018 09:30:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 279FDC22645; Tue, 11 Dec 2018 09:30:18 +0000 (UTC) Received: from mail-pl1-f194.google.com (mail-pl1-f194.google.com [209.85.214.194]) by lists.denx.de (Postfix) with ESMTPS id 99EB5C224E4 for ; Tue, 11 Dec 2018 09:30:14 +0000 (UTC) Received: by mail-pl1-f194.google.com with SMTP id e5so6663083plb.5 for ; Tue, 11 Dec 2018 01:30:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=nVuKDiGL9w5KlopY25hdYANLUPvI6EzHqyW1+gJlmV0=; b=Lo0R41srBeAhSNuFCRCLwW6bUxEf3MhCGCGc+iijJrnsH1maljTxajNnYOtQK8u2RC cWPcW+7Bv5L0zMm1wRNFIMWZKSYWVUUa5m7tK0HNgBF2yvQkIYQBKHHpImE6gQrCN7lW Z6vgL6GLhQlGNX5AvyybAHo6UvRc1NzTLjqxzHEuNLlEtvHMMkPhlIHE4ImB2+JMcux7 t4SRCAKlLbBqARRaZf+sgKVKGupQ/Fr4nC5GMYGg7eYIBJLkIQ+NxCpwdyCU/icwzPIl ylKrPW6n1zVFok7TB/4eIKmzggr+R8j+RqE/e+vkgxQ5cTItSVYedpI9vTdQOxK3XCxq csmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=nVuKDiGL9w5KlopY25hdYANLUPvI6EzHqyW1+gJlmV0=; b=iu5k8o7vVGpavNhjGtj3RfvK0UPnD05uyzm4t3GcvhXXtgW41OpJ7iYPjO9FT5tiiQ G5bJ0J/Tk0ED32pWXJSDC54TOKA4DWEI84Lou2gg5mp7JcFQzaRxNPLKkBWV3/sfJdLY EdrAwP2HhnzUHKXHJgJJSayS6o9wyB91074+VtcR8xbaKSIh9dlNKuznVlIAbbaOrQrj LX6hHDnyWWY1B1mT3WEOsW4JUNJmV5hCX8TTJukPrdQZuK8fIrcWBXuTF7gwIWpMC6cD ITmHPKZYEqK3/5hbOSJnQvM/5mSGOgbpao3K1aFyX+PFZzQQB0gzXiGsHFM2PWBThDW0 +oKA== X-Gm-Message-State: AA+aEWZh4yUbUjR1e/Ooensh4W72HwfGIgcRNzD1JGuYpFQfhsmBE/ti tA8XN2YneDYt6GP24dX/NfE= X-Google-Smtp-Source: AFSGD/WOMQ2+vAvs6G85+6ybXqyN5B/ZUlLDVZrEwjKZtgij2Mf3s7q/PjZ1kAwYMdBexPbXTZWZgA== X-Received: by 2002:a17:902:848d:: with SMTP id c13mr15429686plo.257.1544520613150; Tue, 11 Dec 2018 01:30:13 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.12 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:12 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:44 -0800 Message-Id: <1544520901-31558-9-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 08/25] riscv: Add a SYSCON driver for SiFive's Core Local Interruptor X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - check return value of syscon_get_first_range() Changes in v2: - rename the driver name to sifive_clint - save the clint base address to arch specific global data to support pre-relocation stage - remove the probe routine - add riscv_clear_ipi() API arch/riscv/Kconfig | 9 ++++ arch/riscv/include/asm/global_data.h | 3 ++ arch/riscv/include/asm/syscon.h | 19 ++++++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/sifive_clint.c | 84 ++++++++++++++++++++++++++++++++++++ 5 files changed, 116 insertions(+) create mode 100644 arch/riscv/include/asm/syscon.h create mode 100644 arch/riscv/lib/sifive_clint.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 55c60e4..f513f52 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -95,4 +95,13 @@ config 32BIT config 64BIT bool +config SIFIVE_CLINT + bool + depends on RISCV_MMODE + select REGMAP + select SYSCON + help + The SiFive CLINT block holds memory-mapped control and status registers + associated with software and timer interrupts. + endmenu diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 4d5d623..46fcfab 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -12,6 +12,9 @@ /* Architecture-specific global data */ struct arch_global_data { +#ifdef CONFIG_SIFIVE_CLINT + void __iomem *clint; /* clint base address */ +#endif }; #include diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h new file mode 100644 index 0000000..d311ee6 --- /dev/null +++ b/arch/riscv/include/asm/syscon.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng + */ + +#ifndef _ASM_SYSCON_H +#define _ASM_SYSCON_H + +/* + * System controllers in a RISC-V system + * + * So far only SiFive's Core Local Interruptor (CLINT) is defined. + */ +enum { + RISCV_NONE, + RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */ +}; + +#endif /* _ASM_SYSCON_H */ diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b58db89..b13c876 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o +obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-y += interrupts.o obj-y += reset.o obj-y += setjmp.o diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c new file mode 100644 index 0000000..d24e0d5 --- /dev/null +++ b/arch/riscv/lib/sifive_clint.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). + * The CLINT block holds memory-mapped control and status registers + * associated with software and timer interrupts. + */ + +#include +#include +#include +#include +#include +#include + +/* MSIP registers */ +#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4) +/* mtime compare register */ +#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) +/* mtime register */ +#define MTIME_REG(base) ((ulong)(base) + 0xbff8) + +DECLARE_GLOBAL_DATA_PTR; + +#define CLINT_BASE_GET(void) \ + do { \ + long *ret; \ + \ + if (!gd->arch.clint) { \ + ret = syscon_get_first_range(RISCV_SYSCON_CLINT); \ + if (IS_ERR(ret)) \ + return PTR_ERR(ret); \ + gd->arch.clint = ret; \ + } \ + } while (0) + +int riscv_get_time(u64 *time) +{ + CLINT_BASE_GET(); + + *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); + + return 0; +} + +int riscv_set_timecmp(int hart, u64 cmp) +{ + CLINT_BASE_GET(); + + writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); + + return 0; +} + +int riscv_send_ipi(int hart) +{ + CLINT_BASE_GET(); + + writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); + + return 0; +} + +int riscv_clear_ipi(int hart) +{ + CLINT_BASE_GET(); + + writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); + + return 0; +} + +static const struct udevice_id sifive_clint_ids[] = { + { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT }, + { } +}; + +U_BOOT_DRIVER(sifive_clint) = { + .name = "sifive_clint", + .id = UCLASS_SYSCON, + .of_match = sifive_clint_ids, + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Tue Dec 11 09:34:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010917 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="fmRZYu73"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZTG2Q0jz9s0t for ; Tue, 11 Dec 2018 20:31:44 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C631DC22789; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.13 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:13 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:45 -0800 Message-Id: <1544520901-31558-10-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 09/25] riscv: Implement riscv_get_time() API using rdtime instruction X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Anup Patel This adds an implementation of riscv_get_time() API that is using rdtime instruction. This is the case for S-mode U-Boot, and is useful for processors that support rdtime in M-mode too. Signed-off-by: Anup Patel Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: - incorporated and reworked Anup's S-mode timer patch @ http://patchwork.ozlabs.org/patch/1006663/ arch/riscv/Kconfig | 8 ++++++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/rdtime.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+) create mode 100644 arch/riscv/lib/rdtime.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f513f52..7dc6e3f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -104,4 +104,12 @@ config SIFIVE_CLINT The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config RISCV_RDTIME + bool + default y if RISCV_SMODE + help + The provides the riscv_get_time() API that is implemented using the + standard rdtime instruction. This is the case for S-mode U-Boot, and + is useful for processors that support rdtime in M-mode too. + endmenu diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b13c876..edfa616 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o +obj-$(CONFIG_RISCV_RDTIME) += rdtime.o obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-y += interrupts.o obj-y += reset.o diff --git a/arch/riscv/lib/rdtime.c b/arch/riscv/lib/rdtime.c new file mode 100644 index 0000000..e128d7f --- /dev/null +++ b/arch/riscv/lib/rdtime.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Anup Patel + * Copyright (C) 2018, Bin Meng + * + * The riscv_get_time() API implementation that is using the + * standard rdtime instruction. + */ + +#include + +/* Implement the API required by RISC-V timer driver */ +int riscv_get_time(u64 *time) +{ +#ifdef CONFIG_64BIT + u64 n; + + __asm__ __volatile__ ( + "rdtime %0" + : "=r" (n)); + + *time = n; +#else + u32 lo, hi, tmp; + + __asm__ __volatile__ ( + "1:\n" + "rdtimeh %0\n" + "rdtime %1\n" + "rdtimeh %2\n" + "bne %0, %2, 1b" + : "=&r" (hi), "=&r" (lo), "=&r" (tmp)); + + *time = ((u64)hi << 32) | lo; +#endif + + return 0; +} From patchwork Tue Dec 11 09:34:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010930 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="YOWxSRQX"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZhG2M0bz9s3l for ; Tue, 11 Dec 2018 20:41:18 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 047D5C22133; Tue, 11 Dec 2018 09:34:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E9DBCC22634; Tue, 11 Dec 2018 09:30:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8C36EC22605; Tue, 11 Dec 2018 09:30:20 +0000 (UTC) Received: from mail-pl1-f196.google.com (mail-pl1-f196.google.com [209.85.214.196]) by lists.denx.de (Postfix) with ESMTPS id 7C030C223CA for ; Tue, 11 Dec 2018 09:30:16 +0000 (UTC) Received: by mail-pl1-f196.google.com with SMTP id 101so6661946pld.6 for ; Tue, 11 Dec 2018 01:30:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=o/CYIw5sLVjogRo6UkIIhFyp2dcTufWM0oN7o82SiwU=; b=YOWxSRQX7fSyaIYZ5JklrNch+ETvxEXNvXnztJge/t/8XQED7SPBR6IpQbGY0xWFAP u8YXEyitmE8x3GO3dxzRTTwyuveGuBqo8B1iD//H9+Wj7tOZSDn5v7Aswxpksj428Egd A9oeLLqvyj97AgD9oOT9vrEkNuChAp0MtBeKrrdSwKwXRadNAjPDfMhX9fkx1cZVjDQI 9oYfUCILH4N2koLOO5iYw0cpwq4t1b72k1sLMR+qLW5y8PA/A94J1MSGww0uhYALPf9Y IUCxUqzmxlBA8RFpms9hqYUCEZRNoLEJ+mtpPXzPAcq4VUeTjR9NSrpLIDiRlBm6nzX7 p17Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=o/CYIw5sLVjogRo6UkIIhFyp2dcTufWM0oN7o82SiwU=; b=ndEmknhJtIXFnqfCMHclHpSoIJz3003ZaFh6RnwYPoXaiQfTGH283JbqAYSIJrEzrL tlt0k4O0qeNYGdFJxiOS433zFFh0A8NNasW0sBSBjXmzehGNDctAEpGdLZJTh/fk9JeC 29ZCx8ZwId5oikzae5pbSYI1RUqWNYAIxzo7bj1TxX28qp7BstMboJHDO3GR6gXvg6V3 OQnlISWSHSt6zmAjcrXeCxUT1o27NIqg3vVTMo+a8IBFO8Bd1SlMPPDtfyh4ElHmpPUZ v2chB05MyQQLBPj+miZvTx2ztFGTim30P6Ex39qmmCJ0/IJS+u99de4Nx6vcic6Pw7p3 Ks5A== X-Gm-Message-State: AA+aEWb5lyJa3uF49NOrogZZHQ3AOienep79pOgmSbN8pOm9CrPcQ42W QXML2ttLKKe6dZLH/8er8fY= X-Google-Smtp-Source: AFSGD/V/tRA2SCVYj6d0hzYuAQ12A8Mm/Vb/fPZ25FVdMgb5xNFkqxfU5rWH3FZ+dAYL/E1cfvOzKg== X-Received: by 2002:a17:902:9887:: with SMTP id s7mr14994993plp.199.1544520615181; Tue, 11 Dec 2018 01:30:15 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.14 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:14 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:46 -0800 Message-Id: <1544520901-31558-11-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 10/25] riscv: qemu: Add platform-specific Kconfig options X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: - add CMD_CPU as well arch/riscv/Kconfig | 1 + arch/riscv/cpu/qemu/Kconfig | 11 +++++++++++ board/emulation/qemu-riscv/Kconfig | 1 + 3 files changed, 13 insertions(+) create mode 100644 arch/riscv/cpu/qemu/Kconfig diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7dc6e3f..39ca2d8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -22,6 +22,7 @@ source "board/emulation/qemu-riscv/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" +source "arch/riscv/cpu/qemu/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/qemu/Kconfig new file mode 100644 index 0000000..2e953e1 --- /dev/null +++ b/arch/riscv/cpu/qemu/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng + +config QEMU_RISCV + bool + imply CPU + imply CPU_RISCV + imply RISCV_TIMER + imply SIFIVE_CLINT if RISCV_MMODE + imply CMD_CPU diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 56bb533..ed005e5 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -18,6 +18,7 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select QEMU_RISCV imply SYS_NS16550 imply VIRTIO_MMIO imply VIRTIO_NET From patchwork Tue Dec 11 09:34:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010925 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="i3aaC/qG"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZd15hbRz9s3l for ; Tue, 11 Dec 2018 20:38:29 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 784DCC2253C; Tue, 11 Dec 2018 09:34:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E31E4C226BD; Tue, 11 Dec 2018 09:30:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7E3B6C22197; Tue, 11 Dec 2018 09:30:21 +0000 (UTC) Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) by lists.denx.de (Postfix) with ESMTPS id 8B782C22172 for ; Tue, 11 Dec 2018 09:30:17 +0000 (UTC) Received: by mail-pg1-f196.google.com with SMTP id z10so6374820pgp.7 for ; Tue, 11 Dec 2018 01:30:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=dItgKU8Ylr+bQoTWoNs5OvvkFf1kZfypiZcOXujftfc=; b=i3aaC/qGJMG4dKv3yydUbCWkNWDAuBKOroJ8JgbDXO+l8NPeslkRlSKsZ+x1nRjxRG USjdofBS6Za/D0uDz8fTDh5fSD/T3TzlmQ6thahWeVMztrxl/VP1LDjz9BmNwwS0OEuB BuFaqD+/sCZd9GDYkpw1h0vp13IbpY/rm0uJFkhN5PTKYtxol/ltR7VM0tgLtMUOurhJ zxg6oKu5zvjaHxToaONoVf0rB/k5OQrBetAVx4tjZcCx4f3QWmOS1jhlRtu26y50DE5q SPBxkCh0ZOmFCar+eza/FupFmELxNSh+dkgdjUmlE8y1IF1/9+93i4q02P2qZiT97hop pIgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=dItgKU8Ylr+bQoTWoNs5OvvkFf1kZfypiZcOXujftfc=; b=JuXJnyHA0/N2i3QDC70bH9YW8Izhij55pin0BCFDRihDzdFlQxUDnjMk+SdhJfLg0y w0m6P97J/24ZtsYQMdWFss2eHVZ/+AhW0Oki3Tnayn5/ws2w1EXRYeFyYUFVkey6o79Z uw1F+nVTjujDJgSfw6opBGD5lRcyls8dfom6xxm3eEbmoYp/7JxrnLAmJZJfrv4RSZVt ZTtbJvCypREZa6eGR0RscPSFT50lD9SdtXupxVTTbhvndoiYbZkSvy0dWXol0ZYWuMkX g96y5LLgWOsTQ27AsrIQhkx0W++oLuB1GdqGPNS2t1rLrcKuKF2H8VWQNwDAkdtFDui0 tABw== X-Gm-Message-State: AA+aEWZvNEy0+7GY+h2KoL0L9X07tjVv7Cq6JuFZLg8Jl1AbwK4jlgmy fsK2/gdmLHPvNOvvkAYA3v8= X-Google-Smtp-Source: AFSGD/XahQ0/NYxdFnAZ5fPq9M2Zp+nFGpE+KGm3twKPPtn9yss9KkE9aPyciSWiGQyPzlX9/UFGwQ== X-Received: by 2002:a63:7044:: with SMTP id a4mr13703872pgn.359.1544520616254; Tue, 11 Dec 2018 01:30:16 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.15 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:15 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:47 -0800 Message-Id: <1544520901-31558-12-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 11/25] riscv: Enlarge the default SYS_MALLOC_F_LEN X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Increase the heap size for the pre-relocation stage, so that CPU driver can be loaded. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 39ca2d8..c45e4d7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -113,4 +113,7 @@ config RISCV_RDTIME standard rdtime instruction. This is the case for S-mode U-Boot, and is useful for processors that support rdtime in M-mode too. +config SYS_MALLOC_F_LEN + default 0x1000 + endmenu From patchwork Tue Dec 11 09:34:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010939 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="AWDmkg+0"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZmL68MMz9s9h for ; Tue, 11 Dec 2018 20:44:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 95E30C226DE; Tue, 11 Dec 2018 09:35:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D1C2EC226D9; Tue, 11 Dec 2018 09:31:09 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B5288C225AD; Tue, 11 Dec 2018 09:30:23 +0000 (UTC) Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) by lists.denx.de (Postfix) with ESMTPS id B8460C2251C for ; Tue, 11 Dec 2018 09:30:18 +0000 (UTC) Received: by mail-pf1-f194.google.com with SMTP id z9so6856707pfi.2 for ; Tue, 11 Dec 2018 01:30:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=/7hASM1lXnOiLdBE8BNGV9K99nA03Lj+M7ztvY7HwTs=; b=AWDmkg+06vLsGyN4lWnEbcWwnu2K+BHVxXqnXhxrOIeOr0L2zJ5YWGgQtWOrRXiSTg NLTyhmcuVAwp9TAh7YW3mDYE2Sac1+YNPqdGJba6ftheY8aA6uW1rZtKm3mbCkMEApzs N16Yff/juhJAH1KWtd44A8VRCe5xGy9VA3tRtuCY8K8lUVUmcfzi1bhM4QehSVuyE155 QniAltbAR3bscQWjUKX7LDKHNf40LE6A1TuEhC+Sr6cj+ijFJ8rD0YoNxsug4H9n95hC uFkQ8qonpNGpUpkuh+jnmb/CNM9W/P6Ly+uEw8o7qEHAnshZRa3Rj5mXi3uhH1aHrOPj U6xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=/7hASM1lXnOiLdBE8BNGV9K99nA03Lj+M7ztvY7HwTs=; b=lGBM0L9lDw60xowtGS8lKbWfJ5RIrgIPzUIBlyhavU/DPy/U+1zsclGpZtwMVm8WGE 1RDJLc4i5aN4sKV6jKePyRXUOzl+l4VFewLNAQlx6QrmY3aPnrHeeHTC2/UBvdqZ2r3q hLmh7vfblGBabwTQ0coZ7jUExU0omP7RuRDI8WI6lEmr0hZN47U1niYhJ9NOaBNFMB+I qQfbenOTVluI6CC7XyO82xFC1y2Y9KQU8VwW1CMuhHa4RBevYuXpkujf5OYBw3UiMlAV iHyq6HGvy+oCISJhAfVLTtNuOIiGFFxa0JICvZge0iRRYpIoEMrEbdMhcX55EqzHXvmz Mlcw== X-Gm-Message-State: AA+aEWak8ZAElxy33hY0ibZP1K9ULGzC8Zx0JXSwjjfsmgZYAqsjxIx5 P3Oe8jZnRRDByB8YeGh7YUs= X-Google-Smtp-Source: AFSGD/XUonsmZm8Vx8J46I8zTD0SnsiRC5wFOggGLltnVJVA2csKqWFp7fQfWDL7g+GizOI/2lR0xQ== X-Received: by 2002:a63:7556:: with SMTP id f22mr12774236pgn.231.1544520617376; Tue, 11 Dec 2018 01:30:17 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.16 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:16 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:48 -0800 Message-Id: <1544520901-31558-13-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 12/25] riscv: Probe cpus during boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This calls cpu_probe_all() to probe all available cpus. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - probe cpus in the pre-relocation stage too Changes in v2: - move to arch/riscv/cpu/cpu.c arch/riscv/cpu/cpu.c | 26 ++++++++++++++++++++++++++ arch/riscv/cpu/qemu/Kconfig | 1 + 2 files changed, 27 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index d9f820c..8286a0c 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include /* @@ -53,3 +55,27 @@ int print_cpuinfo(void) return 0; } + +static int riscv_cpu_probe(void) +{ +#ifdef CONFIG_CPU + int ret; + + /* probe cpus so that RISC-V timer can be bound */ + ret = cpu_probe_all(); + if (ret) + return log_msg_ret("RISC-V cpus probe failed\n", ret); +#endif + + return 0; +} + +int arch_cpu_init_dm(void) +{ + return riscv_cpu_probe(); +} + +int arch_early_init_r(void) +{ + return riscv_cpu_probe(); +} diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/qemu/Kconfig index 2e953e1..f48751e 100644 --- a/arch/riscv/cpu/qemu/Kconfig +++ b/arch/riscv/cpu/qemu/Kconfig @@ -4,6 +4,7 @@ config QEMU_RISCV bool + select ARCH_EARLY_INIT_R imply CPU imply CPU_RISCV imply RISCV_TIMER From patchwork Tue Dec 11 09:34:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010931 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Vn5jym8N"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZhN4Xztz9s3l for ; Tue, 11 Dec 2018 20:41:24 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3AF36C225D2; Tue, 11 Dec 2018 09:36:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BA53AC226CD; Tue, 11 Dec 2018 09:31:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 14F24C2245E; Tue, 11 Dec 2018 09:30:23 +0000 (UTC) Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) by lists.denx.de (Postfix) with ESMTPS id A916DC2258D for ; Tue, 11 Dec 2018 09:30:19 +0000 (UTC) Received: by mail-pl1-f172.google.com with SMTP id w4so6671356plz.1 for ; Tue, 11 Dec 2018 01:30:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=fE9Rw7z4i9/sTLMl5l7sdNNNRHgFpMSQKyQ7UxAR2Q8=; b=Vn5jym8NamEGW+cE/JPagM58J6SgWJix5QRaWYDre9WYni6k8oV9hs6d6cw83tvBJn eorlnqhjWzlTan2KGEkvTGhBie9vVXhTg3Cv7WFU1M+Zwa+G/rpnzjFq/n6/kTGVe+/i IztZxk1klJxfhNk6zwMfa+Z+J7YoaxgNazTymvhg9RATeNEwILWi5DomQrLJiNid2mKb TRX6wtp0KNprC4qSpXEqFynolQZwiLv85IEW0Up6rJXv2BlImqvIFYc2Rd03h3ja86o1 Qme62GXu1z7MJLhw9Bx3zmkuN9EjfG7gmksujWDDZi9LIX2uMAEW7RbVrkusNQjlhisv /Qrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=fE9Rw7z4i9/sTLMl5l7sdNNNRHgFpMSQKyQ7UxAR2Q8=; b=fJPQanUVDsYnEsPfmv1XC7CkxSw6lpxip/2Yt6QhXFx1G1vJGhoiXpIBFsg0EGRUbV 12hL/kI3C/tNnX9yW6j7TYEzifOA6qVF+X72tfzvpDCNC+aMyeWz76KSexQjOwn8jk1e F93KkJvtZSr+hed/81USI3sS2Hzb6KqADcMEKsvzQj4LNkq4Zw9a8HIWv3H6iIP3q6Ed KueSaXeG3qNEA+Ub8u2wbzZ0Ng5fBAAhEPLTP/+1PTSPsZWOvlrU+N1jTZPF25yKDhYp dPnzXqDnkSv2bp548hGLK1DwEHFEQM+qCWr/ZdLssE0xQHnoVo9G2XTIyDIl/4OPRN63 yrWg== X-Gm-Message-State: AA+aEWbZlgjrtM3q/fdcw3py/eBlgUx/x//GTROJSK+CSvtd6MND5TNK qPAPI75FWJEJACpX64a8Xwc= X-Google-Smtp-Source: AFSGD/X/wp7uGsZrTOlasomDAfWWDa+tZ+LwjWREuj95zXbS1d1USb6ENlEGMdO1/KxIOOLXlDOyyw== X-Received: by 2002:a17:902:4681:: with SMTP id p1mr15786260pld.184.1544520618321; Tue, 11 Dec 2018 01:30:18 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.17 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:17 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:49 -0800 Message-Id: <1544520901-31558-14-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 13/25] riscv: Remove non-DM version of print_cpuinfo() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" With DM CPU driver, the non-DM version of print_cpuinfo() is no longer needed. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - new patch to remove non-DM version of print_cpuinfo() Changes in v2: None arch/riscv/cpu/cpu.c | 37 ------------------------------------- 1 file changed, 37 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 8286a0c..d3c59da 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -14,48 +14,11 @@ */ phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); -enum { - ISA_INVALID = 0, - ISA_32BIT, - ISA_64BIT, - ISA_128BIT -}; - -static const char * const isa_bits[] = { - [ISA_INVALID] = NULL, - [ISA_32BIT] = "32", - [ISA_64BIT] = "64", - [ISA_128BIT] = "128" -}; - static inline bool supports_extension(char ext) { return csr_read(misa) & (1 << (ext - 'a')); } -int print_cpuinfo(void) -{ - char name[32]; - char *s = name; - int bit; - - s += sprintf(name, "rv"); - bit = csr_read(misa) >> (sizeof(long) * 8 - 2); - s += sprintf(s, isa_bits[bit]); - - supports_extension('i') ? *s++ = 'i' : 'r'; - supports_extension('m') ? *s++ = 'm' : 'i'; - supports_extension('a') ? *s++ = 'a' : 's'; - supports_extension('f') ? *s++ = 'f' : 'c'; - supports_extension('d') ? *s++ = 'd' : '-'; - supports_extension('c') ? *s++ = 'c' : 'v'; - *s++ = '\0'; - - printf("CPU: %s\n", name); - - return 0; -} - static int riscv_cpu_probe(void) { #ifdef CONFIG_CPU From patchwork Tue Dec 11 09:34:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010937 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WlYb5gdn"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZlS23wBz9s3l for ; Tue, 11 Dec 2018 20:44:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E47C2C2244E; Tue, 11 Dec 2018 09:37:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 14E8DC22530; Tue, 11 Dec 2018 09:31:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F199FC2246B; Tue, 11 Dec 2018 09:30:25 +0000 (UTC) Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by lists.denx.de (Postfix) with ESMTPS id C5F40C2253C for ; Tue, 11 Dec 2018 09:30:20 +0000 (UTC) Received: by mail-pf1-f196.google.com with SMTP id b7so6846052pfi.8 for ; Tue, 11 Dec 2018 01:30:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=9MHf2qNCZB+lhbSrFBn8E6m1siNhsuuu1Cpo7TffreI=; b=WlYb5gdn6u43FROUUVtk32xP6bfnMGzj5T9ZqWmhVknVasVwCH3h1Cmo09PU1sH0TH 8WyK6zgxEt6vAhjvI6mGskh9G0sbXe/rkYJOQdvQMu7abd/Ie8Ot2x3jqGHZMSDhQRX2 qj/mdkQE5qTRk7SkfIhh/RkuRGgBxZnUp0zeINqcQObvGjNMm7RBBbLy2wS754ENLF8o bZVt7f/bGMmTymoI1wj/VRyGUDOJZM6jZ0fVYTggH8Jwg4ksQrVNG26fMu64gV3895Nq iSHLaprbP/zjdtt9W39bG/o/NDM+LmCBVbekCE9qcq9ySa4fj+ECdsk23feQ+eS5vR5a aR6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=9MHf2qNCZB+lhbSrFBn8E6m1siNhsuuu1Cpo7TffreI=; b=J3dHmWheSw5akcYdIr/IFh8sXzrHFzB0qw/cHAhdULvRiFUW5hixjWNeZc87XoAXo0 UVoSTUHoM3eGryz0ybuAZ/MAZLmk7oh8ZtiGcJ8xc/MPVN8ckSNhO55WtzuthtQf/AwQ 0VaFfOiCBq0Kq6yls0Plrkhf40KNJhzYcIFT7A92AINirj8F6L5bYW0/OJShSl8jHlAF dlpVSX4w0CbNybHlqAYeoELboRnRW9j83OBGnAg0jKMgljnPIIVc1teboRrqeLUCmIJV aPcm8TEa0rjT8aqQDylLjUFEF3GqZW3magpwqi/ANx48wM/QKnsJ9gVVL6ebr9Ej97Ph qHdQ== X-Gm-Message-State: AA+aEWbDXe3sdqBB13yf5z9sFYE85gg7UBCltu6upC+jPHO1Vzl9kmAp LynTnN6gbZ9MqrJ8pV1oH/A= X-Google-Smtp-Source: AFSGD/WJh+sHQW5WL6XZvEIvPh9MqV0Le2c09ycbU3cllkKavjQ5x9CA9nSt/B7BeizXpXKtWTVbVw== X-Received: by 2002:a63:2d82:: with SMTP id t124mr13865866pgt.260.1544520619426; Tue, 11 Dec 2018 01:30:19 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.18 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:18 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:50 -0800 Message-Id: <1544520901-31558-15-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 14/25] riscv: Add CSR numbers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4096 CSRs. This adds all known CSR numbers as defined in the RISC-V Privileged Architecture Version 1.10. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - add sedeleg (0x102) and sideleg (0x103) CSRs Changes in v2: None arch/riscv/include/asm/encoding.h | 221 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 221 insertions(+) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 97cf906..05e1ce3 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -152,6 +152,227 @@ #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) +/* CSR numbers */ +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 + +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 + +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf + +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 + +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f + +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 + #endif /* __riscv */ #endif /* RISCV_CSR_ENCODING_H */ From patchwork Tue Dec 11 09:34:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010938 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mIEakCXn"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.19 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:19 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:51 -0800 Message-Id: <1544520901-31558-16-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 15/25] riscv: Add exception codes for xcause register X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds all exception codes in encoding.h. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/include/asm/encoding.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 05e1ce3..772668c 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -85,6 +85,21 @@ #define IRQ_COP 12 #define IRQ_HOST 13 +#define CAUSE_MISALIGNED_FETCH 0 +#define CAUSE_FETCH_ACCESS 1 +#define CAUSE_ILLEGAL_INSTRUCTION 2 +#define CAUSE_BREAKPOINT 3 +#define CAUSE_MISALIGNED_LOAD 4 +#define CAUSE_LOAD_ACCESS 5 +#define CAUSE_MISALIGNED_STORE 6 +#define CAUSE_STORE_ACCESS 7 +#define CAUSE_USER_ECALL 8 +#define CAUSE_SUPERVISOR_ECALL 9 +#define CAUSE_MACHINE_ECALL 11 +#define CAUSE_FETCH_PAGE_FAULT 12 +#define CAUSE_LOAD_PAGE_FAULT 13 +#define CAUSE_STORE_PAGE_FAULT 15 + #define DEFAULT_RSTVEC 0x00001000 #define DEFAULT_NMIVEC 0x00001004 #define DEFAULT_MTVEC 0x00001010 From patchwork Tue Dec 11 09:34:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010941 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="EPEH+sNP"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZpv1p8qz9s3l for ; Tue, 11 Dec 2018 20:47:03 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E6514C225F7; Tue, 11 Dec 2018 09:35:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3265DC226AF; Tue, 11 Dec 2018 09:31:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 47DD6C226DE; Tue, 11 Dec 2018 09:30:26 +0000 (UTC) Received: from mail-pl1-f196.google.com (mail-pl1-f196.google.com [209.85.214.196]) by lists.denx.de (Postfix) with ESMTPS id A4086C223C3 for ; Tue, 11 Dec 2018 09:30:22 +0000 (UTC) Received: by mail-pl1-f196.google.com with SMTP id y1so6654857plp.9 for ; Tue, 11 Dec 2018 01:30:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=lunPt6wl7PJS4dk8mpxPBK5mTf8u79/zpg9Ec+u84Ks=; b=EPEH+sNPeApusq1/fq/ACDfivcRhSVc1zg4gcdh0iJCIEnviixKGjRQsAle6KcYYS9 NKmMGO7y92CUq/WV1xsCb7QYOizoTHSYEjcEJjtt/3Yk/JGdkbrIkSoohzB+wss6/Sx6 CMpClTTgpQmJU7YMlRjCA6RH8s8D/yox4BGCsKjKvxLnniFSViT8WcbJyoqcZAVxJ9lV m7TdIK+olcb5QIEct+R2zk3AbH3x31+XJ9/yaVAOWcgXoGNLrVru/CYtt7qb1ukRQVpr uTg8ibk9ZcpqnQnyAOncF024ETVfEwYm8bLoEMCRUTiDhCs7MJzVNTm8Kyk+HsNY0tdJ +pXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=lunPt6wl7PJS4dk8mpxPBK5mTf8u79/zpg9Ec+u84Ks=; b=ke/gU/BORi4XX3NDr8M3C+2Lb8VMp3JvIVMFu6dCxq2yLHISubu9vxKexc8p8SxBeh biXBuzyZcQ99N+SiTAK41RMh89X/o2PZ3GAm+ha13ogUTvvR3EWLaRrEQhGBT0GKtObT AHCyM4q2JBO3FtqtNL6dERHipyy6Dk0eUMzL17cLKH9HFaFWxQEVDlViPtnwh9zrcR88 74cmuQiGNuUN8t2a6aL/CnLYEwU47e19nuWgbCO0pdHvwv+QgF9q1AMhQIODichTn/zf aPzG6027fAds3SXVq+Uh+Zwn92t28/7YYZPFTXBASWkidH7+9bUMepzdwbUE8dSMlwoD SiSQ== X-Gm-Message-State: AA+aEWb198bCoWWDQ1/BeDLBjZFe8UTZ4bAk1L6P2M0tyj2znoAhd8UJ oWQYNR2BfXOa16dy32Z8ekI= X-Google-Smtp-Source: AFSGD/XK76aaSDCdcuQwTjLQBr+0KWpY60cOGdUlxRnrASg/x72ot/Wm/5pc7pVP8HDNtoROCtx7Qw== X-Received: by 2002:a17:902:7687:: with SMTP id m7mr2431966pll.187.1544520621345; Tue, 11 Dec 2018 01:30:21 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.20 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:20 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:52 -0800 Message-Id: <1544520901-31558-17-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 16/25] riscv: Update supports_extension() to use desc from cpu driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This updates supports_extension() implementation to use the desc string from the cpu driver whenever possible, which avoids the reading of misa CSR for S-mode U-Boot. Signed-off-by: Bin Meng --- Changes in v3: - new patch to update supports_extension() to use desc from cpu driver Changes in v2: None arch/riscv/cpu/cpu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index d3c59da..704ae70 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -5,8 +5,10 @@ #include #include +#include #include #include +#include /* * prior_stage_fdt_address must be stored in the data section since it is used @@ -16,7 +18,21 @@ phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); static inline bool supports_extension(char ext) { +#ifdef CONFIG_CPU + struct udevice *dev; + char desc[32]; + + uclass_find_first_device(UCLASS_CPU, &dev); + if (!cpu_get_desc(dev, desc, sizeof(desc))) { + /* skip the first 4 characters (rv32|rv64) */ + if (strchr(desc + 4, ext)) + return true; + } + + return false; +#else return csr_read(misa) & (1 << (ext - 'a')); +#endif } static int riscv_cpu_probe(void) From patchwork Tue Dec 11 09:34:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010923 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Ka6IXKB8"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZbB2VlZz9s0t for ; Tue, 11 Dec 2018 20:36:54 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id EDC65C223CA; Tue, 11 Dec 2018 09:35:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E1D57C22126; Tue, 11 Dec 2018 09:31:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 84653C224D5; Tue, 11 Dec 2018 09:30:28 +0000 (UTC) Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) by lists.denx.de (Postfix) with ESMTPS id EBBC2C2251C for ; Tue, 11 Dec 2018 09:30:23 +0000 (UTC) Received: by mail-pf1-f195.google.com with SMTP id 64so6843201pfr.9 for ; Tue, 11 Dec 2018 01:30:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=I8lERN5kDdEyJ6b7pq7bKgFLoaOeBiuSbg+rG8Lx7Ak=; b=Ka6IXKB8dV7KqHkWl19Pfi0t/OHCXDOiJgVaCffDgyurlIAPXgzLUZi3jfIvrvUwCO CoyzxCkLlPT2ykWuU8EfzlLjInoqQlWUc1GUoAdC+aaffSfnQc/2BO6Gzz1b8TrIeh13 XeEH2QZI2BIAGJh75IV/HIm4JQpW4iUvdqll6hCbslkYSTHyVajaEPuzMQ86XQB5BIFN BWkFY65jAgFIC71aOXSICsLXPcDRJ8k+AdkyUCmh5iB2IM6qQpCKhSSbOsTlh1i4Ll+T w36h9xE+Bd79UBm0WhlZ0USYfaCu8QNEjf55Sg3nh5TX9Q2wfMkBFl86ijK33ok37ZJ6 1Lcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=I8lERN5kDdEyJ6b7pq7bKgFLoaOeBiuSbg+rG8Lx7Ak=; b=UYWfWQ+eGyFhIzutPUhkgglSEmRDLDztsXnLrTOu+NzhiYWsFJmtnC378lcD2zhwCj I0Bhi8spKshUMDV2ll+6sc8nphq//AvCEenJF8U4AnMu7z54ApkRf33UpnrSPz71SuWj zDsCJyEGj6yPJm+zHILNPcyKkUyKEfeo3MpXBYKPjGHy7TICS/XbY60WtprKosfluzx+ 7yPc6V1UgKuDGj2IdB06Yw4a5BL4QLG3MCXKwMwJNqSF/v0KJQTxbnZy5JaYiUYqAYA5 F/vL9nSArsvbNEWLukX+TnWJwyX140CCaYz0QG2lHcwNtKmO6wHaHLA/d0tYQK+NzrU0 zKXQ== X-Gm-Message-State: AA+aEWbN4Mb+4y7dhbU3Ir/H8NKcrCo9DGS5BazYBrp1WLkLuS7Ve6Ny LN+kFw6c37G/i6mo0pKdEkcDUKBn X-Google-Smtp-Source: AFSGD/XGr5vQ2O8MmweKMvir/Fw/pfCjQgb8ihwhzCmp8OlYkkl3vJ/twaWddJdW6SnWDWKDEH4uGw== X-Received: by 2002:a62:2702:: with SMTP id n2mr16036501pfn.29.1544520622621; Tue, 11 Dec 2018 01:30:22 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.21 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:22 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:53 -0800 Message-Id: <1544520901-31558-18-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 17/25] riscv: Add indirect stringification to csr_xxx ops X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" With current csr_xxx ops, we cannot pass a macro to parameter 'csr', hence we need add another level to allow the parameter to be a macro itself, aka indirect stringification. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: - new patch to add indirect stringification to csr_xxx ops arch/riscv/include/asm/csr.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 29624fd..86136f5 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -61,10 +61,12 @@ #ifndef __ASSEMBLY__ +#define xcsr(csr) #csr + #define csr_swap(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -73,7 +75,7 @@ #define csr_read(csr) \ ({ \ register unsigned long __v; \ - __asm__ __volatile__ ("csrr %0, " #csr \ + __asm__ __volatile__ ("csrr %0, " xcsr(csr) \ : "=r" (__v) : \ : "memory"); \ __v; \ @@ -82,7 +84,7 @@ #define csr_write(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrw " #csr ", %0" \ + __asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -90,7 +92,7 @@ #define csr_read_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -99,7 +101,7 @@ #define csr_set(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrs " #csr ", %0" \ + __asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) @@ -107,7 +109,7 @@ #define csr_read_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ + __asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \ : "=r" (__v) : "rK" (__v) \ : "memory"); \ __v; \ @@ -116,7 +118,7 @@ #define csr_clear(csr, val) \ ({ \ unsigned long __v = (unsigned long)(val); \ - __asm__ __volatile__ ("csrc " #csr ", %0" \ + __asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \ : : "rK" (__v) \ : "memory"); \ }) From patchwork Tue Dec 11 09:34:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010940 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="E9dxZH6t"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZpn4hjxz9s3l for ; Tue, 11 Dec 2018 20:46:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5910CC226F4; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.22 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:23 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:54 -0800 Message-Id: <1544520901-31558-19-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 18/25] riscv: Do some basic architecture level cpu initialization X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In arch_cpu_init_dm() do some basic architecture level cpu initialization, like FPU enable, etc. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - only initialize mcounteren CSR for S-mode - only touch satp in M-mode U-Boot - move the implementation to arch_cpu_init_dm() Changes in v2: - use csr_set() to set MSTATUS_FS - only enabling the cycle, time, and instret counters - change to use satp arch/riscv/cpu/cpu.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 704ae70..2196b14 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include /* @@ -51,7 +52,31 @@ static int riscv_cpu_probe(void) int arch_cpu_init_dm(void) { - return riscv_cpu_probe(); + int ret; + + ret = riscv_cpu_probe(); + if (ret) + return ret; + + /* Enable FPU */ + if (supports_extension('d') || supports_extension('f')) { + csr_set(MODE_PREFIX(status), MSTATUS_FS); + csr_write(fcsr, 0); + } + + if (CONFIG_IS_ENABLED(RISCV_MMODE)) { + /* + * Enable perf counters for cycle, time, + * and instret counters only + */ + csr_write(mcounteren, GENMASK(2, 0)); + + /* Disable paging */ + if (supports_extension('s')) + csr_write(satp, 0); + } + + return 0; } int arch_early_init_r(void) From patchwork Tue Dec 11 09:34:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010926 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.23 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:24 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:55 -0800 Message-Id: <1544520901-31558-20-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 19/25] riscv: Move trap handler codes to mtrap.S X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/cpu/Makefile | 2 +- arch/riscv/cpu/mtrap.S | 111 ++++++++++++++++++++++++++++++++++++++++++++++++ arch/riscv/cpu/start.S | 89 -------------------------------------- 3 files changed, 112 insertions(+), 90 deletions(-) create mode 100644 arch/riscv/cpu/mtrap.S diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile index 2cc6757..6bf6f91 100644 --- a/arch/riscv/cpu/Makefile +++ b/arch/riscv/cpu/Makefile @@ -4,4 +4,4 @@ extra-y = start.o -obj-y += cpu.o +obj-y += cpu.o mtrap.o diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S new file mode 100644 index 0000000..a5ad558 --- /dev/null +++ b/arch/riscv/cpu/mtrap.S @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * M-mode Trap Handler Code for RISC-V Core + * + * Copyright (c) 2017 Microsemi Corporation. + * Copyright (c) 2017 Padmarao Begari + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + * + * Copyright (C) 2018, Bin Meng + */ + +#include +#include + +#ifdef CONFIG_32BIT +#define LREG lw +#define SREG sw +#define REGBYTES 4 +#else +#define LREG ld +#define SREG sd +#define REGBYTES 8 +#endif + + .text + + /* trap entry */ + .align 2 + .global trap_entry +trap_entry: + addi sp, sp, -32 * REGBYTES + SREG x1, 1 * REGBYTES(sp) + SREG x2, 2 * REGBYTES(sp) + SREG x3, 3 * REGBYTES(sp) + SREG x4, 4 * REGBYTES(sp) + SREG x5, 5 * REGBYTES(sp) + SREG x6, 6 * REGBYTES(sp) + SREG x7, 7 * REGBYTES(sp) + SREG x8, 8 * REGBYTES(sp) + SREG x9, 9 * REGBYTES(sp) + SREG x10, 10 * REGBYTES(sp) + SREG x11, 11 * REGBYTES(sp) + SREG x12, 12 * REGBYTES(sp) + SREG x13, 13 * REGBYTES(sp) + SREG x14, 14 * REGBYTES(sp) + SREG x15, 15 * REGBYTES(sp) + SREG x16, 16 * REGBYTES(sp) + SREG x17, 17 * REGBYTES(sp) + SREG x18, 18 * REGBYTES(sp) + SREG x19, 19 * REGBYTES(sp) + SREG x20, 20 * REGBYTES(sp) + SREG x21, 21 * REGBYTES(sp) + SREG x22, 22 * REGBYTES(sp) + SREG x23, 23 * REGBYTES(sp) + SREG x24, 24 * REGBYTES(sp) + SREG x25, 25 * REGBYTES(sp) + SREG x26, 26 * REGBYTES(sp) + SREG x27, 27 * REGBYTES(sp) + SREG x28, 28 * REGBYTES(sp) + SREG x29, 29 * REGBYTES(sp) + SREG x30, 30 * REGBYTES(sp) + SREG x31, 31 * REGBYTES(sp) + csrr a0, MODE_PREFIX(cause) + csrr a1, MODE_PREFIX(epc) + mv a2, sp + jal handle_trap + csrw MODE_PREFIX(epc), a0 + +#ifdef CONFIG_RISCV_SMODE + /* Remain in S-mode after sret */ + li t0, SSTATUS_SPP +#else + /* Remain in M-mode after mret */ + li t0, MSTATUS_MPP +#endif + csrs MODE_PREFIX(status), t0 + LREG x1, 1 * REGBYTES(sp) + LREG x2, 2 * REGBYTES(sp) + LREG x3, 3 * REGBYTES(sp) + LREG x4, 4 * REGBYTES(sp) + LREG x5, 5 * REGBYTES(sp) + LREG x6, 6 * REGBYTES(sp) + LREG x7, 7 * REGBYTES(sp) + LREG x8, 8 * REGBYTES(sp) + LREG x9, 9 * REGBYTES(sp) + LREG x10, 10 * REGBYTES(sp) + LREG x11, 11 * REGBYTES(sp) + LREG x12, 12 * REGBYTES(sp) + LREG x13, 13 * REGBYTES(sp) + LREG x14, 14 * REGBYTES(sp) + LREG x15, 15 * REGBYTES(sp) + LREG x16, 16 * REGBYTES(sp) + LREG x17, 17 * REGBYTES(sp) + LREG x18, 18 * REGBYTES(sp) + LREG x19, 19 * REGBYTES(sp) + LREG x20, 20 * REGBYTES(sp) + LREG x21, 21 * REGBYTES(sp) + LREG x22, 22 * REGBYTES(sp) + LREG x23, 23 * REGBYTES(sp) + LREG x24, 24 * REGBYTES(sp) + LREG x25, 25 * REGBYTES(sp) + LREG x26, 26 * REGBYTES(sp) + LREG x27, 27 * REGBYTES(sp) + LREG x28, 28 * REGBYTES(sp) + LREG x29, 29 * REGBYTES(sp) + LREG x30, 30 * REGBYTES(sp) + LREG x31, 31 * REGBYTES(sp) + addi sp, sp, 32 * REGBYTES + MODE_PREFIX(ret) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 64246a4..47c3bf0 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -198,92 +198,3 @@ call_board_init_r: * jump to it ... */ jr t4 /* jump to board_init_r() */ - -/* - * trap entry - */ -.align 2 -trap_entry: - addi sp, sp, -32*REGBYTES - SREG x1, 1*REGBYTES(sp) - SREG x2, 2*REGBYTES(sp) - SREG x3, 3*REGBYTES(sp) - SREG x4, 4*REGBYTES(sp) - SREG x5, 5*REGBYTES(sp) - SREG x6, 6*REGBYTES(sp) - SREG x7, 7*REGBYTES(sp) - SREG x8, 8*REGBYTES(sp) - SREG x9, 9*REGBYTES(sp) - SREG x10, 10*REGBYTES(sp) - SREG x11, 11*REGBYTES(sp) - SREG x12, 12*REGBYTES(sp) - SREG x13, 13*REGBYTES(sp) - SREG x14, 14*REGBYTES(sp) - SREG x15, 15*REGBYTES(sp) - SREG x16, 16*REGBYTES(sp) - SREG x17, 17*REGBYTES(sp) - SREG x18, 18*REGBYTES(sp) - SREG x19, 19*REGBYTES(sp) - SREG x20, 20*REGBYTES(sp) - SREG x21, 21*REGBYTES(sp) - SREG x22, 22*REGBYTES(sp) - SREG x23, 23*REGBYTES(sp) - SREG x24, 24*REGBYTES(sp) - SREG x25, 25*REGBYTES(sp) - SREG x26, 26*REGBYTES(sp) - SREG x27, 27*REGBYTES(sp) - SREG x28, 28*REGBYTES(sp) - SREG x29, 29*REGBYTES(sp) - SREG x30, 30*REGBYTES(sp) - SREG x31, 31*REGBYTES(sp) - csrr a0, MODE_PREFIX(cause) - csrr a1, MODE_PREFIX(epc) - mv a2, sp - jal handle_trap - csrw MODE_PREFIX(epc), a0 - -#ifdef CONFIG_RISCV_SMODE -/* - * Remain in S-mode after sret - */ - li t0, SSTATUS_SPP -#else -/* - * Remain in M-mode after mret - */ - li t0, MSTATUS_MPP -#endif - csrs MODE_PREFIX(status), t0 - LREG x1, 1*REGBYTES(sp) - LREG x2, 2*REGBYTES(sp) - LREG x3, 3*REGBYTES(sp) - LREG x4, 4*REGBYTES(sp) - LREG x5, 5*REGBYTES(sp) - LREG x6, 6*REGBYTES(sp) - LREG x7, 7*REGBYTES(sp) - LREG x8, 8*REGBYTES(sp) - LREG x9, 9*REGBYTES(sp) - LREG x10, 10*REGBYTES(sp) - LREG x11, 11*REGBYTES(sp) - LREG x12, 12*REGBYTES(sp) - LREG x13, 13*REGBYTES(sp) - LREG x14, 14*REGBYTES(sp) - LREG x15, 15*REGBYTES(sp) - LREG x16, 16*REGBYTES(sp) - LREG x17, 17*REGBYTES(sp) - LREG x18, 18*REGBYTES(sp) - LREG x19, 19*REGBYTES(sp) - LREG x20, 20*REGBYTES(sp) - LREG x21, 21*REGBYTES(sp) - LREG x22, 22*REGBYTES(sp) - LREG x23, 23*REGBYTES(sp) - LREG x24, 24*REGBYTES(sp) - LREG x25, 25*REGBYTES(sp) - LREG x26, 26*REGBYTES(sp) - LREG x27, 27*REGBYTES(sp) - LREG x28, 28*REGBYTES(sp) - LREG x29, 29*REGBYTES(sp) - LREG x30, 30*REGBYTES(sp) - LREG x31, 31*REGBYTES(sp) - addi sp, sp, 32*REGBYTES - MODE_PREFIX(ret) From patchwork Tue Dec 11 09:34:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010933 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="M9njK5MM"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZhk01lwz9s8r for ; Tue, 11 Dec 2018 20:41:41 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id AC2E3C22130; Tue, 11 Dec 2018 09:37:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1FC36C22817; Tue, 11 Dec 2018 09:31:32 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C8D27C2280E; Tue, 11 Dec 2018 09:30:31 +0000 (UTC) Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) by lists.denx.de (Postfix) with ESMTPS id 0EF06C221A9 for ; Tue, 11 Dec 2018 09:30:27 +0000 (UTC) Received: by mail-pg1-f182.google.com with SMTP id n2so6375779pgm.3 for ; Tue, 11 Dec 2018 01:30:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=cyM5TPv6l35zbdXNYjjlZaNJCxWCZSNVOLpajzDImOU=; b=M9njK5MMAF5YQKs87k6IVUVR14wZsfjefZrLWJIW8JfMb2CfEYyCM7vjtmf4C/yUsb +bK+BcZltTmHSfpYYYleOeXxnfkBd/dGEuvjHPg9jfNqrkdFtJ3YQeH5eQzew8gayzA5 Zicblxp783MdxviWHu48Ej97Rd49wRGNJ6YCvYr3s3TFDe6xnWZtRQYfXm1A5OWHwDr2 oeb7Vx1OX9vc3bkhiLnGUb1Bt9slPGJqc57B64/N1yMwQKyvaRTH9BqDXhbqCpa7ROq3 kzpFlqtZDJ5yGCwCN5494dPvQbxJko6xyo23R53msc+YsKUonZwH8LMR2PiO1BhBSrel qKAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=cyM5TPv6l35zbdXNYjjlZaNJCxWCZSNVOLpajzDImOU=; b=M2DlU2B8mHt8ehwMhpKmSIhF7AAQnydhBj4Cqnrz5PCo2XXPgAwq/+86wQ4r64e2gQ yl6QAy90CjoBub4dyGGVRQdfvTuPDhRtcBVvy2AwyTcnFmFFV6kcv9w8AKAF4SZDrOnp 9y4u102c1lrvKiXPoGKNqzG2DMFEKshYgV95Db3YSARs7XORipj/H7GaZ6zBe4ViZoPR m0xUu/FIZSEpQY64HTZX57TTraCreg+rwJHnd4o/13/ngObcskWvBTIJyuD/KxnrmnOS O9BSF3DrSKflJpjPT1lZbxkRaLEs4yMZEcJLBsBxt59bmDqFqUr1m0gEsL91Wh397m1C CgUg== X-Gm-Message-State: AA+aEWbS4zWKSNrBY4B27O8RwslQ9la54J/CKdwGxfyjedJSX+gZqyCR zqGuQUrh6wb8cpgJ9bvEWHU= X-Google-Smtp-Source: AFSGD/XGByXm5yRqfB4m2hTuo3nxMorVofhApHfWmjYFMnkQYvMs9lkbdOMx3QK2fS0vYN0i4AOtig== X-Received: by 2002:a63:ed42:: with SMTP id m2mr13927926pgk.147.1544520625738; Tue, 11 Dec 2018 01:30:25 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.24 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:25 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:56 -0800 Message-Id: <1544520901-31558-21-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 20/25] riscv: Fix context restore before returning from trap handler X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" sp cannot be loaded before restoring other registers. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/cpu/mtrap.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index a5ad558..da307e4 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -77,7 +77,6 @@ trap_entry: #endif csrs MODE_PREFIX(status), t0 LREG x1, 1 * REGBYTES(sp) - LREG x2, 2 * REGBYTES(sp) LREG x3, 3 * REGBYTES(sp) LREG x4, 4 * REGBYTES(sp) LREG x5, 5 * REGBYTES(sp) @@ -107,5 +106,6 @@ trap_entry: LREG x29, 29 * REGBYTES(sp) LREG x30, 30 * REGBYTES(sp) LREG x31, 31 * REGBYTES(sp) + LREG x2, 2 * REGBYTES(sp) addi sp, sp, 32 * REGBYTES MODE_PREFIX(ret) From patchwork Tue Dec 11 09:34:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010935 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tYAGcEzy"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZk22fTsz9s3l for ; Tue, 11 Dec 2018 20:42:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D8E27C22655; Tue, 11 Dec 2018 09:34:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DA40BC22547; Tue, 11 Dec 2018 09:31:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 54375C226CD; Tue, 11 Dec 2018 09:30:32 +0000 (UTC) Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) by lists.denx.de (Postfix) with ESMTPS id 47000C22634 for ; Tue, 11 Dec 2018 09:30:28 +0000 (UTC) Received: by mail-pg1-f195.google.com with SMTP id w6so6370740pgl.6 for ; Tue, 11 Dec 2018 01:30:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=4abFoezZyVAlzGulsXo2VTuL3Kmp+xp50fH+seiddbw=; b=tYAGcEzy7HcAXg6ks9udLnSY32fEzxjQ2+ECXm2o0uip+WSQ6AbsqD2oyphO0jXdEx zWM2/wl1AOXE4uQ/KvCJi3KUOyYaOgkwXtQJDRUrNeWWT+Eh5jn50bZZ2jdW8z0KTuoW E7kHA4ldFY3VzW0/QC9QD7gYggH2VEfpCk5XbE9f5xfEDXY1iJO2/yqoSeNAqOdqxJSI BBVEiej2eCHc/21eOJPLSB/ixmp1sknR1kg8LRhYjuKnaDCc/445HEZ/LDNI4UGYpTvi 2axmVp31TyoDpY3rXSSa1Qwhpie09K9K5AoETicn376vP2Py9cdq6bBKdqgtdx/dA1wX k4Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=4abFoezZyVAlzGulsXo2VTuL3Kmp+xp50fH+seiddbw=; b=TYUCQJFV7oiN/JRQTHy1B9VSw8+VVL3ACGt+KnX4NxAelHZ0UcC6GaTC/V5ENxHw2b HrFT9EvzjoW2gvIsdGGo5z7V5L2Bv0xfSCCOyTR3Bv9PdTB2Kk0CvWiQgl3eyU/CluNR +DtUrdiDoEP8pHFKbbRpPKLr3mC1Sqf7t1pDo8kTOSXB9I9s9meurGXdqxaUhNYGj2Mg JXKWNUG+JGDRjtdZja69iT2WiT7MtUtyVDXCPP23ngu1HveYgXNjOeYJoCn7R7VgOKK2 IGQMTBj3TZ6nErZFP7N3CsDFNN1Lrz/FZGBZfMGHTgJ5zuw0GCNBjljPitinySTKFTAK BteQ== X-Gm-Message-State: AA+aEWYUx2s3XwlmAJ2mkNcy00JR0shE6p/qPE8e4CdYzDAJmKJhZN+/ MYmzOMaCe7y64LX/LukmNog= X-Google-Smtp-Source: AFSGD/XnLqGSRnhyeePNo8W7dWThm9UKBjUnUJXgvYhsB77xMI/rtozUvPRbacON55GUZOopQVaYQA== X-Received: by 2002:a62:345:: with SMTP id 66mr15529973pfd.189.1544520626974; Tue, 11 Dec 2018 01:30:26 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.25 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:26 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:57 -0800 Message-Id: <1544520901-31558-22-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 21/25] riscv: Return to previous privilege level after trap handling X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present the trap handler returns to M-mode only. Change to returning to previous privilege level instead. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: None arch/riscv/cpu/mtrap.S | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index da307e4..407ecfa 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -68,14 +68,6 @@ trap_entry: jal handle_trap csrw MODE_PREFIX(epc), a0 -#ifdef CONFIG_RISCV_SMODE - /* Remain in S-mode after sret */ - li t0, SSTATUS_SPP -#else - /* Remain in M-mode after mret */ - li t0, MSTATUS_MPP -#endif - csrs MODE_PREFIX(status), t0 LREG x1, 1 * REGBYTES(sp) LREG x3, 3 * REGBYTES(sp) LREG x4, 4 * REGBYTES(sp) From patchwork Tue Dec 11 09:34:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010924 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="qpdh+IvQ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZbm5ccTz9s0t for ; Tue, 11 Dec 2018 20:37:24 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6322DC22483; Tue, 11 Dec 2018 09:33:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7892AC225F7; Tue, 11 Dec 2018 09:30:47 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3BADFC2246D; Tue, 11 Dec 2018 09:30:34 +0000 (UTC) Received: from mail-pg1-f194.google.com (mail-pg1-f194.google.com [209.85.215.194]) by lists.denx.de (Postfix) with ESMTPS id DD164C22172 for ; Tue, 11 Dec 2018 09:30:29 +0000 (UTC) Received: by mail-pg1-f194.google.com with SMTP id d72so6371626pga.9 for ; Tue, 11 Dec 2018 01:30:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=huYSz/3CpAOKnakko+sdlGgaLotexcclv7dCVwOwT4E=; b=qpdh+IvQY8xajXQwQk4EC6ZCvvFHnJFZnouCjFpWZNjyUX/ukwZ4BX+eK76nINkcit SUU2gjXfxYkjjpnbLfFYNhpabaYpOlakHa1Q5rffuEgvsnA6PuE2PtVgjIgYhmDz7pK7 Fl31PWNrUxh+QEeSIisg+wt3k/zKjLJjvBcw2AaZA2k9vCMXK2A9Uqjk+wx30FAS0Xz0 dgl7nHRnfrSNuDNWlCNJ8Delg8gVkn/wv9v2UrpfrQ4WdIPge2X+cICaYn8I0VATNAE5 DH/d1c/O9MJk7MvbQBkpenDJK89OIvlhXVNQONlxpepynmXudjhB71z0wv9qa8jbgiNW sAYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=huYSz/3CpAOKnakko+sdlGgaLotexcclv7dCVwOwT4E=; b=FJNBOMwnMFOtvCvUS+k8qLrue/yqXUmiipldgZi1qY2LCNJLyJWDGmp9lwsda4jPHC PYszVDSMGVjJtLeGGmJyHpmkpQ71jZIy7UV3BhUJQt9LdD4Y4f6fH6GN4+HSwbOr4GMc N5tC1D8lMYtjmIn1avBRLC9YjVlEy81ohRUHvftS+BkHie7x+7UJN7yDyiWQX9yq8bRJ T+UvqWFcKxHIsiYVo/aRHV3rMFAqxNIXi283/uY+yMA8LcMlvlf646XkyjwKzhiqAkQc WWbeNAYXa/A3IskYjVxKvK3uXbZUoo9eyxwVX9bgzEFTq5vF6jK8j3U8KnaWJ4upXKns ntvQ== X-Gm-Message-State: AA+aEWYbgBRxJWvNJUAhGx61/e+8gMYcvb20DE9h7oXymcwP1SnYoc9Y nxCw+KO1O9VBwJAPDG1kL18= X-Google-Smtp-Source: AFSGD/Uugl/V4KxF3bLl4DofIzKOBOK5xZ5K8FoTB9Eoiz3iBg7MRQl4DXqqofszD6VxS3g+lxFg9g== X-Received: by 2002:a63:e516:: with SMTP id r22mr14230353pgh.256.1544520628548; Tue, 11 Dec 2018 01:30:28 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.27 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:27 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:58 -0800 Message-Id: <1544520901-31558-23-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 22/25] riscv: Adjust the _exit_trap() position to come before handle_trap() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" With this change, we can avoid a forward declaration. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: None Changes in v2: - rebase on u-boot/master - drop the patch "riscv: Pass correct exception code to _exit_trap()" - drop the patch "riscv: Refactor handle_trap() a little for future extension" - drop the patch "riscv: Allow U-Boot to run on hart 0 only", and leave the SMP support to Lukas's future patch series arch/riscv/lib/interrupts.c | 62 ++++++++++++++++++++++----------------------- 1 file changed, 30 insertions(+), 32 deletions(-) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 3aff006..e185933 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -12,7 +12,36 @@ #include #include -static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs); +static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) +{ + static const char * const exception_code[] = { + "Instruction address misaligned", + "Instruction access fault", + "Illegal instruction", + "Breakpoint", + "Load address misaligned", + "Load access fault", + "Store/AMO address misaligned", + "Store/AMO access fault", + "Environment call from U-mode", + "Environment call from S-mode", + "Reserved", + "Environment call from M-mode", + "Instruction page fault", + "Load page fault", + "Reserved", + "Store/AMO page fault", + }; + + if (code < ARRAY_SIZE(exception_code)) { + printf("exception code: %ld , %s , epc %lx , ra %lx\n", + code, exception_code[code], epc, regs->ra); + } else { + printf("Reserved\n"); + } + + hang(); +} int interrupt_init(void) { @@ -72,34 +101,3 @@ __attribute__((weak)) void external_interrupt(struct pt_regs *regs) __attribute__((weak)) void timer_interrupt(struct pt_regs *regs) { } - -static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) -{ - static const char * const exception_code[] = { - "Instruction address misaligned", - "Instruction access fault", - "Illegal instruction", - "Breakpoint", - "Load address misaligned", - "Load access fault", - "Store/AMO address misaligned", - "Store/AMO access fault", - "Environment call from U-mode", - "Environment call from S-mode", - "Reserved", - "Environment call from M-mode", - "Instruction page fault", - "Load page fault", - "Reserved", - "Store/AMO page fault", - }; - - if (code < ARRAY_SIZE(exception_code)) { - printf("exception code: %ld , %s , epc %lx , ra %lx\n", - code, exception_code[code], epc, regs->ra); - } else { - printf("Reserved\n"); - } - - hang(); -} From patchwork Tue Dec 11 09:34:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010929 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MM7s7cqW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZg91Vc0z9s8r for ; Tue, 11 Dec 2018 20:40:21 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C4B3BC2267C; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.28 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:29 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:34:59 -0800 Message-Id: <1544520901-31558-24-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 23/25] riscv: Save boot hart id to the global data X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At present the hart id passed via a0 in the U-Boot entry is saved to s0 at the beginning but does not preserve later. Save it to the global data structure so that it can be used later. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - new patch to save boot hart id to the global data Changes in v2: None arch/riscv/cpu/start.S | 4 ++++ arch/riscv/include/asm/global_data.h | 1 + arch/riscv/lib/asm-offsets.c | 19 +++++++++++++++++++ 3 files changed, 24 insertions(+) create mode 100644 arch/riscv/lib/asm-offsets.c diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 47c3bf0..81ea52b 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -14,6 +14,7 @@ #include #include #include +#include #ifdef CONFIG_32BIT #define LREG lw @@ -70,6 +71,9 @@ call_board_init_f_0: jal board_init_f_init_reserve + /* save the boot hart id to global_data */ + SREG s0, GD_BOOT_HART(gp) + mv a0, zero /* a0 <-- boot_flags = 0 */ la t5, board_init_f jr t5 /* jump to board_init_f() */ diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 46fcfab..a3a342c 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -12,6 +12,7 @@ /* Architecture-specific global data */ struct arch_global_data { + long boot_hart; /* boot hart id */ #ifdef CONFIG_SIFIVE_CLINT void __iomem *clint; /* clint base address */ #endif diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c new file mode 100644 index 0000000..e0b71f5 --- /dev/null +++ b/arch/riscv/lib/asm-offsets.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + * + * From arch/x86/lib/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + */ + +#include +#include + +int main(void) +{ + DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); + + return 0; +} From patchwork Tue Dec 11 09:35:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010936 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; 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[147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.29 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:30 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:35:00 -0800 Message-Id: <1544520901-31558-25-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 24/25] riscv: bootm: Change to use boot_hart from global data X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Avoid reading mhartid CSR directly, instead use the one we saved in the global data structure before. With this patch, BBL no longer needs to be hacked to provide the mhartid CSR emulation for S-mode U-Boot. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - new patch to change to use boot_hart from global data Changes in v2: None arch/riscv/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 124aeef..60b32cc 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -93,7 +93,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) if (!fake) { if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) - kernel(csr_read(mhartid), images->ft_addr); + kernel(gd->arch.boot_hart, images->ft_addr); } } From patchwork Tue Dec 11 09:35:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1010942 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="vAGeHB7d"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43DZpz37srz9s3l for ; Tue, 11 Dec 2018 20:47:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 17270C226AF; Tue, 11 Dec 2018 09:36:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9B7F5C227FC; Tue, 11 Dec 2018 09:31:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8CB90C227E8; Tue, 11 Dec 2018 09:30:38 +0000 (UTC) Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) by lists.denx.de (Postfix) with ESMTPS id F369EC225E2 for ; Tue, 11 Dec 2018 09:30:32 +0000 (UTC) Received: by mail-pf1-f182.google.com with SMTP id q1so6851455pfi.5 for ; Tue, 11 Dec 2018 01:30:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=fNhVy94x4w2BxfS18oYZk3CN5+cTePwafuMU+DfiFAY=; b=vAGeHB7dDPjpu2MSiBNZL4ElK6S5Lfd+O0EcQ9PRIjNwEWG6Z1pj3cUbkyyjFtHWpM BOhHT4++hwkcbD3zzBKdn0qcnapSGhSxDSvPH5EIcpKvFvkLjPZlyOG+u0dbUrLolQ2a J/abG/tCrLC56rVEFbdoDRYgLb+3nlr2SZrSrPhVqJhaH8uJ9SKD06XjadJbi+uu2GRT SmIvcDO2BRDX0LRx7doymueWqxgwE7UVMKme08fKMVjyHz9j8gvYsulayGFYJ5koyHiO QzKXRuAed6MbGBVmpgnzlsaEUugAC6EMx1yj3Sv6vLqvcis81BCUvYRbSq8X+bnOH0Gh dmzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=fNhVy94x4w2BxfS18oYZk3CN5+cTePwafuMU+DfiFAY=; b=SRC0QMRfGWM1lUdfPQnv8JbY52HUtcaboP/CW3P5i2EPGhnUKnfIpWJ1k+tWA4N7dX UDZdMNDyOQdwlmc70TWjZUUMSL2TVJjTfAfV9qn65EkEeaNsXG5E22Z8vP5Yv2ShFa1/ BPTQ38QIv2IsP1WPBLqEY9xHD8Akc6uulCylR5hjZY+jOJglgo2eIYeKKhLnuYIZrevD 1hnh8wb/ay/YmHtRxlUd7VRACWqVzXTlyeYn7g0l+N3MVU7Q5GplPCMgoJvEFkN+/vF/ s7BuMFfZMc4pKMug1FGE7Y0ApEynSzi6zXjKzFY+Z3ajH/o4QeeejP2GKtOPeBurnjxG Oz+A== X-Gm-Message-State: AA+aEWZGb4Uvm8YZLmVWeoKFHIEZFUhwCpRlbLriD5nD1892JeELqYvK LrDcaMO9ZXUXmAnjuVMqQQo= X-Google-Smtp-Source: AFSGD/Wrprzms1I5LXPbqIcnO8VGm1cZ7Y1xvah/ANpumI4kiZxQjZBYNhLfOFxVrLaDjhRbvTGZ/w== X-Received: by 2002:a63:8c0d:: with SMTP id m13mr14049631pgd.422.1544520631581; Tue, 11 Dec 2018 01:30:31 -0800 (PST) Received: from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com. [147.11.156.139]) by smtp.gmail.com with ESMTPSA id n66sm21916129pfk.19.2018.12.11.01.30.30 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Dec 2018 01:30:31 -0800 (PST) From: Bin Meng To: Rick Chen , Simon Glass , Lukas Auer , Anup Patel , U-Boot Mailing List Date: Tue, 11 Dec 2018 01:35:01 -0800 Message-Id: <1544520901-31558-26-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> References: <1544520901-31558-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH v3 25/25] riscv: Remove ae350.dts X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This is not used by any board. Remove it. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer --- Changes in v3: - new patch to remove ae350.dts Changes in v2: None arch/riscv/dts/ae350.dts | 229 ----------------------------------------------- 1 file changed, 229 deletions(-) delete mode 100644 arch/riscv/dts/ae350.dts diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts deleted file mode 100644 index e48c298..0000000 --- a/arch/riscv/dts/ae350.dts +++ /dev/null @@ -1,229 +0,0 @@ -/dts-v1/; - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "andestech,ax25"; - model = "andestech,ax25"; - - aliases { - uart0 = &serial0; - spi0 = &spi; - }; - - chosen { - bootargs = "console=ttyS0,38400n8 debug loglevel=7"; - stdout-path = "uart0:38400n8"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <60000000>; - CPU0: cpu@0 { - device_type = "cpu"; - reg = <0>; - status = "okay"; - compatible = "riscv"; - riscv,isa = "rv64imafdc"; - mmu-type = "riscv,sv39"; - clock-frequency = <60000000>; - d-cache-size = <0x8000>; - d-cache-line-size = <32>; - CPU0_intc: interrupt-controller { - #interrupt-cells = <1>; - interrupt-controller; - compatible = "riscv,cpu-intc"; - }; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x0 0x40000000>; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "andestech,riscv-ae350-soc"; - ranges; - - plic0: interrupt-controller@e4000000 { - compatible = "riscv,plic0"; - #address-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x0 0xe4000000 0x0 0x2000000>; - riscv,ndev=<71>; - interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; - }; - - plic1: interrupt-controller@e6400000 { - compatible = "riscv,plic1"; - #address-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0x0 0xe6400000 0x0 0x400000>; - riscv,ndev=<1>; - interrupts-extended = <&CPU0_intc 3>; - }; - - plmt0@e6000000 { - compatible = "riscv,plmt0"; - interrupts-extended = <&CPU0_intc 7>; - reg = <0x0 0xe6000000 0x0 0x100000>; - }; - }; - - spiclk: virt_100mhz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - - timer0: timer@f0400000 { - compatible = "andestech,atcpit100"; - reg = <0x0 0xf0400000 0x0 0x1000>; - clock-frequency = <60000000>; - interrupts = <3 4>; - interrupt-parent = <&plic0>; - }; - - serial0: serial@f0300000 { - compatible = "andestech,uart16550", "ns16550a"; - reg = <0x0 0xf0300000 0x0 0x1000>; - interrupts = <9 4>; - clock-frequency = <19660800>; - reg-shift = <2>; - reg-offset = <32>; - no-loopback-test = <1>; - interrupt-parent = <&plic0>; - }; - - mac0: mac@e0100000 { - compatible = "andestech,atmac100"; - reg = <0x0 0xe0100000 0x0 0x1000>; - interrupts = <19 4>; - interrupt-parent = <&plic0>; - }; - - mmc0: mmc@f0e00000 { - compatible = "andestech,atfsdc010"; - max-frequency = <100000000>; - clock-freq-min-max = <400000 100000000>; - fifo-depth = <0x10>; - reg = <0x0 0xf0e00000 0x0 0x1000>; - interrupts = <18 4>; - cap-sd-highspeed; - interrupt-parent = <&plic0>; - }; - - dma0: dma@f0c00000 { - compatible = "andestech,atcdmac300"; - reg = <0x0 0xf0c00000 0x0 0x1000>; - interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>; - dma-channels = <8>; - interrupt-parent = <&plic0>; - }; - - lcd0: lcd@e0200000 { - compatible = "andestech,atflcdc100"; - reg = <0x0 0xe0200000 0x0 0x1000>; - interrupts = <20 4>; - interrupt-parent = <&plic0>; - }; - - smc0: smc@e0400000 { - compatible = "andestech,atfsmc020"; - reg = <0x0 0xe0400000 0x0 0x1000>; - }; - - snd0: snd@f0d00000 { - compatible = "andestech,atfac97"; - reg = <0x0 0xf0d00000 0x0 0x1000>; - interrupts = <17 4>; - interrupt-parent = <&plic0>; - }; - - virtio_mmio@fe007000 { - interrupts = <0x17 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe007000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe006000 { - interrupts = <0x16 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe006000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe005000 { - interrupts = <0x15 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe005000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe004000 { - interrupts = <0x14 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe004000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe003000 { - interrupts = <0x13 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe003000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe002000 { - interrupts = <0x12 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe002000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe001000 { - interrupts = <0x11 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe001000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - virtio_mmio@fe000000 { - interrupts = <0x10 0x4>; - interrupt-parent = <0x2>; - reg = <0x0 0xfe000000 0x0 0x1000>; - compatible = "virtio,mmio"; - }; - - nor@0,0 { - compatible = "cfi-flash"; - reg = <0x0 0x88000000 0x0 0x1000>; - bank-width = <2>; - device-width = <1>; - }; - - spi: spi@f0b00000 { - compatible = "andestech,atcspi200"; - reg = <0x0 0xf0b00000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - clocks = <&spiclk>; - interrupts = <4 4>; - interrupt-parent = <&plic0>; - flash@0 { - compatible = "spi-flash"; - spi-max-frequency = <50000000>; - reg = <0>; - spi-cpol; - spi-cpha; - }; - }; -};