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X-Received-From: 2a00:1450:400c:c0c::229 Subject: [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Riku Voipio , qemu-devel@nongnu.org, Laurent Vivier , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Laurent Vivier --- linux-user/main.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/linux-user/main.c b/linux-user/main.c index 829f974662..5072aa855b 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3854,6 +3854,11 @@ static void handle_arg_log(const char *arg) qemu_set_log(mask); } +static void handle_arg_dfilter(const char *arg) +{ + qemu_set_dfilter_ranges(arg, NULL); +} + static void handle_arg_log_filename(const char *arg) { qemu_set_log_filename(arg, &error_fatal); @@ -4054,6 +4059,8 @@ static const struct qemu_argument arg_table[] = { {"d", "QEMU_LOG", true, handle_arg_log, "item[,...]", "enable logging of specified items " "(use '-d help' for a list of items)"}, + {"dfilter", "QEMU_DFILTER", true, handle_arg_dfilter, + "range[,...]","filter logging based on address range"}, {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename, "logfile", "write logs to 'logfile' (default stderr)"}, {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize, From patchwork Fri Oct 13 16:24:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825575 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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X-Received-From: 2a00:1450:400c:c0c::22e Subject: [Qemu-devel] [RFC PATCH 02/30] arm: introduce ARM_V8_FP16 feature bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 89d49cdcb2..3a0f27c782 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1340,6 +1340,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ + ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6e..973614dfc6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -226,6 +226,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ } From patchwork Fri Oct 13 16:24:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825578 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; 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Fri, 13 Oct 2017 17:24:38 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:11 +0100 Message-Id: <20171013162438.32458-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::229 Subject: [Qemu-devel] [RFC PATCH 03/30] include/exec/helper-head.h: support f16 in helper calls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Peter Crosthwaite , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This allows us to explicitly pass float16 to helpers rather than assuming uint32_t and dealing with the result. Of course they will be passed in i32 sized registers by default. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- include/exec/helper-head.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index 1cfc43b9ff..fdb82151d3 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -30,6 +30,7 @@ #define dh_alias_int i32 #define dh_alias_i64 i64 #define dh_alias_s64 i64 +#define dh_alias_f16 i32 #define dh_alias_f32 i32 #define dh_alias_f64 i64 #define dh_alias_ptr ptr @@ -42,6 +43,7 @@ #define dh_ctype_int int #define dh_ctype_i64 uint64_t #define dh_ctype_s64 int64_t +#define dh_ctype_f16 float16 #define dh_ctype_f32 float32 #define dh_ctype_f64 float64 #define dh_ctype_ptr void * @@ -98,6 +100,7 @@ #define dh_is_signed_s32 1 #define dh_is_signed_i64 0 #define dh_is_signed_s64 1 +#define dh_is_signed_f16 0 #define dh_is_signed_f32 0 #define dh_is_signed_f64 0 #define dh_is_signed_tl 0 From patchwork Fri Oct 13 16:24:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825574 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="SUqz/46b"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDCkQ0rzvz9sRm for ; Sat, 14 Oct 2017 03:25:34 +1100 (AEDT) Received: from localhost ([::1]:51017 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32mC-0002S7-5T for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:25:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41604) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32lS-0002Pc-Lx for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32lR-0006Ul-4A for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:46 -0400 Received: from mail-wr0-x232.google.com ([2a00:1450:400c:c0c::232]:44335) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32lQ-0006Tu-T2 for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:45 -0400 Received: by mail-wr0-x232.google.com with SMTP id l24so1420968wre.1 for ; Fri, 13 Oct 2017 09:24:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U/1sagJWWnbpr+LHtke20CA0+z5ItCTw37KNEr04Ng8=; b=SUqz/46bnTxPL/7OTHNpdxoRqyCARIXxWqrgTLNUBIbEx5CwfD3OBAQ1w+7IWTRcLv 6A4KL7UuUdQarCqcTMyEqV+vVCPrFE98sZFUx8aCZA7PQVvD3pdUQ0JOxX035kovfhy9 c0K8M2i5pmKMNceysswZ9rp8WrHOWRu7z5/mY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U/1sagJWWnbpr+LHtke20CA0+z5ItCTw37KNEr04Ng8=; b=q+ePm1vq9ZpBm6DlX69IBN7uvyU35MrVavlIkOLtOdb44JgqnEIzY1U01pKnqM+EVa e/B4+cIXXZ5P+pXKyUnXDGD6+dlxPdLbdQMWB+5eEyoOa4EDKIxyIAGJocdXgES2gZlU dpm8WRd6GKtqrkhF/UPzrfTT3spZZ+YYj9MYhpAr4WubOnoDHy8mdPRafVaWjfZOCWHN DKZJVb4GSzW6IdIGu4dl1SS/4gcwYD/dk77pWTworO/S83IqHHkKxxp0lSb9aAgy8HQO +gLgyNzm9Hs3t9eJBeLyzRT9B/UZu0eA+ITNgVKaJAaDHe+TBXX2V0MqdDxgmKZ6f06P SY/w== X-Gm-Message-State: AMCzsaWE/iEvmPlj4T2urMRlroecsmW/U30dKcLSPQ2y3yNr+xgJTPFU fEHsJqID4/fOCBmOpQeDLEdSdQ== X-Google-Smtp-Source: AOwi7QD+YR0FTy+Z2MAH3qr5KwoRtTqLDRqwHvzSfJYjYUY/GyZ7UsgDE/8pl0z1U1YmsDO+UuDBEw== X-Received: by 10.223.151.9 with SMTP id r9mr2079865wrb.238.1507911883881; Fri, 13 Oct 2017 09:24:43 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id s196sm2224812wmb.26.2017.10.13.09.24.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:24:42 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id AE6C23E06EB; Fri, 13 Oct 2017 17:24:38 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:12 +0100 Message-Id: <20171013162438.32458-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::232 Subject: [Qemu-devel] [RFC PATCH 04/30] target/arm/cpu.h: update comment for half-precision values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3a0f27c782..521b82d46e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -488,6 +488,7 @@ typedef struct CPUARMState { * Qn = regs[2n+1]:regs[2n] * Dn = regs[2n] * Sn = regs[2n] bits 31..0 + * Hn = regs[2n] bits 15..0 for even n, and bits 31..16 for odd n * This corresponds to the architecturally defined mapping between * the two execution states, and means we do not need to explicitly * map these registers when changing states. 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X-Received-From: 2a00:1450:400c:c0c::22f Subject: [Qemu-devel] [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.h | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index de2c5d5702..c8282b8bf7 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -685,6 +685,49 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, } #endif +/*---------------------------------------------------------------------------- +| Takes two half-precision floating-point values `a' and `b', one of which +| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a +| signaling NaN, the invalid exception is raised. +*----------------------------------------------------------------------------*/ + +static float16 propagateFloat16NaN(float16 a, float16 b, float_status *status) +{ + flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; + flag aIsLargerSignificand; + uint16_t av, bv; + + aIsQuietNaN = float16_is_quiet_nan(a, status); + aIsSignalingNaN = float16_is_signaling_nan(a, status); + bIsQuietNaN = float16_is_quiet_nan(b, status); + bIsSignalingNaN = float16_is_signaling_nan(b, status); + av = float16_val(a); + bv = float16_val(b); + + if (aIsSignalingNaN | bIsSignalingNaN) { + float_raise(float_flag_invalid, status); + } + + if (status->default_nan_mode) { + return float16_default_nan(status); + } + + if ((uint16_t)(av << 1) < (uint16_t)(bv << 1)) { + aIsLargerSignificand = 0; + } else if ((uint16_t)(bv << 1) < (uint16_t)(av << 1)) { + aIsLargerSignificand = 1; + } else { + aIsLargerSignificand = (av < bv) ? 1 : 0; + } + + if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, + aIsLargerSignificand)) { + return float16_maybe_silence_nan(b, status); + } else { + return float16_maybe_silence_nan(a, status); + } +} + /*---------------------------------------------------------------------------- | Takes two single-precision floating-point values `a' and `b', one of which | is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a From patchwork Fri Oct 13 16:24:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825582 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="RLPZZY0c"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDCqN4n21z9sxR for ; Sat, 14 Oct 2017 03:29:51 +1100 (AEDT) Received: from localhost ([::1]:51042 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32qK-0006LJ-NL for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:29:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41675) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32lU-0002Qq-8J for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32lT-0006Wp-6u for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:48 -0400 Received: from mail-wr0-x22e.google.com ([2a00:1450:400c:c0c::22e]:53996) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32lS-0006VQ-RZ for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:46 -0400 Received: by mail-wr0-x22e.google.com with SMTP id y44so1424697wry.10 for ; Fri, 13 Oct 2017 09:24:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/ILSMgJPmHL8NTcJ6LKg/3Dh7htBXoyvVG+Xzv5BpWM=; b=RLPZZY0cNtkqpNTUREEa1RZ8I4sYgOmXXuMZrRYWPrM4WxK+Er2+tBXcjSPiieHXTl Qi4Qu6JK5GC/iYPcZoO7lgQbuZzDRjnFZu0jCrjMYg6XW+nQs62QdsHoiMmeEChZehkY ctL4wCXEuBlWeC+Bam+Y4k+Jy/gpxx74eViIA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/ILSMgJPmHL8NTcJ6LKg/3Dh7htBXoyvVG+Xzv5BpWM=; b=p6slkQtVCFWMZHOqODnhATBOa2ylE/72T9qmzUyD/O8wmj4p3WkXQkByKow4o0uP6W jZEc+orowABQILOIA/1uDBGgXq4A4aN29HLgERp+0yw8Iv+0sAsgGlvg0M7u72ecYXua EK+QAeh8RlEGtNNixjdkqt8ZOAQ45VZwacEnXpdVwTkYtrrxhsuCppdUygHfB+j0C6bu 67JLe/N5rMQCV9yFzlaa8V7Ey1DXWFcVD/e8zkkyfi1+9yhFvL9yuuH3Z+f/tvIZtspS RSSrBNx1mebMnWeTqGex2r99FsjRBOwwzYVMODDNtnAOjTTRLnspZLwL41Nni/AyCKh9 y/Lg== X-Gm-Message-State: AMCzsaUqN+CP2kjVjaqQhdyIklfLg3U3xsQ4WtwGD9n9c2kAlKKzcsaw hobgh05mw2bJlZzq0UOwHlS6gQ== X-Google-Smtp-Source: AOwi7QAcSTGMPGxi/Lw5yRBCFPKOK4B89G/TG5E2IOxQSKJ0L7L6NyDNvuO7kldLs8tZN4xo8KQebQ== X-Received: by 10.223.169.33 with SMTP id u30mr1820536wrc.205.1507911885779; Fri, 13 Oct 2017 09:24:45 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id e132sm1404279wmd.42.2017.10.13.09.24.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:24:42 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id D243C3E0756; Fri, 13 Oct 2017 17:24:38 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:14 +0100 Message-Id: <20171013162438.32458-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22e Subject: [Qemu-devel] [RFC PATCH 06/30] fpu/softfloat: implement float16_squash_input_denormal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- fpu/softfloat.c | 15 +++++++++++++++ include/fpu/softfloat.h | 1 + 2 files changed, 16 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 433c5dad2d..3a4ab1355f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3488,6 +3488,21 @@ static float16 roundAndPackFloat16(flag zSign, int zExp, return packFloat16(zSign, zExp, zSig >> 13); } +/*---------------------------------------------------------------------------- +| If `a' is denormal and we are in flush-to-zero mode then set the +| input-denormal exception and return zero. Otherwise just return the value. +*----------------------------------------------------------------------------*/ +float16 float16_squash_input_denormal(float16 a, float_status *status) +{ + if (status->flush_inputs_to_zero) { + if (extractFloat16Exp(a) == 0 && extractFloat16Frac(a) != 0) { + float_raise(float_flag_input_denormal, status); + return make_float16(float16_val(a) & 0x8000); + } + } + return a; +} + static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr, uint32_t *zSigPtr) { diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 0f96a0edd1..d5e99667b6 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -277,6 +277,7 @@ void float_raise(uint8_t flags, float_status *status); | If `a' is denormal and we are in flush-to-zero mode then set the | input-denormal exception and return zero. Otherwise just return the value. *----------------------------------------------------------------------------*/ +float16 float16_squash_input_denormal(float16 a, float_status *status); float32 float32_squash_input_denormal(float32 a, float_status *status); float64 float64_squash_input_denormal(float64 a, float_status *status); From patchwork Fri Oct 13 16:24:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825583 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="PUWf2U92"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDCrb2dlsz9sRm for ; Sat, 14 Oct 2017 03:30:55 +1100 (AEDT) Received: from localhost ([::1]:51047 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32rN-0007Ff-Ba for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:30:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41704) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32lV-0002S2-2Q for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32lT-0006XS-Pn for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:49 -0400 Received: from mail-wr0-x22c.google.com ([2a00:1450:400c:c0c::22c]:46124) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32lT-0006WV-Jl for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:47 -0400 Received: by mail-wr0-x22c.google.com with SMTP id l1so1432509wrc.3 for ; Fri, 13 Oct 2017 09:24:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uzu0EfPAl6ZQEQsG6fFZRrif6loBpwApnK+pLYxHuaw=; b=PUWf2U92u1di+u8UIVYKidFpVWoMPgs8n6BOd3L5lUBTaOrsWEoH9CiFK85yW40W2W 5Y81jVPtWAtLiFn9t5LrQfPyw/7mw+lxkoEdTOn0ttj9/JGldcQTC1uwCPsHPYiA98fe lORQGEgNybMx8R2zIrlBK/3yKdj5G10ccL+XI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uzu0EfPAl6ZQEQsG6fFZRrif6loBpwApnK+pLYxHuaw=; b=LS7a38d/Nyc134ZgAjNTUtkii+SWtw2GBGSLnkZ5nwE4l2A1c0755gEJJUGdOLXD5S 6iyHdggyPuLpcTvMy6h7EKOJwqrvPG5MxRZbpXeIUOxj5kG2QfrtVPCaAHYu9eAiuiAA EMft0zskHy9iEOUaJ2gqddwhYz5h7vnaC4LGqY5R3NjALugBvh5sfhlHSExCgWzgrjzR vMYzVvyFZ2TkcdmQqg5qwLFZhykh6x5ikrrqmKaautWU6If3klTk708+Lrfd4onOhro4 CYhFr3Mhu0p8vgEsY+jjv+juJuES8ciOYhl1lRFVDUAFN27Xz81K2FWF2vm8+Vr5xxRi 9XUw== X-Gm-Message-State: AMCzsaWxAhI4phrc0UU9ioUxso3LEidruId04tqwTwiADOIdHlKIGldU xMz32lmMM1SzhXuvjAyQr/KYDQ== X-Google-Smtp-Source: AOwi7QDDw5gy9g/lqttRcwlYM9iOaOMaboLoBwqZN4XvrMoq7lpS5kDC5cp4VOU2zLtN2yNEpi28YQ== X-Received: by 10.223.135.108 with SMTP id 41mr1825523wrz.160.1507911886525; Fri, 13 Oct 2017 09:24:46 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 31sm1042784wrr.6.2017.10.13.09.24.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:24:42 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id E36443E07CC; Fri, 13 Oct 2017 17:24:38 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:15 +0100 Message-Id: <20171013162438.32458-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22c Subject: [Qemu-devel] [RFC PATCH 07/30] fpu/softfloat: implement float16_abs helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This will be required when expanding the MINMAX() macro for 16 bit/half-precision operations. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- include/fpu/softfloat.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index d5e99667b6..edf402d422 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -374,6 +374,13 @@ static inline int float16_is_zero_or_denormal(float16 a) return (float16_val(a) & 0x7c00) == 0; } +static inline float16 float16_abs(float16 a) +{ + /* Note that abs does *not* handle NaN specially, nor does + * it flush denormal inputs to zero. + */ + return make_float16(float16_val(a) & 0x7fff); +} /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ From patchwork Fri Oct 13 16:24:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825579 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="AVq/h3pn"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDCnp4lKvz9s72 for ; Sat, 14 Oct 2017 03:28:30 +1100 (AEDT) Received: from localhost ([::1]:51036 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32p2-0005D7-Ml for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:28:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41724) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32lV-0002Sv-Mo for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32lU-0006YT-Ql for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:49 -0400 Received: from mail-wr0-x22a.google.com ([2a00:1450:400c:c0c::22a]:52247) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32lU-0006Xb-LO for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:48 -0400 Received: by mail-wr0-x22a.google.com with SMTP id k62so1426464wrc.9 for ; Fri, 13 Oct 2017 09:24:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YNYltpURvYkc94gBhiDKkKFxSym98VonnTpWX1QJW2o=; b=AVq/h3pnIAWqqAj64gitNQJkWPgxW3lemKeLMpJGIehwXrOkR4KoT/pVP6WVGFo7Ph nEZDOLjyjROZg9dmtYy5CJ2m4LaWcMD0KKxWyfnow+ABzCmVHAdeZWy/LUsTuY1NNSH/ SYVXqDsHM8lCYoCYfPBo60S/Ue0sWlZfeau10= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YNYltpURvYkc94gBhiDKkKFxSym98VonnTpWX1QJW2o=; b=VRwjpLPrdTlxbB3wkxI+9RMSWDBPOWwMQ2klw1swXRAPI3Een7LXn8XbKuk500RAkA aktmfFF9lHQ1WoZJzr3qXHs2c5wjf02ckgXMzPB+5TMDq0ED/7GYeUDOlDDqmOOuRWNv b8r7QqwjxSZ129VF46m9QHDRSKee/xHloj+0EhjVYqdJd5yj5Va4E+A/jWnisOXp+LXM ci0Q/lgnWmzJw/fxlKvDxeyvUBkKuDQKnkIpiXhyS74nQKmrZ5e2iPwm85Ae32NzJqKM 8sEc/SFrPDhrR2+qRTc1uTsuTyAx1lzSZxsjXml80RPD3/zOCu0UC/ZP4VRj7jQhwrnR E60g== X-Gm-Message-State: AMCzsaWdYrE5KGujotK9jV2I/WxVBSAQKV1MeHfElVK7qDM+cp1E5gXd WxP8tWabSh1cj6ymxBAy9Ysn9A== X-Google-Smtp-Source: AOwi7QC2eieJN7k/GTmj2xRrD0weoeOOI4ShnG7wfcQIrBtYVtFDv11bU946BPTTLhdlWXxJNGQjcQ== X-Received: by 10.223.150.25 with SMTP id b25mr1888659wra.147.1507911887594; Fri, 13 Oct 2017 09:24:47 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id b190sm1885439wma.22.2017.10.13.09.24.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:24:42 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 019123E07E1; Fri, 13 Oct 2017 17:24:39 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:16 +0100 Message-Id: <20171013162438.32458-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22a Subject: [Qemu-devel] [RFC PATCH 08/30] softfloat: add half-precision expansions for MINMAX fns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Expand the current helpers to include half-precision functions. The includes having f16 version of the compare functions. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- fpu/softfloat.c | 2 ++ include/fpu/softfloat.h | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 3a4ab1355f..013b223947 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -7579,6 +7579,7 @@ int float ## s ## _compare_quiet(float ## s a, float ## s b, \ return float ## s ## _compare_internal(a, b, 1, status); \ } +COMPARE(16, 0x1f) COMPARE(32, 0xff) COMPARE(64, 0x7ff) @@ -7779,6 +7780,7 @@ float ## s float ## s ## _maxnummag(float ## s a, float ## s b, \ return float ## s ## _minmax(a, b, 0, 1, 1, status); \ } +MINMAX(16) MINMAX(32) MINMAX(64) diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index edf402d422..d89fdf7675 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -381,6 +381,17 @@ static inline float16 float16_abs(float16 a) */ return make_float16(float16_val(a) & 0x7fff); } + +/* Expanded by the MINMAX macro in softfloat.c */ +int float16_compare(float16, float16, float_status *status); +int float16_compare_quiet(float16, float16, float_status *status); +float16 float16_min(float16, float16, float_status *status); +float16 float16_max(float16, float16, float_status *status); +float16 float16_minnum(float16, float16, float_status *status); +float16 float16_maxnum(float16, float16, float_status *status); +float16 float16_minnummag(float16, float16, float_status *status); +float16 float16_maxnummag(float16, float16, float_status *status); + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ From patchwork Fri Oct 13 16:24:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825584 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 13 Oct 2017 17:24:39 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:17 +0100 Message-Id: <20171013162438.32458-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::233 Subject: [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" While a comparison between a QNaN and a number will return the number it is not the same with a signaling NaN. In this case the SNaN will "win" and after potentially raising an exception it will be quietened. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 013b223947..6ab4b39c09 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -7684,6 +7684,7 @@ int float128_compare_quiet(float128 a, float128 b, float_status *status) * minnum() and maxnum() functions. These are similar to the min() * and max() functions but if one of the arguments is a QNaN and * the other is numerical then the numerical argument is returned. + * SNaNs will get quietened before being returned. * minnum() and maxnum correspond to the IEEE 754-2008 minNum() * and maxNum() operations. min() and max() are the typical min/max * semantics provided by many CPUs which predate that specification. @@ -7704,11 +7705,14 @@ static inline float ## s float ## s ## _minmax(float ## s a, float ## s b, \ if (float ## s ## _is_any_nan(a) || \ float ## s ## _is_any_nan(b)) { \ if (isieee) { \ - if (float ## s ## _is_quiet_nan(a, status) && \ + if (float ## s ## _is_signaling_nan(a, status) || \ + float ## s ## _is_signaling_nan(b, status)) { \ + propagateFloat ## s ## NaN(a, b, status); \ + } else if (float ## s ## _is_quiet_nan(a, status) && \ !float ## s ##_is_any_nan(b)) { \ return b; \ } else if (float ## s ## _is_quiet_nan(b, status) && \ - !float ## s ## _is_any_nan(a)) { \ + !float ## s ## _is_any_nan(a)) { \ return a; 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Fri, 13 Oct 2017 09:24:48 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 243893E08CD; Fri, 13 Oct 2017 17:24:39 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:18 +0100 Message-Id: <20171013162438.32458-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Mention the pseudo-code fragment from which this is based and correct the spelling of signalling. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index c8282b8bf7..2ccd4abe11 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -445,14 +445,14 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status) #if defined(TARGET_ARM) static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) + flag aIsLargerSignificand) { - /* ARM mandated NaN propagation rules: take the first of: - * 1. A if it is signaling - * 2. B if it is signaling + /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take the first of: + * 1. A if it is signalling + * 2. B if it is signalling * 3. A (quiet) * 4. B (quiet) - * A signaling NaN is always quietened before returning it. + * A signalling NaN is always quietened before returning it. */ if (aIsSNaN) { return 0; From patchwork Fri Oct 13 16:24:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825585 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="dOFfXf0k"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDCs75PQqz9sRm for ; Sat, 14 Oct 2017 03:31:23 +1100 (AEDT) Received: from localhost ([::1]:51056 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32rp-0007jZ-O1 for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:31:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41842) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32ld-0002d2-Qi for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32lY-0006ax-PM for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:57 -0400 Received: from mail-wm0-x233.google.com ([2a00:1450:400c:c09::233]:56123) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32lY-0006aR-G7 for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:52 -0400 Received: by mail-wm0-x233.google.com with SMTP id u138so22951877wmu.4 for ; Fri, 13 Oct 2017 09:24:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bkb/DAK/MhmwL4UQX64YPV883SIsP4TZw8zxphtUdEw=; b=dOFfXf0k6YrSXU8JMcl5Luw77SHTBXfPrCi8OgVQ1mVbxVAFZngDqnAE21f/2ixYVQ la3u/YPYX0nyyPGp0Nu/FE2/PJDL6L1koMFkU1S2QgnuCe6usSh/0zaB/QW9lAc65H5W DjI1E63BfpFURjJJHZMT7HgdY9sKZufrK9lwU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bkb/DAK/MhmwL4UQX64YPV883SIsP4TZw8zxphtUdEw=; b=CjecAdlzanYLc336zSELtAVSXfRCMeHQzS8Nwdt0Qim/6CnT36e7kSI4fQ+ty5hj1g Tmt4goCsTgx2p45R+3C8eFFfdzUWUC6mW+flVY9ietszYpyHqg2AWuLUHJj5iObjBiiG 50JX0CPtJkBN6ow4ZAtJ7qQyjaHa8Zb0UC0x6yl8vOheR/1CsnofU5CDNmEwouaeAg75 6Ytxz/rn8Y5EWbn8cgh6KRnsslKUNc5zZgeLRmKFrEfO0Q1bPcrGA5XlNa95vCm+zemJ SEfKEOs0PUeGrux8+3L21oZRjsv9outwnkQHXal2X7cvs0FOK7AVueJAdM7jC3k+ge1B uJFA== X-Gm-Message-State: AMCzsaWJpoaHC+pNVmt8Zb3Mdto2MM4OXmSdqd3VhX47JsR/Wm/678kX B8NbLvqyHJVxJliQzodDcnVKKQ== X-Google-Smtp-Source: AOwi7QDXep42gX4oj8a8n1VTo2TmPWw8bdRk4q81jIQrDA3l9xIqkEmLM743VDEZYsmhZ3yRIhD7lQ== X-Received: by 10.28.236.25 with SMTP id k25mr2136788wmh.146.1507911891277; Fri, 13 Oct 2017 09:24:51 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id v10sm2211799wrb.92.2017.10.13.09.24.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:24:48 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 376273E0AA7; Fri, 13 Oct 2017 17:24:39 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:19 +0100 Message-Id: <20171013162438.32458-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::233 Subject: [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Signed-off-by: Alex Bennée --- v1 - dropped the advsimd_2a stuff --- target/arm/helper-a64.c | 18 ++++++ target/arm/helper-a64.h | 4 ++ target/arm/translate-a64.c | 147 ++++++++++++++++++++++++++++----------------- 3 files changed, 115 insertions(+), 54 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index d9df82cff5..a0c20faabc 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -537,3 +537,21 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, return !success; } + +/* + * AdvSIMD half-precision + */ + +#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix)) + +#define ADVSIMD_HALFOP(name) \ +float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \ +{ \ + float_status *fpst = fpstp; \ + return float16_ ## name(a, b, fpst); \ +} + +ADVSIMD_HALFOP(min) +ADVSIMD_HALFOP(max) +ADVSIMD_HALFOP(minnum) +ADVSIMD_HALFOP(maxnum) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6f9eaba533..b774431f1f 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -44,3 +44,7 @@ DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a39b9d3633..1282d14c58 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5602,26 +5602,80 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_resh); } -static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2, - int opc, bool is_min, TCGv_ptr fpst) -{ - /* Helper function for disas_simd_across_lanes: do a single precision - * min/max operation on the specified two inputs, - * and return the result in tcg_elt1. - */ - if (opc == 0xc) { - if (is_min) { - gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } else { - gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } +/* + * do_reduction_op helper + * + * This mirrors the Reduce() pseudocode in the ARM ARM. It is + * important for correct NaN propagation that we do these + * operations in exactly the order specified by the pseudocode. + * + * This is a recursive function, TCG temps should be freed by the + * calling function once it is done with the values. + */ +static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, + int esize, int size, int vmap, TCGv_ptr fpst) +{ + if (esize == size) { + int element; + TCGMemOp msize = esize == 16 ? MO_16 : MO_32; + TCGv_i32 tcg_elem; + + /* We should have one register left here */ + assert(ctpop8(vmap) == 1); + element = ctz32(vmap); + assert(element < 8); + + tcg_elem = tcg_temp_new_i32(); + read_vec_element_i32(s, tcg_elem, rn, element, msize); + return tcg_elem; } else { - assert(opc == 0xf); - if (is_min) { - gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } else { - gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst); + int bits = size / 2; + int shift = ctpop8(vmap) / 2; + int vmap_lo = (vmap >> shift) & vmap; + int vmap_hi = (vmap & ~vmap_lo); + TCGv_i32 tcg_hi, tcg_lo, tcg_res; + + tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst); + tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst); + tcg_res = tcg_temp_new_i32(); + + /* base fpopcode = 0x0c NMV, 0x0f V + 0x10 MIN, 0x00 MAX + 0x20 F32, 0x00 FP16 + */ + switch(fpopcode) { + case 0x0c: /* fmaxnmv half-precision */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x0f: /* fmaxv half-precision */ + gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x1c: /* fminnmv half-precision */ + gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x1f: /* fminv half-precision */ + gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x2c: /* fmaxnmv */ + gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x2f: /* fmaxv */ + gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x3c: /* fminnmv */ + gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x3f: /* fminv */ + gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst); + break; + default: + fprintf(stderr, "%s: fpopcode %x not handled\n", __func__, fpopcode); + break; } + + tcg_temp_free_i32(tcg_hi); + tcg_temp_free_i32(tcg_lo); + return tcg_res; } } @@ -5663,16 +5717,21 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) break; case 0xc: /* FMAXNMV, FMINNMV */ case 0xf: /* FMAXV, FMINV */ - if (!is_u || !is_q || extract32(size, 0, 1)) { - unallocated_encoding(s); - return; - } - /* Bit 1 of size field encodes min vs max, and actual size is always - * 32 bits: adjust the size variable so following code can rely on it + /* Bit 1 of size field encodes min vs max and the actual size + * depends on the encoding of the U bit. If not set (and FP16 + * enabled) then we do half-precision float instead of single + * precision. */ is_min = extract32(size, 1, 1); is_fp = true; - size = 2; + if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + size = 1; + } else if (!is_u || !is_q || extract32(size, 0, 1)) { + unallocated_encoding(s); + return; + } else { + size = 2; + } break; default: unallocated_encoding(s); @@ -5729,38 +5788,18 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) } } else { - /* Floating point ops which work on 32 bit (single) intermediates. + /* Floating point vector reduction ops which work across 32 + * bit (single) or 16 bit (half-precision) intermediates. * Note that correct NaN propagation requires that we do these * operations in exactly the order specified by the pseudocode. */ - TCGv_i32 tcg_elt1 = tcg_temp_new_i32(); - TCGv_i32 tcg_elt2 = tcg_temp_new_i32(); - TCGv_i32 tcg_elt3 = tcg_temp_new_i32(); TCGv_ptr fpst = get_fpstatus_ptr(); - - assert(esize == 32); - assert(elements == 4); - - read_vec_element(s, tcg_elt, rn, 0, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt); - read_vec_element(s, tcg_elt, rn, 1, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt); - - do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); - - read_vec_element(s, tcg_elt, rn, 2, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt); - read_vec_element(s, tcg_elt, rn, 3, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt); - - do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst); - - do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); - - tcg_gen_extu_i32_i64(tcg_res, tcg_elt1); - tcg_temp_free_i32(tcg_elt1); - tcg_temp_free_i32(tcg_elt2); - tcg_temp_free_i32(tcg_elt3); + int fpopcode = opcode | is_min << 4 | is_u << 5; + int vmap = (1 << elements) - 1; + TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize, + (is_q ? 128 : 64), vmap, fpst); + tcg_gen_extu_i32_i64(tcg_res, tcg_res32); + tcg_temp_free_i32(tcg_res32); tcg_temp_free_ptr(fpst); } @@ -5882,7 +5921,7 @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, { int size = ctz32(imm5); int esize = 8 << size; - int elements = (is_q ? 128 : 64)/esize; + int elements = (is_q ? 128 : 64) / esize; int i = 0; if (size > 3 || ((size == 3) && !is_q)) { From patchwork Fri Oct 13 16:24:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825590 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Njkp3gUd"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDCzk65Fdz9sRm for ; Sat, 14 Oct 2017 03:37:06 +1100 (AEDT) Received: from localhost ([::1]:51086 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32xM-00044j-TY for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:37:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32ld-0002d6-SI for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32la-0006cD-84 for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:57 -0400 Received: from mail-wr0-x236.google.com ([2a00:1450:400c:c0c::236]:55840) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32la-0006bZ-1l for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:54 -0400 Received: by mail-wr0-x236.google.com with SMTP id 22so1427510wrb.12 for ; Fri, 13 Oct 2017 09:24:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4bssyXsH/U9UMc4CIz9eLNvIqbTB2VIF8Y515Lq6qNg=; b=Njkp3gUdT6I4EE6ZiYHWMTFPfUueukTtd0VG2Kem2Q98r+2YFIw61C4j/6zh1ntF5L OYxEK/mcTtraQpTrff4UQ/Rnxd4rJCofQJTwPTsxGNxEC76SH7ymxkbc9Irst4i8zOhQ BPy7XmAipZmDLKksK8/8JCVDgoQLgiG3Elk84= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4bssyXsH/U9UMc4CIz9eLNvIqbTB2VIF8Y515Lq6qNg=; b=ppOqFTkdb1uXuKW9N0MneOgB4c8czylMPD4Raw+A/wZGa5mkljewuTP1wnM3uxCgnF EsDJZhR+WJggESnbVosBYoyA/RXV281uMRMaIYakSeFu7GhnCo2o0u0upb4EJQVGZAFe bhbMRJ0qd85qnQGaaF/B/FG9kEz/Oi1UAkNiR0HzXDPJ9V4GgOC8Swc8WqYOH/oVOXbm JJnMLf5ho7RQpWGQ7tVohczPjRE1+iPXhvQysVv3ZmZLKEqCd8PmCUAH+WpgV6ZQWe4p ed//RVfrLXrYPwk2Wdt1j6/7OwW7JnyL3HBb4JDlf1zKEuFxGcxLi9haRsfkXWwsmoks n6Gg== X-Gm-Message-State: AMCzsaVim8w8gjlx61r/TBChKsPOk1sn8Nvt/dCE8VerfbDkOjvagbDn REZ2yuiHwnBqh7+oEJOyFC43hA== X-Google-Smtp-Source: AOwi7QB1X+A3gRBnq3tQJrXF5FTzIPwV7PYBwayhsnSY6X4ExU4pgV/oKUPGFR0CiXmRw8IJeuBmkw== X-Received: by 10.223.132.6 with SMTP id 6mr1835959wrf.93.1507911892994; Fri, 13 Oct 2017 09:24:52 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id v80sm1282447wmv.37.2017.10.13.09.24.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:24:48 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 4872E3E0BDC; Fri, 13 Oct 2017 17:24:39 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:20 +0100 Message-Id: <20171013162438.32458-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We do implement all the opcodes. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1282d14c58..50e53bf8b0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7177,8 +7177,7 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u, /* Handle 64x64->64 opcodes which are shared between the scalar * and vector 3-same groups. We cover every opcode where size == 3 * is valid in either the three-reg-same (integer, not pairwise) - * or scalar-three-reg-same groups. (Some opcodes are not yet - * implemented.) + * or scalar-three-reg-same groups. */ TCGCond cond; From patchwork Fri Oct 13 16:24:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825601 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="PCoJH8J0"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDD8G5cK7z9sxR for ; Sat, 14 Oct 2017 03:44:30 +1100 (AEDT) Received: from localhost ([::1]:51130 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e334W-0001v7-Mv for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:44:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44005) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32sX-0000Yv-T1 for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32sW-0002Fu-SI for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:05 -0400 Received: from mail-wr0-x231.google.com ([2a00:1450:400c:c0c::231]:56650) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32sW-0002FE-L9 for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:04 -0400 Received: by mail-wr0-x231.google.com with SMTP id r79so1443165wrb.13 for ; Fri, 13 Oct 2017 09:32:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TKxk+a6SMfN5OFT+aCbP3LUxDsdDcUHvI4Ye9fChGlI=; b=PCoJH8J0b+x1OgnFemMEMxQgxfsqJVk4PvbfCsaNPC+4fB7xOV8s39/hNQnNyBfIq7 my37Hec4b1AlHsRf8j3ggJ8N0B703jeaA6/OPLX93kkvC7ZI7Zz6BNSV86sK7lcNXTtR 476I58pK2LI+Nb9ODUBCHCO809fw/O1/gVxhc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TKxk+a6SMfN5OFT+aCbP3LUxDsdDcUHvI4Ye9fChGlI=; b=C0f5Nv6uzcotqrZ4gHtpDZGEWKKQIT+kG+ZctSgBH7SoE0N6VD/5eGi4y1LpIzGioz rWX1rCX1Yr9hGuDSsYfxopAoIkZUOp9VIWxYR+5i1rbkS109RbJfOnn/TaJ7Y9EMqSSH Pl58pcyqjEFMZk3DxcnVOx78wbduat6zoDE/9+C/mIsSTpRybe7i3Hs0mG8UyHh3lZiE 6PFyXX3RIsUnmxJibLPmDPr7OkWA6Ent+i+8fXHcQkDm0gtmrMtO4JOdZuh0DCup4CCt TSQFhdBtHWACCBJC0HHqvJDrhOoBO590Gbe2nZk9mMhVw9m0d+HDvkNo3zM/IG31kOOF dHcA== X-Gm-Message-State: AMCzsaUQb53UvBGah7KNkzTmY78fmHpZGGzyzTn9AKtFmJcgDDnTHTpS 41JLoDHp5pp7+CEJ4G+cK5eRHQ== X-Google-Smtp-Source: AOwi7QBWVSndHfNDluEHQFZPfTixImfpt9/Bjate7+W+A81VVgIej48nFuPgdw92QGgycJmVaE4UZQ== X-Received: by 10.223.195.131 with SMTP id p3mr2075335wrf.89.1507912323423; Fri, 13 Oct 2017 09:32:03 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id i76sm6042508wmd.2.2017.10.13.09.31.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:31:59 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 590D23E0BDF; Fri, 13 Oct 2017 17:24:39 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:21 +0100 Message-Id: <20171013162438.32458-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::231 Subject: [Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is the initial decode skeleton for the Advanced SIMD scalar three same instruction group. The fprintf is purely to aid debugging as the additional instructions are added. It will be removed once the group is complete. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/translate-a64.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 50e53bf8b0..5e531b3ae4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9751,6 +9751,81 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) } } +/* + * Advanced SIMD three same (ARMv8.2 FP16 variants) + * + * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 + * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ + * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | + * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ + * + * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE + * (register), FACGE, FABD, FCMGT (register) and FACGT. + * + */ +static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) +{ + int opcode, fpopcode; + int is_q, u, a, rm, rn, rd; + int datasize, elements; + int pass; + TCGv_ptr fpst; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + /* For these floating point ops, the U, a and opcode bits + * together indicate the operation. + */ + opcode = extract32(insn, 11, 3); + u = extract32(insn, 29, 1); + a = extract32(insn, 23, 1); + is_q = extract32(insn, 30, 1); + rm = extract32(insn, 16, 5); + rn = extract32(insn, 5, 5); + rd = extract32(insn, 0, 5); + + fpopcode = opcode | (a << 4) | (u << 5); + datasize = is_q ? 128 : 64; + elements = datasize / 16; + + fpst = get_fpstatus_ptr(); + + for (pass = 0; pass < elements; pass++) { + TCGv_i32 tcg_op1 = tcg_temp_new_i32(); + TCGv_i32 tcg_op2 = tcg_temp_new_i32(); + TCGv_i32 tcg_res = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); + read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); + + switch (fpopcode) { + default: + fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpopcode); + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + } + + tcg_temp_free_ptr(fpst); + + if (!is_q) { + /* non-quad vector op */ + clear_vec_high(s, rd); + } + +} + static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, int size, int rn, int rd) { @@ -11159,6 +11234,7 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, + { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, { 0x00000000, 0x00000000, NULL } }; From patchwork Fri Oct 13 16:24:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825605 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 13 Oct 2017 17:24:39 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:22 +0100 Message-Id: <20171013162438.32458-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Half-precision helpers for float16 maths. I didn't bother hand-coding the count leading zeros as we could always fall-back to host-utils if we needed to. Signed-off-by: Alex Bennée --- fpu/softfloat-macros.h | 39 +++++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 21 +++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/fpu/softfloat-macros.h b/fpu/softfloat-macros.h index 9cc6158cb4..73091a88a8 100644 --- a/fpu/softfloat-macros.h +++ b/fpu/softfloat-macros.h @@ -89,6 +89,31 @@ this code that are retained. # define SOFTFLOAT_GNUC_PREREQ(maj, min) 0 #endif +/*---------------------------------------------------------------------------- +| Shifts `a' right by the number of bits given in `count'. If any nonzero +| bits are shifted off, they are ``jammed'' into the least significant bit of +| the result by setting the least significant bit to 1. The value of `count' +| can be arbitrarily large; in particular, if `count' is greater than 16, the +| result will be either 0 or 1, depending on whether `a' is zero or nonzero. +| The result is stored in the location pointed to by `zPtr'. +*----------------------------------------------------------------------------*/ + +static inline void shift16RightJamming(uint16_t a, int count, uint16_t *zPtr) +{ + uint16_t z; + + if ( count == 0 ) { + z = a; + } + else if ( count < 16 ) { + z = ( a>>count ) | ( ( a<<( ( - count ) & 16 ) ) != 0 ); + } + else { + z = ( a != 0 ); + } + *zPtr = z; + +} /*---------------------------------------------------------------------------- | Shifts `a' right by the number of bits given in `count'. If any nonzero @@ -664,6 +689,20 @@ static uint32_t estimateSqrt32(int aExp, uint32_t a) } +/*---------------------------------------------------------------------------- +| Returns the number of leading 0 bits before the most-significant 1 bit of +| `a'. If `a' is zero, 16 is returned. +*----------------------------------------------------------------------------*/ + +static int8_t countLeadingZeros16( uint16_t a ) +{ + if (a) { + return __builtin_clz(a); + } else { + return 16; + } +} + /*---------------------------------------------------------------------------- | Returns the number of leading 0 bits before the most-significant 1 bit of | `a'. If `a' is zero, 32 is returned. diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6ab4b39c09..cf7bf6d4f4 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3488,6 +3488,27 @@ static float16 roundAndPackFloat16(flag zSign, int zExp, return packFloat16(zSign, zExp, zSig >> 13); } +/*---------------------------------------------------------------------------- +| Takes an abstract floating-point value having sign `zSign', exponent `zExp', +| and significand `zSig', and returns the proper single-precision floating- +| point value corresponding to the abstract input. This routine is just like +| `roundAndPackFloat32' except that `zSig' does not have to be normalized. +| Bit 15 of `zSig' must be zero, and `zExp' must be 1 less than the ``true'' +| floating-point exponent. +*----------------------------------------------------------------------------*/ + +static float16 + normalizeRoundAndPackFloat16(flag zSign, int zExp, uint16_t zSig, + float_status *status) +{ + int8_t shiftCount; + + shiftCount = countLeadingZeros16( zSig ) - 1; + return roundAndPackFloat16(zSign, zExp - shiftCount, zSig< X-Patchwork-Id: 825589 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UtUvA8aG"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDCyD44wgz9sRm for ; Sat, 14 Oct 2017 03:35:48 +1100 (AEDT) Received: from localhost ([::1]:51076 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32w6-0002up-JO for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:35:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41845) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32ld-0002d4-RX for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:25:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32lb-0006dD-Dx for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:57 -0400 Received: from mail-wr0-x22b.google.com ([2a00:1450:400c:c0c::22b]:51102) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32lb-0006cR-4S for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:24:55 -0400 Received: by mail-wr0-x22b.google.com with SMTP id q42so1429855wrb.7 for ; Fri, 13 Oct 2017 09:24:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fe3BMdKMEp8SD7k107xez1o/mOjZCJNEkZcsa6A7NcE=; b=UtUvA8aG+nlBCNImP1T7Ygfh30+r57Jy91nrIKPYZMrRH056i4D1ev6BCJ4W24adZS 1uE30FCgS9DATphTI8kwbl0SBQgxQPrB54CfkvBV1+JELiyF5BG3V+qhNRlHapE8yyk8 t2QtnuyuZcv/rmcP4tXgovs6XIx0OqcbzCPSo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fe3BMdKMEp8SD7k107xez1o/mOjZCJNEkZcsa6A7NcE=; b=Ql5SZvYIqnNHTldAuFhwFfX4lNzGJk063zH1Il4AlVAsUndDLSH7g86lNKAxIutcEb ZaEpzXTh0H/0fFxjU996+OCHwLa/CJZ6YZJCx8J+SLUbhrC9sqMM7bsfhSbbuLHVtf6y ohTicJyj51+F430tQRutSTudn7ZbCeAgYlpLXIbNtCelF5IiTCEQVfu3EwHZ7Eaxqc0R of6w1LzoRqgngQBHdCqRjLKCmXD58pYVKd4G+KxDT9cZ9+dNLlKZVli1oDqGrl06QFV0 YbuJYfUgSTivo6dOFxVi7HSf8Dph5vhiXwMUOjoyRanbi9ieJRVaASMAyI99uUZaO7hH ZVrw== X-Gm-Message-State: AMCzsaVvdswItWgccBZIEj0wUcscc1qsFGZbtx5b2pZs7pjDCH4lbDR2 51njGFjek9KHww99eAM2l4LLYQ== X-Google-Smtp-Source: AOwi7QCNc1+J2+7HSPhA1B08nu7XFV1wG4Q8+dPFgQMcnpyIzJkVvFPjiIBHjqKYYahHSWP5b55JZg== X-Received: by 10.223.148.71 with SMTP id 65mr1753373wrq.263.1507911893708; Fri, 13 Oct 2017 09:24:53 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id c37sm2870579wra.73.2017.10.13.09.24.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:24:48 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 7DA773E0CA5; Fri, 13 Oct 2017 17:24:39 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:23 +0100 Message-Id: <20171013162438.32458-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::22b Subject: [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Rather than following the SoftFloat3 implementation I've used the same basic template as the rest of our softfloat code. One minor difference is the 32bit intermediates end up with the binary point in the same place as the 32 bit version so the change isn't totally mechanical. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 352 ++++++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 6 + 2 files changed, 358 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index cf7bf6d4f4..ff967f5525 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3532,6 +3532,358 @@ static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr, *zExpPtr = 1 - shiftCount; } +/*---------------------------------------------------------------------------- +| Returns the result of adding the absolute values of the half-precision +| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated +| before being returned. `zSign' is ignored if the result is a NaN. +| The addition is performed according to the IEC/IEEE Standard for Binary +| Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +static float16 addFloat16Sigs(float16 a, float16 b, flag zSign, + float_status *status) +{ + int aExp, bExp, zExp; + uint16_t aSig, bSig, zSig; + int expDiff; + + aSig = extractFloat16Frac( a ); + aExp = extractFloat16Exp( a ); + bSig = extractFloat16Frac( b ); + bExp = extractFloat16Exp( b ); + expDiff = aExp - bExp; + aSig <<= 3; + bSig <<= 3; + if ( 0 < expDiff ) { + if ( aExp == 0x1F ) { + if (aSig) { + return propagateFloat16NaN(a, b, status); + } + return a; + } + if ( bExp == 0 ) { + --expDiff; + } + else { + bSig |= 0x20000000; + } + shift16RightJamming( bSig, expDiff, &bSig ); + zExp = aExp; + } + else if ( expDiff < 0 ) { + if ( bExp == 0x1F ) { + if (bSig) { + return propagateFloat16NaN(a, b, status); + } + return packFloat16( zSign, 0x1F, 0 ); + } + if ( aExp == 0 ) { + ++expDiff; + } + else { + aSig |= 0x0400; + } + shift16RightJamming( aSig, - expDiff, &aSig ); + zExp = bExp; + } + else { + if ( aExp == 0x1F ) { + if (aSig | bSig) { + return propagateFloat16NaN(a, b, status); + } + return a; + } + if ( aExp == 0 ) { + if (status->flush_to_zero) { + if (aSig | bSig) { + float_raise(float_flag_output_denormal, status); + } + return packFloat16(zSign, 0, 0); + } + return packFloat16( zSign, 0, ( aSig + bSig )>>3 ); + } + zSig = 0x0400 + aSig + bSig; + zExp = aExp; + goto roundAndPack; + } + aSig |= 0x0400; + zSig = ( aSig + bSig )<<1; + --zExp; + if ( (int16_t) zSig < 0 ) { + zSig = aSig + bSig; + ++zExp; + } + roundAndPack: + return roundAndPackFloat16(zSign, zExp, zSig, true, status); + +} + +/*---------------------------------------------------------------------------- +| Returns the result of subtracting the absolute values of the half- +| precision floating-point values `a' and `b'. If `zSign' is 1, the +| difference is negated before being returned. `zSign' is ignored if the +| result is a NaN. The subtraction is performed according to the IEC/IEEE +| Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +static float16 subFloat16Sigs(float16 a, float16 b, flag zSign, + float_status *status) +{ + int aExp, bExp, zExp; + uint16_t aSig, bSig, zSig; + int expDiff; + + aSig = extractFloat16Frac( a ); + aExp = extractFloat16Exp( a ); + bSig = extractFloat16Frac( b ); + bExp = extractFloat16Exp( b ); + expDiff = aExp - bExp; + aSig <<= 7; + bSig <<= 7; + if ( 0 < expDiff ) goto aExpBigger; + if ( expDiff < 0 ) goto bExpBigger; + if ( aExp == 0xFF ) { + if (aSig | bSig) { + return propagateFloat16NaN(a, b, status); + } + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + if ( aExp == 0 ) { + aExp = 1; + bExp = 1; + } + if ( bSig < aSig ) goto aBigger; + if ( aSig < bSig ) goto bBigger; + return packFloat16(status->float_rounding_mode == float_round_down, 0, 0); + bExpBigger: + if ( bExp == 0xFF ) { + if (bSig) { + return propagateFloat16NaN(a, b, status); + } + return packFloat16( zSign ^ 1, 0xFF, 0 ); + } + if ( aExp == 0 ) { + ++expDiff; + } + else { + aSig |= 0x40000000; + } + shift16RightJamming( aSig, - expDiff, &aSig ); + bSig |= 0x40000000; + bBigger: + zSig = bSig - aSig; + zExp = bExp; + zSign ^= 1; + goto normalizeRoundAndPack; + aExpBigger: + if ( aExp == 0xFF ) { + if (aSig) { + return propagateFloat16NaN(a, b, status); + } + return a; + } + if ( bExp == 0 ) { + --expDiff; + } + else { + bSig |= 0x40000000; + } + shift16RightJamming( bSig, expDiff, &bSig ); + aSig |= 0x40000000; + aBigger: + zSig = aSig - bSig; + zExp = aExp; + normalizeRoundAndPack: + --zExp; + return normalizeRoundAndPackFloat16(zSign, zExp, zSig, status); + +} + +/*---------------------------------------------------------------------------- +| Returns the result of adding the half-precision floating-point values `a' +| and `b'. The operation is performed according to the IEC/IEEE Standard for +| Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_add(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + if ( aSign == bSign ) { + return addFloat16Sigs(a, b, aSign, status); + } + else { + return subFloat16Sigs(a, b, aSign, status); + } + +} + +/*---------------------------------------------------------------------------- +| Returns the result of subtracting the half-precision floating-point values +| `a' and `b'. The operation is performed according to the IEC/IEEE Standard +| for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_sub(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + if ( aSign == bSign ) { + return subFloat16Sigs(a, b, aSign, status); + } + else { + return addFloat16Sigs(a, b, aSign, status); + } + +} + +/*---------------------------------------------------------------------------- +| Returns the result of multiplying the half-precision floating-point values +| `a' and `b'. The operation is performed according to the IEC/IEEE Standard +| for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_mul(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign, zSign; + int aExp, bExp, zExp; + uint32_t aSig, bSig; + uint32_t zSig32; /* no zSig as zSig32 passed into rp&f */ + + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + aSig = extractFloat16Frac( a ); + aExp = extractFloat16Exp( a ); + aSign = extractFloat16Sign( a ); + bSig = extractFloat16Frac( b ); + bExp = extractFloat16Exp( b ); + bSign = extractFloat16Sign( b ); + zSign = aSign ^ bSign; + if ( aExp == 0x1F ) { + if ( aSig || ( ( bExp == 0x1F ) && bSig ) ) { + return propagateFloat16NaN(a, b, status); + } + if ( ( bExp | bSig ) == 0 ) { + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + return packFloat16( zSign, 0x1F, 0 ); + } + if ( bExp == 0x1F ) { + if (bSig) { + return propagateFloat16NaN(a, b, status); + } + if ( ( aExp | aSig ) == 0 ) { + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + return packFloat16( zSign, 0x1F, 0 ); + } + if ( aExp == 0 ) { + if ( aSig == 0 ) return packFloat16( zSign, 0, 0 ); + normalizeFloat16Subnormal( aSig, &aExp, &aSig ); + } + if ( bExp == 0 ) { + if ( bSig == 0 ) return packFloat16( zSign, 0, 0 ); + normalizeFloat16Subnormal( bSig, &bExp, &bSig ); + } + zExp = aExp + bExp - 0xF; + /* Add implicit bit */ + aSig = ( aSig | 0x0400 )<<4; + bSig = ( bSig | 0x0400 )<<5; + /* Max (format " => 0x%x" (* (lsh #x400 4) (lsh #x400 5))) => 0x20000000 + * So shift so binary point from 30/29 to 23/22 + */ + shift32RightJamming( ( (uint32_t) aSig ) * bSig, 7, &zSig32 ); + /* At this point the significand is at the same point as + * float32_mul, so we can do the same test */ + if ( 0 <= (int32_t) ( zSig32<<1 ) ) { + zSig32 <<= 1; + --zExp; + } + return roundAndPackFloat16(zSign, zExp, zSig32, true, status); +} + +/*---------------------------------------------------------------------------- +| Returns the result of dividing the half-precision floating-point value `a' +| by the corresponding value `b'. The operation is performed according to the +| IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_div(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign, zSign; + int aExp, bExp, zExp; + uint32_t aSig, bSig, zSig; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + aSig = extractFloat16Frac( a ); + aExp = extractFloat16Exp( a ); + aSign = extractFloat16Sign( a ); + bSig = extractFloat16Frac( b ); + bExp = extractFloat16Exp( b ); + bSign = extractFloat16Sign( b ); + zSign = aSign ^ bSign; + if ( aExp == 0xFF ) { + if (aSig) { + return propagateFloat16NaN(a, b, status); + } + if ( bExp == 0xFF ) { + if (bSig) { + return propagateFloat16NaN(a, b, status); + } + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + return packFloat16( zSign, 0xFF, 0 ); + } + if ( bExp == 0xFF ) { + if (bSig) { + return propagateFloat16NaN(a, b, status); + } + return packFloat16( zSign, 0, 0 ); + } + if ( bExp == 0 ) { + if ( bSig == 0 ) { + if ( ( aExp | aSig ) == 0 ) { + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + float_raise(float_flag_divbyzero, status); + return packFloat16( zSign, 0xFF, 0 ); + } + normalizeFloat16Subnormal( bSig, &bExp, &bSig ); + } + if ( aExp == 0 ) { + if ( aSig == 0 ) return packFloat16( zSign, 0, 0 ); + normalizeFloat16Subnormal( aSig, &aExp, &aSig ); + } + zExp = aExp - bExp + 0x7D; + aSig = ( aSig | 0x00800000 )<<7; + bSig = ( bSig | 0x00800000 )<<8; + if ( bSig <= ( aSig + aSig ) ) { + aSig >>= 1; + ++zExp; + } + zSig = ( ( (uint64_t) aSig )<<16 ) / bSig; + if ( ( zSig & 0x3F ) == 0 ) { + zSig |= ( (uint64_t) bSig * zSig != ( (uint64_t) aSig )<<16 ); + } + return roundAndPackFloat16(zSign, zExp, zSig, true, status); + +} + /* Half precision floats come in two formats: standard IEEE and "ARM" format. The latter gains extra exponent range by omitting the NaN/Inf encodings. */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index d89fdf7675..f1d79b6d03 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -345,6 +345,12 @@ float64 float16_to_float64(float16 a, flag ieee, float_status *status); /*---------------------------------------------------------------------------- | Software half-precision operations. *----------------------------------------------------------------------------*/ + +float16 float16_add(float16, float16, float_status *status); +float16 float16_sub(float16, float16, float_status *status); +float16 float16_mul(float16, float16, float_status *status); +float16 float16_div(float16, float16, float_status *status); + int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); float16 float16_maybe_silence_nan(float16, float_status *status); From patchwork Fri Oct 13 16:24:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825607 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="W7JjesUm"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDDGn44rfz9sRq for ; Sat, 14 Oct 2017 03:50:09 +1100 (AEDT) Received: from localhost ([::1]:51163 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e339z-0006Er-L9 for incoming@patchwork.ozlabs.org; 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X-Received-From: 2a00:1450:400c:c0c::229 Subject: [Qemu-devel] [RFC PATCH 16/30] target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 4 ++++ target/arm/helper-a64.h | 4 ++++ target/arm/translate-a64.c | 12 +++++++++++- 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index a0c20faabc..8ef15c4c45 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -551,6 +551,10 @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \ return float16_ ## name(a, b, fpst); \ } +ADVSIMD_HALFOP(add) +ADVSIMD_HALFOP(sub) +ADVSIMD_HALFOP(mul) +ADVSIMD_HALFOP(div) ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index b774431f1f..a4ce87970e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -44,6 +44,10 @@ DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5e531b3ae4..f687bab214 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9806,8 +9806,18 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); switch (fpopcode) { + case 0x2: /* FADD */ + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x23: /* FMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x27: /* FDIV */ + gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); + break; default: - fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpopcode); + fprintf(stderr,"%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", + __func__, insn, fpopcode, s->pc); g_assert_not_reached(); } From patchwork Fri Oct 13 16:24:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825586 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; 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X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 18 ++++++++++++++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 45 +++++++++++++++++++++++++++++++++++---------- 3 files changed, 54 insertions(+), 10 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 8ef15c4c45..dd26675d5c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -559,3 +559,21 @@ ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) + +/* Data processing - scalar floating-point and advanced SIMD */ + +float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + + a = float16_squash_input_denormal(a, fpst); + b = float16_squash_input_denormal(b, fpst); + + if ((float16_is_zero(a) && float16_is_infinity(b)) || + (float16_is_infinity(a) && float16_is_zero(b))) { + /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ + return make_float16((1U << 14) | + ((float16_val(a) ^ float16_val(b)) & (1U << 15))); + } + return float16_mul(a, b, fpst); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a4ce87970e..0f97eb607f 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -52,3 +52,4 @@ DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f687bab214..d12106695f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10648,7 +10648,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } /* fall through */ case 0x9: /* FMUL, FMULX */ - if (!extract32(size, 1, 1)) { + if (!extract32(size, 1, 1) && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); return; } @@ -10660,18 +10660,30 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } if (is_fp) { - /* low bit of size indicates single/double */ - size = extract32(size, 0, 1) ? 3 : 2; - if (size == 2) { + /* convert insn encoded size to TCGMemOp size */ + switch (size) { + case 0: /* half-precision */ + size = MO_16; + index = h << 2 | l << 1 | m; + break; + case 2: /* single precision */ + size = MO_32; index = h << 1 | l; - } else { + rm |= (m << 4); + break; + case 3: /* double precision */ + size = MO_64; if (l || !is_q) { unallocated_encoding(s); return; } index = h; + rm |= (m << 4); + break; + default: + g_assert_not_reached(); + break; } - rm |= (m << 4); } else { switch (size) { case 1: @@ -10805,10 +10817,23 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); break; case 0x9: /* FMUL, FMULX */ - if (u) { - gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); - } else { - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); + switch (size) { + case 1: + if (u) { + gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx, fpst); + } else { + g_assert_not_reached(); + } + break; + case 2: + if (u) { + gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); + } else { + gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); + } + break; + default: + g_assert_not_reached(); } break; case 0xc: /* SQDMULH */ From patchwork Fri Oct 13 16:24:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825599 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; 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Fri, 13 Oct 2017 09:32:05 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id f89sm2308145wmh.18.2017.10.13.09.31.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:32:03 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id B4D7D3E0DA9; Fri, 13 Oct 2017 17:24:39 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:26 +0100 Message-Id: <20171013162438.32458-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::232 Subject: [Qemu-devel] [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is just the decode skeleton which will be filled out by later patches. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d12106695f..11990daff4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10568,6 +10568,40 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } } +/* AdvSIMD two reg misc FP16 + * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 + * +---+---+---+-----------+---+-------------+--------+-----+------+------+ + * | 0 | 1 | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | + * +---+---+---+-----------+---+-------------+--------+-----+------+------+ + * mask: 1101 1111 0111 1110 0000 1100 0000 0000 0xdf7e 0c00 + * val: 0101 1110 0111 1000 0000 1000 0000 0000 0x5e78 0800 + * Half-precision variants of two-reg misc. + */ +static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) +{ + int fpop, opcode, a; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + opcode = extract32(insn, 12, 4); + a = extract32(insn, 23, 1); + fpop = deposit32(opcode, 5, 1, a); + + switch (fpop) { + default: + fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); + g_assert_not_reached(); + } + +} + /* AdvSIMD scalar x indexed element * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ @@ -11270,6 +11304,7 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, + { 0x5e780800, 0xdf7e0c00, disas_simd_two_reg_misc_fp16 }, { 0x00000000, 0x00000000, NULL } }; From patchwork Fri Oct 13 16:24:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825611 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 13 Oct 2017 17:24:39 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:27 +0100 Message-Id: <20171013162438.32458-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22c Subject: [Qemu-devel] [RFC PATCH 19/30] Fix mask for AdvancedSIMD 2 reg misc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" While the group encoding declares bit 28 a zero it is set for FCMGT (zero) Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 11990daff4..7792cea9f5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10571,10 +10571,10 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) /* AdvSIMD two reg misc FP16 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 * +---+---+---+-----------+---+-------------+--------+-----+------+------+ - * | 0 | 1 | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | + * | 0 | Q | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | * +---+---+---+-----------+---+-------------+--------+-----+------+------+ - * mask: 1101 1111 0111 1110 0000 1100 0000 0000 0xdf7e 0c00 - * val: 0101 1110 0111 1000 0000 1000 0000 0000 0x5e78 0800 + * mask: 1001 1111 0111 1110 0000 1100 0000 0000 0x9f7e 0c00 + * val: 0001 1110 0111 1000 0000 1000 0000 0000 0x1e78 0800 * Half-precision variants of two-reg misc. */ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) @@ -11304,7 +11304,7 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, - { 0x5e780800, 0xdf7e0c00, disas_simd_two_reg_misc_fp16 }, + { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, { 0x00000000, 0x00000000, NULL } }; @@ -11318,6 +11318,8 @@ static void disas_data_proc_simd(DisasContext *s, uint32_t insn) if (fn) { fn(s, insn); } else { + fprintf(stderr, "%s: failed to find %#4x @ %#" PRIx64 "\n", + __func__, insn, s->pc); unallocated_encoding(s); } } From patchwork Fri Oct 13 16:24:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825598 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="dBGKdtCu"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDD626DWzz9sRm for ; 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Fri, 13 Oct 2017 09:32:06 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id f84sm872845wme.44.2017.10.13.09.31.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:32:03 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id D771E3E0FA4; Fri, 13 Oct 2017 17:24:39 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:28 +0100 Message-Id: <20171013162438.32458-21-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is mostly a mechanical conversion of the float32 variants of the same name with some judicious search/replace and some constants changed. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 216 ++++++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 8 ++ 2 files changed, 224 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index ff967f5525..fdb2999c41 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3884,6 +3884,222 @@ float16 float16_div(float16 a, float16 b, float_status *status) } +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is equal to +| the corresponding value `b', and 0 otherwise. The invalid exception is +| raised if either operand is a NaN. Otherwise, the comparison is performed +| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_eq(float16 a, float16 b, float_status *status) +{ + uint32_t av, bv; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 0; + } + av = float16_val(a); + bv = float16_val(b); + return ( av == bv ) || ( (uint32_t) ( ( av | bv )<<1 ) == 0 ); +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is less than +| or equal to the corresponding value `b', and 0 otherwise. The invalid +| exception is raised if either operand is a NaN. The comparison is performed +| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_le(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 0; + } + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + av = float16_val(a); + bv = float16_val(b); + if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 ); + return ( av == bv ) || ( aSign ^ ( av < bv ) ); + +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is less than +| the corresponding value `b', and 0 otherwise. The invalid exception is +| raised if either operand is a NaN. The comparison is performed according +| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_lt(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 0; + } + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + av = float16_val(a); + bv = float16_val(b); + if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 ); + return ( av != bv ) && ( aSign ^ ( av < bv ) ); + +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point values `a' and `b' cannot +| be compared, and 0 otherwise. The invalid exception is raised if either +| operand is a NaN. The comparison is performed according to the IEC/IEEE +| Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_unordered(float16 a, float16 b, float_status *status) +{ + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + float_raise(float_flag_invalid, status); + return 1; + } + return 0; +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is equal to +| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an +| exception. The comparison is performed according to the IEC/IEEE Standard +| for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_eq_quiet(float16 a, float16 b, float_status *status) +{ + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 0; + } + return ( float16_val(a) == float16_val(b) ) || + ( (uint32_t) ( ( float16_val(a) | float16_val(b) )<<1 ) == 0 ); +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is less than or +| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not +| cause an exception. Otherwise, the comparison is performed according to the +| IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_le_quiet(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 0; + } + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + av = float16_val(a); + bv = float16_val(b); + if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 ); + return ( av == bv ) || ( aSign ^ ( av < bv ) ); + +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point value `a' is less than +| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an +| exception. Otherwise, the comparison is performed according to the IEC/IEEE +| Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_lt_quiet(float16 a, float16 b, float_status *status) +{ + flag aSign, bSign; + uint32_t av, bv; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 0; + } + aSign = extractFloat16Sign( a ); + bSign = extractFloat16Sign( b ); + av = float16_val(a); + bv = float16_val(b); + if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 ); + return ( av != bv ) && ( aSign ^ ( av < bv ) ); + +} + +/*---------------------------------------------------------------------------- +| Returns 1 if the half-precision floating-point values `a' and `b' cannot +| be compared, and 0 otherwise. Quiet NaNs do not cause an exception. The +| comparison is performed according to the IEC/IEEE Standard for Binary +| Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +int float16_unordered_quiet(float16 a, float16 b, float_status *status) +{ + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) ) + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) ) + ) { + if (float16_is_signaling_nan(a, status) + || float16_is_signaling_nan(b, status)) { + float_raise(float_flag_invalid, status); + } + return 1; + } + return 0; +} + /* Half precision floats come in two formats: standard IEEE and "ARM" format. The latter gains extra exponent range by omitting the NaN/Inf encodings. */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index f1d79b6d03..76a8310780 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -350,6 +350,14 @@ float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); float16 float16_mul(float16, float16, float_status *status); float16 float16_div(float16, float16, float_status *status); +int float16_eq(float16, float16, float_status *status); +int float16_le(float16, float16, float_status *status); +int float16_lt(float16, float16, float_status *status); +int float16_unordered(float16, float16, float_status *status); +int float16_eq_quiet(float16, float16, float_status *status); +int float16_le_quiet(float16, float16, float_status *status); +int float16_lt_quiet(float16, float16, float_status *status); +int float16_unordered_quiet(float16, float16, float_status *status); int float16_is_quiet_nan(float16, float_status *status); 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X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" I re-use the existing handle_2misc_fcmp_zero handler and tweak it slightly to deal with the half-precision case. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 39 +++++++++++++++++++++++++++++++++++++++ target/arm/helper-a64.h | 6 ++++++ target/arm/translate-a64.c | 25 ++++++++++++++++++------- 3 files changed, 63 insertions(+), 7 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index dd26675d5c..b62d77aec4 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -577,3 +577,42 @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) } return float16_mul(a, b, fpst); } + + +/* + * Floating point comparisons produce an integer result. + * Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires. + */ +uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + return -float16_eq_quiet(a, b, fpst); +} + +uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + return -float16_le(b, a, fpst); +} + +uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + return -float16_lt(b, a, fpst); +} + +uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + float16 f0 = float16_abs(a); + float16 f1 = float16_abs(b); + return -float16_le(f1, f0, fpst); +} + +/* uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) */ +/* { */ +/* float_status *fpst = fpstp; */ +/* float16 f0 = float16_abs(a); */ +/* float16 f1 = float16_abs(b); */ +/* return -float16_lt(f1, f0, fpst); */ +/* } */ diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 0f97eb607f..952869f43e 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -53,3 +53,9 @@ DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) + +DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7792cea9f5..623b0b3fab 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7785,6 +7785,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, TCGv_i32 tcg_res = tcg_temp_new_i32(); NeonGenTwoSingleOPFn *genfn; bool swap = false; + bool hp = (size == 1 ? true : false); int pass, maxpasses; switch (opcode) { @@ -7792,7 +7793,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, swap = true; /* fall through */ case 0x2c: /* FCMGT (zero) */ - genfn = gen_helper_neon_cgt_f32; + genfn = hp ? gen_helper_advsimd_cgt_f16 : gen_helper_neon_cgt_f32; break; case 0x2d: /* FCMEQ (zero) */ genfn = gen_helper_neon_ceq_f32; @@ -7814,7 +7815,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, } for (pass = 0; pass < maxpasses; pass++) { - read_vec_element_i32(s, tcg_op, rn, pass, MO_32); + read_vec_element_i32(s, tcg_op, rn, pass, hp ? MO_16 : MO_32); if (swap) { genfn(tcg_res, tcg_zero, tcg_op, fpst); } else { @@ -7823,7 +7824,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, if (is_scalar) { write_fp_sreg(s, rd, tcg_res); } else { - write_vec_element_i32(s, tcg_res, rd, pass, MO_32); + write_vec_element_i32(s, tcg_res, rd, pass, hp ? MO_16 : MO_32); } } tcg_temp_free_i32(tcg_res); @@ -9809,6 +9810,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x2: /* FADD */ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x6: /* FMAX */ + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x23: /* FMUL */ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10580,21 +10584,28 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) { int fpop, opcode, a; + int rn, rd; if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); return; } - if (!fp_access_check(s)) { - return; - } - opcode = extract32(insn, 12, 4); a = extract32(insn, 23, 1); fpop = deposit32(opcode, 5, 1, a); + rn = extract32(insn, 5, 5); + rd = extract32(insn, 0, 5); + switch (fpop) { + case 0x2c: /* FCMGT (zero) */ + case 0x2d: /* FCMEQ (zero) */ + case 0x2e: /* FCMLT (zero) */ + case 0x6c: /* FCMGE (zero) */ + case 0x6d: /* FCMLE (zero) */ + handle_2misc_fcmp_zero(s, fpop, true, 0, false, 1, rn, rd); + break; default: fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); From patchwork Fri Oct 13 16:24:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825588 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="YzvH0shK"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDCwL5v0Gz9s7c for ; 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X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 14 +++++++------- target/arm/helper-a64.h | 1 - target/arm/translate-a64.c | 3 +++ 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index b62d77aec4..137866732d 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -609,10 +609,10 @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp) return -float16_le(f1, f0, fpst); } -/* uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) */ -/* { */ -/* float_status *fpst = fpstp; */ -/* float16 f0 = float16_abs(a); */ -/* float16 f1 = float16_abs(b); */ -/* return -float16_lt(f1, f0, fpst); */ -/* } */ +uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + float16 f0 = float16_abs(a); + float16 f1 = float16_abs(b); + return -float16_lt(f1, f0, fpst); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 952869f43e..66c4062ea5 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -53,7 +53,6 @@ DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) - DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 623b0b3fab..4ad470d9e8 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9819,6 +9819,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x27: /* FDIV */ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x35: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; default: fprintf(stderr,"%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", __func__, insn, fpopcode, s->pc); From patchwork Fri Oct 13 16:24:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825596 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="OuxIJYlI"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDD4N4dCmz9sRm for ; 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X-Received-From: 2a00:1450:400c:c09::22c Subject: [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- fpu/softfloat-specialize.h | 52 +++++++ fpu/softfloat.c | 327 +++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 2 + 3 files changed, 381 insertions(+) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 2ccd4abe11..33c4be1757 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -728,6 +728,58 @@ static float16 propagateFloat16NaN(float16 a, float16 b, float_status *status) } } +/*---------------------------------------------------------------------------- +| Takes three half-precision floating-point values `a', `b' and `c', one of +| which is a NaN, and returns the appropriate NaN result. If any of `a', +| `b' or `c' is a signaling NaN, the invalid exception is raised. +| The input infzero indicates whether a*b was 0*inf or inf*0 (in which case +| obviously c is a NaN, and whether to propagate c or some other NaN is +| implementation defined). +*----------------------------------------------------------------------------*/ + +static float16 propagateFloat16MulAddNaN(float16 a, float16 b, + float16 c, flag infzero, + float_status *status) +{ + flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, + cIsQuietNaN, cIsSignalingNaN; + int which; + + aIsQuietNaN = float16_is_quiet_nan(a, status); + aIsSignalingNaN = float16_is_signaling_nan(a, status); + bIsQuietNaN = float16_is_quiet_nan(b, status); + bIsSignalingNaN = float16_is_signaling_nan(b, status); + cIsQuietNaN = float16_is_quiet_nan(c, status); + cIsSignalingNaN = float16_is_signaling_nan(c, status); + + if (aIsSignalingNaN | bIsSignalingNaN | cIsSignalingNaN) { + float_raise(float_flag_invalid, status); + } + + which = pickNaNMulAdd(aIsQuietNaN, aIsSignalingNaN, + bIsQuietNaN, bIsSignalingNaN, + cIsQuietNaN, cIsSignalingNaN, infzero, status); + + if (status->default_nan_mode) { + /* Note that this check is after pickNaNMulAdd so that function + * has an opportunity to set the Invalid flag. + */ + return float16_default_nan(status); + } + + switch (which) { + case 0: + return float16_maybe_silence_nan(a, status); + case 1: + return float16_maybe_silence_nan(b, status); + case 2: + return float16_maybe_silence_nan(c, status); + case 3: + default: + return float16_default_nan(status); + } +} + /*---------------------------------------------------------------------------- | Takes two single-precision floating-point values `a' and `b', one of which | is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a diff --git a/fpu/softfloat.c b/fpu/softfloat.c index fdb2999c41..f7473f97e3 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3884,6 +3884,333 @@ float16 float16_div(float16 a, float16 b, float_status *status) } +/*---------------------------------------------------------------------------- +| Returns the remainder of the half-precision floating-point value `a' +| with respect to the corresponding value `b'. The operation is performed +| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_rem(float16 a, float16 b, float_status *status) +{ + flag aSign, zSign; + int aExp, bExp, expDiff; + uint32_t aSig, bSig; + uint32_t q; + uint64_t aSig64, bSig64, q64; + uint32_t alternateASig; + int32_t sigMean; + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + + aSig = extractFloat32Frac( a ); + aExp = extractFloat32Exp( a ); + aSign = extractFloat32Sign( a ); + bSig = extractFloat32Frac( b ); + bExp = extractFloat32Exp( b ); + if ( aExp == 0xFF ) { + if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) { + return propagateFloat32NaN(a, b, status); + } + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + if ( bExp == 0xFF ) { + if (bSig) { + return propagateFloat32NaN(a, b, status); + } + return a; + } + if ( bExp == 0 ) { + if ( bSig == 0 ) { + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + normalizeFloat32Subnormal( bSig, &bExp, &bSig ); + } + if ( aExp == 0 ) { + if ( aSig == 0 ) return a; + normalizeFloat32Subnormal( aSig, &aExp, &aSig ); + } + expDiff = aExp - bExp; + aSig |= 0x00800000; + bSig |= 0x00800000; + if ( expDiff < 32 ) { + aSig <<= 8; + bSig <<= 8; + if ( expDiff < 0 ) { + if ( expDiff < -1 ) return a; + aSig >>= 1; + } + q = ( bSig <= aSig ); + if ( q ) aSig -= bSig; + if ( 0 < expDiff ) { + q = ( ( (uint64_t) aSig )<<32 ) / bSig; + q >>= 32 - expDiff; + bSig >>= 2; + aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q; + } + else { + aSig >>= 2; + bSig >>= 2; + } + } + else { + if ( bSig <= aSig ) aSig -= bSig; + aSig64 = ( (uint64_t) aSig )<<40; + bSig64 = ( (uint64_t) bSig )<<40; + expDiff -= 64; + while ( 0 < expDiff ) { + q64 = estimateDiv128To64( aSig64, 0, bSig64 ); + q64 = ( 2 < q64 ) ? q64 - 2 : 0; + aSig64 = - ( ( bSig * q64 )<<38 ); + expDiff -= 62; + } + expDiff += 64; + q64 = estimateDiv128To64( aSig64, 0, bSig64 ); + q64 = ( 2 < q64 ) ? q64 - 2 : 0; + q = q64>>( 64 - expDiff ); + bSig <<= 6; + aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q; + } + do { + alternateASig = aSig; + ++q; + aSig -= bSig; + } while ( 0 <= (int32_t) aSig ); + sigMean = aSig + alternateASig; + if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) { + aSig = alternateASig; + } + zSign = ( (int32_t) aSig < 0 ); + if ( zSign ) aSig = - aSig; + return normalizeRoundAndPackFloat32(aSign ^ zSign, bExp, aSig, status); +} + +/*---------------------------------------------------------------------------- +| Returns the result of multiplying the half-precision floating-point values +| `a' and `b' then adding 'c', with no intermediate rounding step after the +| multiplication. The operation is performed according to the IEC/IEEE +| Standard for Binary Floating-Point Arithmetic 754-2008. +| The flags argument allows the caller to select negation of the +| addend, the intermediate product, or the final result. (The difference +| between this and having the caller do a separate negation is that negating +| externally will flip the sign bit on NaNs.) +*----------------------------------------------------------------------------*/ + +float16 float16_muladd(float16 a, float16 b, float16 c, int flags, + float_status *status) +{ + flag aSign, bSign, cSign, zSign; + int aExp, bExp, cExp, pExp, zExp, expDiff; + uint32_t aSig, bSig, cSig; + flag pInf, pZero, pSign; + uint64_t pSig64, cSig64, zSig64; + uint32_t pSig; + int shiftcount; + flag signflip, infzero; + + a = float16_squash_input_denormal(a, status); + b = float16_squash_input_denormal(b, status); + c = float16_squash_input_denormal(c, status); + aSig = extractFloat16Frac(a); + aExp = extractFloat16Exp(a); + aSign = extractFloat16Sign(a); + bSig = extractFloat16Frac(b); + bExp = extractFloat16Exp(b); + bSign = extractFloat16Sign(b); + cSig = extractFloat16Frac(c); + cExp = extractFloat16Exp(c); + cSign = extractFloat16Sign(c); + + infzero = ((aExp == 0 && aSig == 0 && bExp == 0x1f && bSig == 0) || + (aExp == 0x1f && aSig == 0 && bExp == 0 && bSig == 0)); + + /* It is implementation-defined whether the cases of (0,inf,qnan) + * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN + * they return if they do), so we have to hand this information + * off to the target-specific pick-a-NaN routine. + */ + if (((aExp == 0xff) && aSig) || + ((bExp == 0xff) && bSig) || + ((cExp == 0xff) && cSig)) { + return propagateFloat16MulAddNaN(a, b, c, infzero, status); + } + + if (infzero) { + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + + if (flags & float_muladd_negate_c) { + cSign ^= 1; + } + + signflip = (flags & float_muladd_negate_result) ? 1 : 0; + + /* Work out the sign and type of the product */ + pSign = aSign ^ bSign; + if (flags & float_muladd_negate_product) { + pSign ^= 1; + } + pInf = (aExp == 0xff) || (bExp == 0xff); + pZero = ((aExp | aSig) == 0) || ((bExp | bSig) == 0); + + if (cExp == 0xff) { + if (pInf && (pSign ^ cSign)) { + /* addition of opposite-signed infinities => InvalidOperation */ + float_raise(float_flag_invalid, status); + return float16_default_nan(status); + } + /* Otherwise generate an infinity of the same sign */ + return packFloat16(cSign ^ signflip, 0xff, 0); + } + + if (pInf) { + return packFloat16(pSign ^ signflip, 0xff, 0); + } + + if (pZero) { + if (cExp == 0) { + if (cSig == 0) { + /* Adding two exact zeroes */ + if (pSign == cSign) { + zSign = pSign; + } else if (status->float_rounding_mode == float_round_down) { + zSign = 1; + } else { + zSign = 0; + } + return packFloat16(zSign ^ signflip, 0, 0); + } + /* Exact zero plus a denorm */ + if (status->flush_to_zero) { + float_raise(float_flag_output_denormal, status); + return packFloat16(cSign ^ signflip, 0, 0); + } + } + /* Zero plus something non-zero : just return the something */ + if (flags & float_muladd_halve_result) { + if (cExp == 0) { + normalizeFloat16Subnormal(cSig, &cExp, &cSig); + } + /* Subtract one to halve, and one again because roundAndPackFloat16 + * wants one less than the true exponent. + */ + cExp -= 2; + cSig = (cSig | 0x00800000) << 7; + return roundAndPackFloat16(cSign ^ signflip, cExp, cSig, true, status); + } + return packFloat16(cSign ^ signflip, cExp, cSig); + } + + if (aExp == 0) { + normalizeFloat16Subnormal(aSig, &aExp, &aSig); + } + if (bExp == 0) { + normalizeFloat16Subnormal(bSig, &bExp, &bSig); + } + + /* Calculate the actual result a * b + c */ + + /* Multiply first; this is easy. */ + /* NB: we subtract 0x7e where float16_mul() subtracts 0x7f + * because we want the true exponent, not the "one-less-than" + * flavour that roundAndPackFloat16() takes. + */ + pExp = aExp + bExp - 0x7e; + aSig = (aSig | 0x00800000) << 7; + bSig = (bSig | 0x00800000) << 8; + pSig64 = (uint64_t)aSig * bSig; + if ((int64_t)(pSig64 << 1) >= 0) { + pSig64 <<= 1; + pExp--; + } + + zSign = pSign ^ signflip; + + /* Now pSig64 is the significand of the multiply, with the explicit bit in + * position 62. + */ + if (cExp == 0) { + if (!cSig) { + /* Throw out the special case of c being an exact zero now */ + shift64RightJamming(pSig64, 32, &pSig64); + pSig = pSig64; + if (flags & float_muladd_halve_result) { + pExp--; + } + return roundAndPackFloat16(zSign, pExp - 1, + pSig, true, status); + } + normalizeFloat16Subnormal(cSig, &cExp, &cSig); + } + + cSig64 = (uint64_t)cSig << (62 - 23); + cSig64 |= LIT64(0x4000000000000000); + expDiff = pExp - cExp; + + if (pSign == cSign) { + /* Addition */ + if (expDiff > 0) { + /* scale c to match p */ + shift64RightJamming(cSig64, expDiff, &cSig64); + zExp = pExp; + } else if (expDiff < 0) { + /* scale p to match c */ + shift64RightJamming(pSig64, -expDiff, &pSig64); + zExp = cExp; + } else { + /* no scaling needed */ + zExp = cExp; + } + /* Add significands and make sure explicit bit ends up in posn 62 */ + zSig64 = pSig64 + cSig64; + if ((int64_t)zSig64 < 0) { + shift64RightJamming(zSig64, 1, &zSig64); + } else { + zExp--; + } + } else { + /* Subtraction */ + if (expDiff > 0) { + shift64RightJamming(cSig64, expDiff, &cSig64); + zSig64 = pSig64 - cSig64; + zExp = pExp; + } else if (expDiff < 0) { + shift64RightJamming(pSig64, -expDiff, &pSig64); + zSig64 = cSig64 - pSig64; + zExp = cExp; + zSign ^= 1; + } else { + zExp = pExp; + if (cSig64 < pSig64) { + zSig64 = pSig64 - cSig64; + } else if (pSig64 < cSig64) { + zSig64 = cSig64 - pSig64; + zSign ^= 1; + } else { + /* Exact zero */ + zSign = signflip; + if (status->float_rounding_mode == float_round_down) { + zSign ^= 1; + } + return packFloat16(zSign, 0, 0); + } + } + --zExp; + /* Normalize to put the explicit bit back into bit 62. */ + shiftcount = countLeadingZeros64(zSig64) - 1; + zSig64 <<= shiftcount; + zExp -= shiftcount; + } + if (flags & float_muladd_halve_result) { + zExp--; + } + + shift64RightJamming(zSig64, 32, &zSig64); + return roundAndPackFloat16(zSign, zExp, zSig64, true, status); +} + /*---------------------------------------------------------------------------- | Returns 1 if the half-precision floating-point value `a' is equal to | the corresponding value `b', and 0 otherwise. The invalid exception is diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 76a8310780..a7435e2a5b 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -350,6 +350,8 @@ float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); float16 float16_mul(float16, float16, float_status *status); float16 float16_div(float16, float16, float_status *status); +float16 float16_rem(float16, float16, float_status *status); +float16 float16_muladd(float16, float16, float16, int, float_status *status); int float16_eq(float16, float16, float_status *status); int float16_le(float16, float16, float_status *status); int float16_lt(float16, float16, float_status *status); From patchwork Fri Oct 13 16:24:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825603 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="EemdC4eI"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDD9L1r5Pz9sxR for ; Sat, 14 Oct 2017 03:45:26 +1100 (AEDT) Received: from localhost ([::1]:51135 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e335Q-0002fn-Af for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:45:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44100) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32se-0000e6-4e for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32sa-0002JA-H9 for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:12 -0400 Received: from mail-wr0-x236.google.com ([2a00:1450:400c:c0c::236]:46156) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32sa-0002II-6p for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:08 -0400 Received: by mail-wr0-x236.google.com with SMTP id l1so1446091wrc.3 for ; Fri, 13 Oct 2017 09:32:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eDKJf8QoZFlvtHit/EDPGrTfxs9RO/NiARjDvgLSZdE=; b=EemdC4eIlKD+6KHgvzwaXiLCzXqL1GZz2zmKR93jFffTBYbUN29ycJuHBz/APy5NhZ cYPbSjK/WU2byPsXNSfHMWaWCY7bZWpsIOgKUdn5+xqtzzvnQsdgsfMR7zT+WHe+QyFN 4kWlf9ehCry12IoNajRpWVWNMf8534Fj2llG8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eDKJf8QoZFlvtHit/EDPGrTfxs9RO/NiARjDvgLSZdE=; b=CkxrO+ocpQbV8HwXm04pJrIaKDQiJAToZmCvl8Ux/7NDfvsPblnLsDLeJFFveXiQcf eu+wU+fe17KsJ69gGaVr2mQFS2p6MPubMhlmZGG/XJyWDsUFaIem3kH7hCpclO3LG+LC LdMFZg8fhWKqcECOPVU7XQBRIwEchoVX1WFrhixSS4mjle09SS4m7HDp2/ABJYQgY7k3 jYYLtKejQU6WBcVn0kIx68M+hGwtPc5asK1gQupydXhExkeHq2VbKMk9pphD51CoGcRZ 5yOXAcLfUnbR6r0pv2TmQ5gpFiBTyME+8PslIIu8XUHhSwkjjnnWHNrzu9Bl+87IdM7B h3TQ== X-Gm-Message-State: AMCzsaXRzWYWelIJhhrMSijOmf/6DYIsCN7liXWCVSnVTDzFhnFq+P/s SS97iewLr4zgaUQHDMO16s3YEA== X-Google-Smtp-Source: AOwi7QCQCZO9DxeV9RPuJKZoGePElDfk5SZCXqPu1keiS5qC6MkWT/7GkOsz967weafGgbHqiTdPPg== X-Received: by 10.223.186.20 with SMTP id o20mr2221573wrg.3.1507912327116; Fri, 13 Oct 2017 09:32:07 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id b11sm2508099wrd.91.2017.10.13.09.32.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:32:03 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 311863E103D; Fri, 13 Oct 2017 17:24:40 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:32 +0100 Message-Id: <20171013162438.32458-25-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::236 Subject: [Qemu-devel] [RFC PATCH 24/30] disas_simd_indexed: support half-precision operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" A mild re-factoring of the !is_double leg to gracefully handle both single and half-precision operations. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 6 ++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 19 +++++++++++++------ 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 137866732d..241fee9d93 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -578,6 +578,12 @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) return float16_mul(a, b, fpst); } +/* fused multiply-accumulate */ +float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp) +{ + float_status *fpst = fpstp; + return float16_muladd(a, b, c, 0, fpst); +} /* * Floating point comparisons produce an integer result. diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 66c4062ea5..444d046500 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -53,6 +53,7 @@ DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) +DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4ad470d9e8..142b23abb5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10757,7 +10757,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) TCGV_UNUSED_PTR(fpst); } - if (size == 3) { + if (size == MO_64) { TCGv_i64 tcg_idx = tcg_temp_new_i64(); int pass; @@ -10802,11 +10802,12 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_idx); } else if (!is_long) { - /* 32 bit floating point, or 16 or 32 bit integer. + /* 16 or 32 bit floating point, or 16 or 32 bit integer. * For the 16 bit scalar case we use the usual Neon helpers and * rely on the fact that 0 op 0 == 0 with no side effects. */ TCGv_i32 tcg_idx = tcg_temp_new_i32(); + bool hp = (size == MO_16 ? true : false); int pass, maxpasses; if (is_scalar) { @@ -10829,7 +10830,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) TCGv_i32 tcg_op = tcg_temp_new_i32(); TCGv_i32 tcg_res = tcg_temp_new_i32(); - read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32); + read_vec_element_i32(s, tcg_op, rn, pass, size); switch (opcode) { case 0x0: /* MLA */ @@ -10861,8 +10862,14 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) gen_helper_vfp_negs(tcg_op, tcg_op); /* fall through */ case 0x1: /* FMLA */ - read_vec_element_i32(s, tcg_res, rd, pass, MO_32); - gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); + read_vec_element_i32(s, tcg_res, rd, pass, size); + if (hp) { + gen_helper_advsimd_muladdh(tcg_res, tcg_op, + tcg_idx, tcg_res, fpst); + } else { + gen_helper_vfp_muladds(tcg_res, tcg_op, + tcg_idx, tcg_res, fpst); + } break; case 0x9: /* FMUL, FMULX */ switch (size) { @@ -10909,7 +10916,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) if (is_scalar) { write_fp_sreg(s, rd, tcg_res); } else { - write_vec_element_i32(s, tcg_res, rd, pass, MO_32); + write_vec_element_i32(s, tcg_res, rd, pass, size); } tcg_temp_free_i32(tcg_op); From patchwork Fri Oct 13 16:24:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825606 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 13 Oct 2017 17:24:40 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:33 +0100 Message-Id: <20171013162438.32458-26-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::22e Subject: [Qemu-devel] [RFC PATCH 25/30] softfloat: float16_round_to_int X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Again a mechanical conversion. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 1 + 2 files changed, 83 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index f7473f97e3..dc7f5f6d88 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -3532,6 +3532,88 @@ static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr, *zExpPtr = 1 - shiftCount; } +/*---------------------------------------------------------------------------- +| Rounds the half-precision floating-point value `a' to an integer, +| and returns the result as a half-precision floating-point value. The +| operation is performed according to the IEC/IEEE Standard for Binary +| Floating-Point Arithmetic. +*----------------------------------------------------------------------------*/ + +float16 float16_round_to_int(float16 a, float_status *status) +{ + flag aSign; + int aExp; + uint16_t lastBitMask, roundBitsMask; + uint16_t z; + a = float16_squash_input_denormal(a, status); + + aExp = extractFloat16Exp( a ); + if ( 0x19 <= aExp ) { + if ( ( aExp == 0x1F ) && extractFloat16Frac( a ) ) { + return propagateFloat16NaN(a, a, status); + } + return a; + } + if ( aExp <= 0xE ) { + if ( (uint16_t) ( float16_val(a)<<1 ) == 0 ) return a; + status->float_exception_flags |= float_flag_inexact; + aSign = extractFloat16Sign( a ); + switch (status->float_rounding_mode) { + case float_round_nearest_even: + if ( ( aExp == 0xE ) && extractFloat16Frac( a ) ) { + return packFloat16( aSign, 0xF, 0 ); + } + break; + case float_round_ties_away: + if (aExp == 0xE) { + return packFloat16(aSign, 0xF, 0); + } + break; + case float_round_down: + return make_float16(aSign ? 0xBC00 : 0); + case float_round_up: + /* -0.0/1.0f */ + return make_float16(aSign ? 0x8000 : 0x3C00); + } + return packFloat16( aSign, 0, 0 ); + } + lastBitMask = 1; + lastBitMask <<= 0x19 - aExp; + roundBitsMask = lastBitMask - 1; + z = float16_val(a); + switch (status->float_rounding_mode) { + case float_round_nearest_even: + z += lastBitMask>>1; + if ((z & roundBitsMask) == 0) { + z &= ~lastBitMask; + } + break; + case float_round_ties_away: + z += lastBitMask >> 1; + break; + case float_round_to_zero: + break; + case float_round_up: + if (!extractFloat16Sign(make_float16(z))) { + z += roundBitsMask; + } + break; + case float_round_down: + if (extractFloat16Sign(make_float16(z))) { + z += roundBitsMask; + } + break; + default: + abort(); + } + z &= ~ roundBitsMask; + if (z != float16_val(a)) { + status->float_exception_flags |= float_flag_inexact; + } + return make_float16(z); + +} + /*---------------------------------------------------------------------------- | Returns the result of adding the absolute values of the half-precision | floating-point values `a' and `b'. If `zSign' is 1, the sum is negated diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index a7435e2a5b..856f67cf12 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -346,6 +346,7 @@ float64 float16_to_float64(float16 a, flag ieee, float_status *status); | Software half-precision operations. *----------------------------------------------------------------------------*/ +float16 float16_round_to_int(float16, float_status *status); float16 float16_add(float16, float16, float_status *status); float16 float16_sub(float16, float16, float_status *status); float16 float16_mul(float16, float16, float_status *status); From patchwork Fri Oct 13 16:24:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825592 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="MGKIdY1i"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDD1K73q4z9sxR for ; Sat, 14 Oct 2017 03:38:29 +1100 (AEDT) Received: from localhost ([::1]:51099 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32yh-0005Co-Ur for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:38:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43921) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32sU-0000UE-0u for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32sS-0002CR-Pi for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:02 -0400 Received: from mail-wm0-x232.google.com ([2a00:1450:400c:c09::232]:50728) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32sS-0002Bh-H8 for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:00 -0400 Received: by mail-wm0-x232.google.com with SMTP id u138so22538024wmu.5 for ; Fri, 13 Oct 2017 09:32:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xj+jn6t73JlhKSswsXO8P/txoe4iBUWKkNZdRIQnS9k=; b=MGKIdY1iQO2WSibuya8Ce0+JcD7wBMYXvYhghgBoedl8iNXMEy8xVUUqwtDhsj2sU9 jAKqndpmq9G7bsWzv4BsXZsyG1WXV0Ha/C1/+LF7B9atgLe+yOzvsvRCbBFdWcb5QzRD TpUKct/trgXSyrjTdyx68X/NXRTqmOG5qAcp4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xj+jn6t73JlhKSswsXO8P/txoe4iBUWKkNZdRIQnS9k=; b=sg5M/d7fOOtuBc9onxtK+7J/MBYT4uj11HI5rHBy0wj3efbK5xwjsvoZzi1Jr0uNFH WLKlHRto8ANnCyO0TA2hZmQm+VDE7fogJwcKfD63jiwSlDzmLfjiKcN6CPgsatZTVyaX prxTcReQD6Jc169vcwYHcyNtCc9klx3V3of1hsZLi5PE8ZbUJzT+RRt6r9JYduUdppaV YRXPRhAy+LAB7v0OFkbbzJSNVD7aqVHNFKVs3ClIN3fCDItkUfYiyo3dHV8ig6pmDdH5 p7d85mjBaWlUDlI39t091XHv1u0nySgMUwT+xJpeqZ0zc3rBVJmxUQ0MLR+66H50wgRx bQnA== X-Gm-Message-State: AMCzsaXU0U/SGa1iuYT6S0IMLwl5TjrwCDbI9s7v+hfNlGNNGmAhVyGF cC0HOsXUtWuuyiWXpV5t2+QJiw== X-Google-Smtp-Source: ABhQp+TTkBU6DzKqJxfTrPJuLJYwLlnyV+sffoc77Oy3TDtsVi36ytdzLdtv55JIVG/MrbvAYi+ZMA== X-Received: by 10.28.24.7 with SMTP id 7mr2146789wmy.78.1507912319374; Fri, 13 Oct 2017 09:31:59 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id n19sm1941695wrn.52.2017.10.13.09.31.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:31:58 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 553483E10E9; Fri, 13 Oct 2017 17:24:40 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:34 +0100 Message-Id: <20171013162438.32458-27-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::232 Subject: [Qemu-devel] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This is a simple pattern based framework for testing our softfloat implementation. It is easier to use while debugging softfloat itself than indirectly with a tool like risu. As the softfloat library is built against given targets we need a version per target architecture we build. Signed-off-by: Alex Bennée --- tests/Makefile.include | 8 ++++++- tests/test-softfloat.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 1 deletion(-) create mode 100644 tests/test-softfloat.c diff --git a/tests/Makefile.include b/tests/Makefile.include index 4ca15e6817..8bf1dfd19a 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -156,6 +156,10 @@ check-unit-y += tests/ptimer-test$(EXESUF) gcov-files-ptimer-test-y = hw/core/ptimer.c check-unit-y += tests/test-qapi-util$(EXESUF) gcov-files-test-qapi-util-y = qapi/qapi-util.c +check-unit-y += tests/test-softfloat$(EXESUF) +gcov-files-test-softfloat-y = fpu/softfloat.c +check-unit-y += tests/test-softfloat-aarch64$(EXESUF) +gcov-files-test-softfloat-aarch64-y = fpu/softfloat.c check-block-$(CONFIG_POSIX) += tests/qemu-iotests-quick.sh @@ -555,7 +559,7 @@ test-obj-y = tests/check-qnum.o tests/check-qstring.o tests/check-qdict.o \ tests/rcutorture.o tests/test-rcu-list.o \ tests/test-qdist.o tests/test-shift128.o \ tests/test-qht.o tests/qht-bench.o tests/test-qht-par.o \ - tests/atomic_add-bench.o + tests/atomic_add-bench.o tests/test-softfloat.o $(test-obj-y): QEMU_INCLUDES += -Itests QEMU_CFLAGS += -I$(SRC_PATH)/tests @@ -604,6 +608,8 @@ tests/test-qht-par$(EXESUF): tests/test-qht-par.o tests/qht-bench$(EXESUF) $(tes tests/qht-bench$(EXESUF): tests/qht-bench.o $(test-util-obj-y) tests/test-bufferiszero$(EXESUF): tests/test-bufferiszero.o $(test-util-obj-y) tests/atomic_add-bench$(EXESUF): tests/atomic_add-bench.o $(test-util-obj-y) +tests/test-softfloat$(EXESUF): tests/test-softfloat.o $(BUILD_DIR)/aarch64-softmmu/fpu/softfloat.o +tests/test-softfloat-aarch64$(EXESUF): tests/test-softfloat.o $(BUILD_DIR)/aarch64-softmmu/fpu/softfloat.o tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ diff --git a/tests/test-softfloat.c b/tests/test-softfloat.c new file mode 100644 index 0000000000..d7b740e1cb --- /dev/null +++ b/tests/test-softfloat.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017, Linaro + * Author: Alex Bennée + * + * License: GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "fpu/softfloat.h" + +typedef struct { + float_status initial_status; + float16 in; + float16 out; + uint8_t final_exception_flags; +} f16_test_data; + +static void test_f16_round_to_int(void) +{ + int i; + float16 out; + float_status flags, *fp = &flags; + f16_test_data test_data[] = { + { { /* defaults */ }, 0x87FF, 0x8000 }, + { { /* defaults */ }, 0xE850, 0xE850 }, + { { /* defaults */ }, 0x0000, 0x0000 }, + { { /* defaults */ }, 0x857F, 0x8000 }, + { { /* defaults */ }, 0x74FB, 0x74FB }, + /* from risu 3b4: 4ef98945 frintp v5.8h, v10.8h */ + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x06b1, 0x3c00, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x6966, 0x6966, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x83c0, 0x8000, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xa619, 0x8000, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x9cf4, 0x8000, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xee11, 0xee11, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xee5c, 0xee5c, 0 }, + { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x8004, 0x8000, 0 } + }; + + for (i = 0; i < ARRAY_SIZE(test_data); ++i) { + flags = test_data[i].initial_status; + out = float16_round_to_int(test_data[i].in, fp); + + if (!(test_data[i].out == out)) { + fprintf(stderr, "%s[%d]: expected %#04x got %#04x\n", + __func__, i, test_data[i].out, out); + g_test_fail(); + } + } +} + +int main(int argc, char *argv[]) +{ + g_test_init(&argc, &argv, NULL); + g_test_add_func("/softfloat/f16/round_to_int", test_f16_round_to_int); + return g_test_run(); +} From patchwork Fri Oct 13 16:24:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825602 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; 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X-Received-From: 2a00:1450:400c:c0c::22f Subject: [Qemu-devel] [RFC PATCH 27/30] target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 17 ++++++++++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 74 insertions(+) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 241fee9d93..63b2bbd4b2 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -585,6 +585,23 @@ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp) return float16_muladd(a, b, c, 0, fpst); } +/* round to integral */ +float16 HELPER(advsimd_rinth)(float16 x, void *fp_status) +{ + int old_flags = get_float_exception_flags(fp_status), new_flags; + float16 ret; + + ret = float16_round_to_int(x, fp_status); + + /* Suppress any inexact exceptions the conversion produced */ + if (!(old_flags & float_flag_inexact)) { + new_flags = get_float_exception_flags(fp_status); + set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); + } + + return ret; +} + /* * Floating point comparisons produce an integer result. * Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires. diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 444d046500..ce36d81091 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -59,3 +59,4 @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) +DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 142b23abb5..bbc0d96f01 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10588,6 +10588,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) { int fpop, opcode, a; int rn, rd; + int is_q; + int pass; + TCGv_i32 tcg_rmode; + TCGv_ptr tcg_fpstatus; + bool need_rmode = false; + int rmode; if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); @@ -10608,12 +10614,62 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6c: /* FCMGE (zero) */ case 0x6d: /* FCMLE (zero) */ handle_2misc_fcmp_zero(s, fpop, true, 0, false, 1, rn, rd); + return; + break; + case 0x28: /* FRINTP */ + need_rmode = true; + rmode = FPROUNDING_POSINF; break; default: fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); } + is_q = extract32(insn, 30, 1); + + if (!fp_access_check(s)) { + return; + } + + tcg_fpstatus = get_fpstatus_ptr(); + + if (need_rmode) { + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + } else { + TCGV_UNUSED_I32(tcg_rmode); + } + + for (pass = 0; pass < (is_q ? 8 : 4); pass++) { + TCGv_i32 tcg_op = tcg_temp_new_i32(); + TCGv_i32 tcg_res = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, pass, MO_16); + + switch (fpop) { + case 0x28: /* FRINTP */ + gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); + break; + default: + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op); + } + + if (!is_q) { + clear_vec_high(s, rd); + } + + if (need_rmode) { + gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + tcg_temp_free_i32(tcg_rmode); + } + + tcg_temp_free_ptr(tcg_fpstatus); } /* AdvSIMD scalar x indexed element From patchwork Fri Oct 13 16:24:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825604 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="QpCpnp+V"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDDBw6v25z9t0F for ; Sat, 14 Oct 2017 03:46:48 +1100 (AEDT) Received: from localhost ([::1]:51146 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e336l-0003ov-3N for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:46:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32sf-0000et-FZ for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32sd-0002MN-BK for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:13 -0400 Received: from mail-wr0-x233.google.com ([2a00:1450:400c:c0c::233]:48755) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32sd-0002Lc-1n for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:11 -0400 Received: by mail-wr0-x233.google.com with SMTP id u5so1438455wrc.5 for ; Fri, 13 Oct 2017 09:32:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FnDwdoES4ku0h3pXwWjXAGZvZqvV94B8hZzSSyJtYDE=; b=QpCpnp+VtC5845d7SZcanX9+acqq03p+vYqKSjZKfer4dPw8aRewPC+cqS1p91d6tn 7ASeuOBaAOsfWx0uW7DGp9duwsqczL6hwKN3cfOgMaIK006dweD2SvOfTlTHu2t8K8WO 9ij+3g62gmb8GktJFnqgw67UOe4f9j6tn1RqM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FnDwdoES4ku0h3pXwWjXAGZvZqvV94B8hZzSSyJtYDE=; b=ZNLtViIxXCUAZYLLjK7/buY2DnaQ61T1ZhUfJRjWuIsI0tQseeo5GTTGsNeu4TnSXL DpCDU2s18fItg5BrWO4WEazVFPXjJ1ycuZC6ZiX6vvHENojaK5NhBPelijHPSVw3c3Vn 5l6Ggm12k9/1OBgA+XkQoZ+4irqaJwKg2+HyRv4ClrHEhPqVjRCCZTRWOn9VZ6lgJhZo iA/fv4XuzFX8IkLUB3fCxuf1rm+FuHCOGtzTa358k3W0jWfaoXxDKxNfwHsFCmDPtYa2 ZoOrARPHGMsjkJtWWpH4sKEoDo+VbHS0CxuR4IGCW+PDwtixZSyMjLTZbttrehIV/KXp /vzw== X-Gm-Message-State: AMCzsaUAHmq5izvZg581bYfZKrXzqY2GPAbnpOFwbchHzN8UQZnoNGMw aiTm9jeao+v14vyQIptnlS87NQ== X-Google-Smtp-Source: AOwi7QBpuotcI6QUuYQm5VtRckgV/R+UYSEKdwOPFO84nR5RsMWjyrdkfzWH1lLOkC81LouCphSN/Q== X-Received: by 10.223.157.30 with SMTP id k30mr1770315wre.159.1507912329908; Fri, 13 Oct 2017 09:32:09 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id p49sm166948wrc.61.2017.10.13.09.32.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:32:03 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 7A9AD3E1337; Fri, 13 Oct 2017 17:24:40 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:36 +0100 Message-Id: <20171013162438.32458-29-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::233 Subject: [Qemu-devel] [RFC PATCH 28/30] softfloat: float16_to_int16 conversion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org, Aurelien Jarno Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" I didn't have another reference for this so I wrote it from first principles. The roundAndPackInt16 works with the same shifted input as roundAndPacknt32 but with different constants for invalid testing for overflow. Signed-off-by: Alex Bennée --- fpu/softfloat.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 1 + 2 files changed, 99 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index dc7f5f6d88..63f7cd1226 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -132,6 +132,62 @@ static inline flag extractFloat16Sign(float16 a) return float16_val(a)>>15; } +/*---------------------------------------------------------------------------- +| Takes a 32-bit fixed-point value `absZ' with binary point between bits 6 +| and 7, and returns the properly rounded 16-bit integer corresponding to the +| input. If `zSign' is 1, the input is negated before being converted to an +| integer. Bit 31 of `absZ' must be zero. Ordinarily, the fixed-point input +| is simply rounded to an integer, with the inexact exception raised if the +| input cannot be represented exactly as an integer. However, if the fixed- +| point input is too large, the invalid exception is raised and the largest +| positive or negative integer is returned. +*----------------------------------------------------------------------------*/ + +static int16_t roundAndPackInt16(flag zSign, uint32_t absZ, float_status *status) +{ + int8_t roundingMode; + flag roundNearestEven; + int8_t roundIncrement, roundBits; + int16_t z; + + roundingMode = status->float_rounding_mode; + roundNearestEven = ( roundingMode == float_round_nearest_even ); + + switch (roundingMode) { + case float_round_nearest_even: + case float_round_ties_away: + roundIncrement = 0x40; + break; + case float_round_to_zero: + roundIncrement = 0; + break; + case float_round_up: + roundIncrement = zSign ? 0 : 0x7f; + break; + case float_round_down: + roundIncrement = zSign ? 0x7f : 0; + break; + default: + abort(); + } + roundBits = absZ & 0x7F; + + absZ = ( absZ + roundIncrement )>>7; + absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven ); + z = absZ; + if ( zSign ) z = - z; + + if ( ( absZ>>16 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) { + float_raise(float_flag_invalid, status); + return zSign ? (int16_t) 0x8000 : 0x7FFF; + } + if (roundBits) { + status->float_exception_flags |= float_flag_inexact; + } + return z; + +} + /*---------------------------------------------------------------------------- | Takes a 64-bit fixed-point value `absZ' with binary point between bits 6 | and 7, and returns the properly rounded 32-bit integer corresponding to the @@ -4509,6 +4565,48 @@ int float16_unordered_quiet(float16 a, float16 b, float_status *status) return 0; } +/*---------------------------------------------------------------------------- +| Returns the result of converting the half-precision floating-point value +| `a' to the 16-bit two's complement integer format. The conversion is +| performed according to the IEC/IEEE Standard for Binary Floating-Point +| Arithmetic---which means in particular that the conversion is rounded +| according to the current rounding mode. If `a' is a NaN, the largest +| positive integer is returned. Otherwise, if the conversion overflows, the +| largest integer with the same sign as `a' is returned. +*----------------------------------------------------------------------------*/ + +int16_t float16_to_int16(float32 a, float_status *status) +{ + flag aSign; + int aExp; + uint32_t aSig; + + a = float16_squash_input_denormal(a, status); + aSig = extractFloat16Frac( a ); + aExp = extractFloat16Exp( a ); + aSign = extractFloat16Sign( a ); + if ( ( aExp == 0x1F ) && aSig ) aSign = 0; + if ( aExp ) aSig |= 0x0400; /* implicit bit */ + + /* At this point the binary point is between 10:9, we need to + * shift the significand it up by the +ve exponent to get the + * integer and then move the binary point down to the 7:6 for + * the final roundAnPackInt16. + * + * Even with the maximum +ve shift everything happily fits in the + * 32 bit aSig. + */ + aExp -= 15; /* exp bias */ + if (aExp >= 3) { + aSig <<= aExp - 3; + } else { + /* ensure small numbers still get rounded */ + shift32RightJamming( aSig, 3 - aExp, &aSig ); + } + + return roundAndPackInt16(aSign, aSig, status); +} + /* Half precision floats come in two formats: standard IEEE and "ARM" format. The latter gains extra exponent range by omitting the NaN/Inf encodings. */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 856f67cf12..49517b19ea 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -338,6 +338,7 @@ static inline float64 uint16_to_float64(uint16_t v, float_status *status) | Software half-precision conversion routines. *----------------------------------------------------------------------------*/ float16 float32_to_float16(float32, flag, float_status *status); +int16_t float16_to_int16(float32 a, float_status *status); float32 float16_to_float32(float16, flag, float_status *status); float16 float64_to_float16(float64 a, flag ieee, float_status *status); float64 float16_to_float64(float16 a, flag ieee, float_status *status); From patchwork Fri Oct 13 16:24:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825597 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ftQ3Yj/O"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yDD5g0fxbz9sRm for ; Sat, 14 Oct 2017 03:42:15 +1100 (AEDT) Received: from localhost ([::1]:51122 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e332L-00008p-3z for incoming@patchwork.ozlabs.org; Fri, 13 Oct 2017 12:42:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43970) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e32sW-0000XU-LD for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e32sV-0002Eo-S6 for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:04 -0400 Received: from mail-wm0-x236.google.com ([2a00:1450:400c:c09::236]:56887) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e32sV-0002Ds-Ml for qemu-devel@nongnu.org; Fri, 13 Oct 2017 12:32:03 -0400 Received: by mail-wm0-x236.google.com with SMTP id l68so22848263wmd.5 for ; Fri, 13 Oct 2017 09:32:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nMItd6ppJG4aBRKRJCZvCu1LGWnUChKl21uE6WyTYsM=; b=ftQ3Yj/ObfoUA6zuznR+2Kk1IbRay9rODjvbuqtGMs7KUcNY1sAlXF9+8y2EcxjJp1 JgpNzVIIenPpV6LTWl+KpR5uBs/iaGVHWiq5I0SFADCdFeSqyR8w9Ed31z2kaeeTWv+1 PaRDaUIeg5hNPaPIZKptR53YnJF1C54sMmZJI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nMItd6ppJG4aBRKRJCZvCu1LGWnUChKl21uE6WyTYsM=; b=boz7J6MZmwCFqD/jnFxmjhZw/AGkOF/DkOd4mQb2roYd73bePbYt0/cRyuHSXP40ZX QLj5RWgSfga/9y2ya4DO+le5aBqV7NFowlnduF2iTpkUddi7LlFvg3Ibnqy0fn9P4Y/M CQrkzN24zrxMzt4x0Vk4tDlT1iggRzx65t4+3DF15n4jz6I6L7ZrTHmVud24EdElOCzU NvdvifQmLSYZFYT7Ph4fiWW+G7DgJBNSC1PHUR0eXKr1mJNizsP/7q3xpXV+rJdhx1PX H3rLztIHzZYuJjp7tmvluDFNKmgDvnyXcYuv+7yO9RNLXnYt6B4r/msdS8kr8pDMvk3e wjFg== X-Gm-Message-State: AMCzsaXYJJeBNKnEsRJJTxUwcZ/AMs+hMkLGtn5/BN58224/n6z475Gu MJP8Ou13pcjquMVQchBCr5SnXg== X-Google-Smtp-Source: ABhQp+QibdNXCgwMG8/4sF8p63jO+m4PJ4an87WqhN2fPRiRAvywIcRg/IamvFU3ZzhRs8Ee7/UXWw== X-Received: by 10.28.146.20 with SMTP id u20mr2136494wmd.49.1507912321829; Fri, 13 Oct 2017 09:32:01 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id g26sm1978426wra.14.2017.10.13.09.31.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 09:31:58 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 8B69A3E138C; Fri, 13 Oct 2017 17:24:40 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:37 +0100 Message-Id: <20171013162438.32458-30-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- tests/test-softfloat.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tests/test-softfloat.c b/tests/test-softfloat.c index d7b740e1cb..e1f356572d 100644 --- a/tests/test-softfloat.c +++ b/tests/test-softfloat.c @@ -16,6 +16,31 @@ typedef struct { uint8_t final_exception_flags; } f16_test_data; +static void test_f16_convert_to_int(void) +{ + int i; + float16 out; + float_status flags, *fp = &flags; + f16_test_data test_data[] = { + /* from risu fcvtps v23.4h, v16.4h */ + { { .float_rounding_mode = float_round_up}, 0xa619, 0xb860, 0 }, + { { .float_rounding_mode = float_round_up}, 0x83c0, 0xff91, 0 }, + { { .float_rounding_mode = float_round_up}, 0x6966, 0x0001, 0 }, + { { .float_rounding_mode = float_round_up}, 0x06b1, 0x0001, 0 }, + }; + + for (i = 0; i < ARRAY_SIZE(test_data); ++i) { + flags = test_data[i].initial_status; + out = float16_to_int16(test_data[i].in, fp); + + if (!(test_data[i].out == out)) { + fprintf(stderr, "%s[%d]: expected %#04x got %#04x\n", + __func__, i, test_data[i].out, out); + g_test_fail(); + } + } +} + static void test_f16_round_to_int(void) { int i; @@ -54,5 +79,6 @@ int main(int argc, char *argv[]) { g_test_init(&argc, &argv, NULL); g_test_add_func("/softfloat/f16/round_to_int", test_f16_round_to_int); + g_test_add_func("/softfloat/f16/convert_to_int", test_f16_convert_to_int); return g_test_run(); } From patchwork Fri Oct 13 16:24:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 825609 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; 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Fri, 13 Oct 2017 17:24:40 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: richard.henderson@linaro.org Date: Fri, 13 Oct 2017 17:24:38 +0100 Message-Id: <20171013162438.32458-31-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org> References: <20171013162438.32458-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [RFC PATCH 30/30] target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn?= =?utf-8?b?w6ll?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 20 ++++++++++++++++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 7 +++++++ 3 files changed, 28 insertions(+) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 63b2bbd4b2..1cc2758eac 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -639,3 +639,23 @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) float16 f1 = float16_abs(b); return -float16_lt(f1, f0, fpst); } + +/* + * Half-precision floating point conversion functions + * + * There are a multitude of conversion functions with various + * different rounding modes. This is dealt with by the calling code + * setting the mode appropriately before calling the helper. + */ + +uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp) +{ + float_status *fpst = fpstp; + + /* Invalid if we are passed a NaN */ + if (float16_is_any_nan(a)) { + float_raise(float_flag_invalid, fpst); + return 0; + } + return float16_to_int16(a, fpst); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index ce36d81091..73a985d1a4 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -60,3 +60,4 @@ DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) +DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bbc0d96f01..ac71911a1a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10620,6 +10620,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) need_rmode = true; rmode = FPROUNDING_POSINF; break; + case 0x2a: /* FCVTPS */ + need_rmode = true; + rmode = FPROUNDING_POSINF; + break; default: fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); @@ -10647,6 +10651,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) read_vec_element_i32(s, tcg_op, rn, pass, MO_16); switch (fpop) { + case 0x2a: /* FCVTPS */ + gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x28: /* FRINTP */ gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); break;