From patchwork Fri Oct 13 15:18:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 825514 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yDBF85R5Sz9t0F for ; Sat, 14 Oct 2017 02:18:36 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 650D5C21FF6; Fri, 13 Oct 2017 15:18:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 30248C21F7F; Fri, 13 Oct 2017 15:18:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 79B5DC21FB6; Fri, 13 Oct 2017 15:18:26 +0000 (UTC) Received: from smtprelay.synopsys.com (smtprelay4.synopsys.com [198.182.47.9]) by lists.denx.de (Postfix) with ESMTPS id B46C3C21F7F for ; Fri, 13 Oct 2017 15:18:25 +0000 (UTC) Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id 7E3A524E0B67; Fri, 13 Oct 2017 08:18:23 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 69B1FB7B; Fri, 13 Oct 2017 08:18:23 -0700 (PDT) Received: from localhost.internal.synopsys.com (unknown [10.121.8.106]) by mailhost.synopsys.com (Postfix) with ESMTP id 942C3B56; Fri, 13 Oct 2017 08:18:20 -0700 (PDT) From: Eugeniy Paltsev To: Jagan Teki Date: Fri, 13 Oct 2017 18:18:17 +0300 Message-Id: <20171013151817.4588-1-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.9.3 Cc: u-boot@lists.denx.de, Eugeniy Paltsev , uboot-snps-arc@synopsys.com Subject: [U-Boot] [PATCH v2] DW SPI: Get clock value from Device Tree X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add option to set spi controller clock frequency via device tree using standard clock bindings. Old way of setting spi controller clock frequency (via implementation of 'cm_get_spi_controller_clk_hz' function in platform specific code) remains supported for backward compatibility. Signed-off-by: Eugeniy Paltsev --- Changes v1->v2: * disable clock if we can't get the rate. * get rid of cm_get_spi_controller_clk_hz weak declaration. drivers/spi/designware_spi.c | 65 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c index 5aa507b..9eb5b1c 100644 --- a/drivers/spi/designware_spi.c +++ b/drivers/spi/designware_spi.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -18,7 +19,10 @@ #include #include #include +/* Only SOCFPGA_GEN5 and SOCFPGA_ARRIA10 uses their clock_manager functions */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) || defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -94,6 +98,7 @@ struct dw_spi_priv { void __iomem *regs; unsigned int freq; /* Default frequency */ unsigned int mode; + unsigned long bus_clk_rate; int bits_per_word; u8 cs; /* chip select pin */ @@ -176,14 +181,72 @@ static void spi_hw_init(struct dw_spi_priv *priv) debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); } +static int dw_spi_of_get_clk(struct udevice *bus) +{ +#if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK) + struct dw_spi_priv *priv = dev_get_priv(bus); + struct clk clk; + int ret; + + ret = clk_get_by_index(bus, 0, &clk); + if (ret) + return -EINVAL; + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) + return ret; + + priv->bus_clk_rate = clk_get_rate(&clk); + if (!priv->bus_clk_rate) { + clk_disable(&clk); + return -EINVAL; + } + + clk_free(&clk); + + return 0; +#else + return -ENOSYS; +#endif +} + +static int dw_spi_get_clk(struct udevice *bus) +{ + struct dw_spi_priv *priv = dev_get_priv(bus); + + /* Firstly try to get clock frequency from device tree */ + if (!dw_spi_of_get_clk(bus)) + return 0; + + /* + * SOCFPGA_GEN5 and SOCFPGA_ARRIA10 uses cm_get_spi_controller_clk_hz + * function (defined in asm/arch/clock_manager.h) to get spi controller + * clock frequency. So in case of get clock frequency from device + * tree failure rollback to cm_get_spi_controller_clk_hz + */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) || defined(CONFIG_TARGET_SOCFPGA_ARRIA10) + priv->bus_clk_rate = cm_get_spi_controller_clk_hz(); +#endif + + if (!priv->bus_clk_rate) + return -EINVAL; + + return 0; +} + static int dw_spi_probe(struct udevice *bus) { struct dw_spi_platdata *plat = dev_get_platdata(bus); struct dw_spi_priv *priv = dev_get_priv(bus); + int ret; priv->regs = plat->regs; priv->freq = plat->frequency; + ret = dw_spi_get_clk(bus); + if (ret) + return ret; + /* Currently only bits_per_word == 8 supported */ priv->bits_per_word = 8; @@ -369,7 +432,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed) spi_enable_chip(priv, 0); /* clk_div doesn't support odd number */ - clk_div = cm_get_spi_controller_clk_hz() / speed; + clk_div = priv->bus_clk_rate / speed; clk_div = (clk_div + 1) & 0xfffe; dw_writel(priv, DW_SPI_BAUDR, clk_div);