From patchwork Fri Dec 7 15:44:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 1009526 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-491897-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="SXQMFpmP"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43BGxX3Q5Kz9s3l for ; Sat, 8 Dec 2018 02:44:47 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=QLOKGD8Vwol46n7nMQWnrpS6+2q0vlfXlOufswdAF8V oNY2UmyOh7/KxC6rMQpRJ2TGs6rJeRM4CWXpjrlvJAYTinSB3M0Cl2xIW+TdWtw6 KbGnhRqIU7oiyUhHy6rm/Jkgatq0lhtbwARQOjUUmrVCGkjpNaRtkOVWeoTEfLgM = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=v1VAFbfjdTztKPtkiapQLKk839s=; b=SXQMFpmPCIGgRRa5J NNB8YhdlYGJz/yIfwNHvuf6dD3sC66D7ywUYR4UVm3lvcDcatRG94jeEIu4qBz3N O+PV3E2QPDd2iZSrZ/rsfm5apzT9uLYceeylOo1eBUyxa0+sJoTIzD35BL68p5MC qkvYTV/3P8qLmUkXkLfuz+e3F0= Received: (qmail 96260 invoked by alias); 7 Dec 2018 15:44:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 96231 invoked by uid 89); 7 Dec 2018 15:44:38 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH autolearn=ham version=3.3.2 spammy=investigations, aim, tuning, Advanced X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 07 Dec 2018 15:44:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 762FA15AB; Fri, 7 Dec 2018 07:44:33 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 82A3E3F575; Fri, 7 Dec 2018 07:44:32 -0800 (PST) Message-ID: <5C0A955E.6040904@foss.arm.com> Date: Fri, 07 Dec 2018 15:44:30 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: "Richard Earnshaw (lists)" , James Greenhalgh , Marcus Shawcroft , Richard Sandiford Subject: [PATCH][AArch64][1/2] Implement TARGET_ESTIMATED_POLY_VALUE Hi all, The hook TARGET_ESTIMATED_POLY_VALUE allows a target to give an estimate for a poly_int run-time value. It is used exclusively in tuning decisions, things like estimated loop iterations, probabilities etc. It is not relied on for correctness. If we know the SVE width implemented in hardware we can make more more informed decisions in the implementation of TARGET_ESTIMATED_POLY_VALUE, even when compiling for VLA vectorisation. This patch adds an sve_width field to our tuning structs and sets it for the current CPU tunings. A new value is introduced to the aarch64_sve_vector_bits_enum enum that indicates that SVE is not available: SVE_NOT_IMPLEMENTED. I set it to the same value as SVE_SCALABLE so that parts of the aarch64 backend that follow the pattern: if (vector_width == SVE_SCALABLE) do_vla_friendly_action () else assume_specific_width_for_correctness () continue to work without change, but the CPU tuning structs can use a more appropriate moniker for indicating the absence of SVE. This sets sve_width to SVE_NOT_IMPLEMENTED for all cores. I aim to add an -moverride switch in the next patch that allows a power user to experiment with different values of it for investigations. Bootstrapped and tested on aarch64-none-linux-gnu. Thanks, Kyrill 2018-12-07 Kyrylo Tkachov * config/aarch64/aarch64-opts.h (aarch64_sve_vector_bits_enum): Add SVE_NOT_IMPLEMENTED value. * config/aarch64/aarch64-protos.h (struct tune_params): Add sve_width field. * config/aarch64/aarch64.c (generic_tunings,cortexa35_tunings, cortexa53_tunings, cortexa57_tunings, cortexa72_tunings, cortexa73_tunings, exynosm1_tunings, thunderx_tunings, thunderx_tunings, tsv110_tunings, xgene1_tunings, qdf24xx_tunings, saphira_tunings, thunderx2t99_tunings, emag_tunings): Specify sve_width. (aarch64_estimated_poly_value): Define. (TARGET_ESTIMATED_POLY_VALUE): Define. diff --git a/gcc/config/aarch64/aarch64-opts.h b/gcc/config/aarch64/aarch64-opts.h index 9d44a598967cad6db06c0097f1f9f2378981b3de..00362695d53f5791d3312bf4d83ddabb7ac10739 100644 --- a/gcc/config/aarch64/aarch64-opts.h +++ b/gcc/config/aarch64/aarch64-opts.h @@ -90,6 +90,7 @@ enum aarch64_function_type { /* SVE vector register sizes. */ enum aarch64_sve_vector_bits_enum { SVE_SCALABLE, + SVE_NOT_IMPLEMENTED = SVE_SCALABLE, SVE_128 = 128, SVE_256 = 256, SVE_512 = 512, diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 1fe1a50d52aeb3719cf30c4a2af41abb8dd7233d..fa3c247f0773e1d4101b6209b6b7ba6cd50f82eb 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -252,6 +252,10 @@ struct tune_params const struct cpu_vector_cost *vec_costs; const struct cpu_branch_cost *branch_costs; const struct cpu_approx_modes *approx_modes; + /* Width of the SVE registers or SVE_NOT_IMPLEMENTED if not appicable. + Only used for tuning decisions, does not disable VLA + vectorization. */ + enum aarch64_sve_vector_bits_enum sve_width; int memmov_cost; int issue_rate; unsigned int fusible_ops; diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 2c267b936b0495a8c5b6593d259619dbe88ae7a8..7ccc6b78d5872d6b43491badbfa9f2d70580015c 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -681,6 +681,7 @@ static const struct tune_params generic_tunings = &generic_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost */ 2, /* issue_rate */ (AARCH64_FUSE_AES_AESMC), /* fusible_ops */ @@ -706,6 +707,7 @@ static const struct tune_params cortexa35_tunings = &generic_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost */ 1, /* issue_rate */ (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD @@ -732,6 +734,7 @@ static const struct tune_params cortexa53_tunings = &generic_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost */ 2, /* issue_rate */ (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD @@ -758,6 +761,7 @@ static const struct tune_params cortexa57_tunings = &cortexa57_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost */ 3, /* issue_rate */ (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD @@ -784,6 +788,7 @@ static const struct tune_params cortexa72_tunings = &cortexa57_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost */ 3, /* issue_rate */ (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD @@ -810,6 +815,7 @@ static const struct tune_params cortexa73_tunings = &cortexa57_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost. */ 2, /* issue_rate. */ (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD @@ -838,6 +844,7 @@ static const struct tune_params exynosm1_tunings = &exynosm1_vector_cost, &generic_branch_cost, &exynosm1_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost */ 3, /* issue_rate */ (AARCH64_FUSE_AES_AESMC), /* fusible_ops */ @@ -863,6 +870,7 @@ static const struct tune_params thunderxt88_tunings = &thunderx_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 6, /* memmov_cost */ 2, /* issue_rate */ AARCH64_FUSE_CMP_BRANCH, /* fusible_ops */ @@ -888,6 +896,7 @@ static const struct tune_params thunderx_tunings = &thunderx_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 6, /* memmov_cost */ 2, /* issue_rate */ AARCH64_FUSE_CMP_BRANCH, /* fusible_ops */ @@ -914,6 +923,7 @@ static const struct tune_params tsv110_tunings = &tsv110_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost */ 4, /* issue_rate */ (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_CMP_BRANCH @@ -940,6 +950,7 @@ static const struct tune_params xgene1_tunings = &xgene1_vector_cost, &generic_branch_cost, &xgene1_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 6, /* memmov_cost */ 4, /* issue_rate */ AARCH64_FUSE_NOTHING, /* fusible_ops */ @@ -965,6 +976,7 @@ static const struct tune_params emag_tunings = &xgene1_vector_cost, &generic_branch_cost, &xgene1_approx_modes, + SVE_NOT_IMPLEMENTED, 6, /* memmov_cost */ 4, /* issue_rate */ AARCH64_FUSE_NOTHING, /* fusible_ops */ @@ -990,6 +1002,7 @@ static const struct tune_params qdf24xx_tunings = &qdf24xx_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost */ 4, /* issue_rate */ (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD @@ -1018,6 +1031,7 @@ static const struct tune_params saphira_tunings = &generic_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost */ 4, /* issue_rate */ (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD @@ -1044,6 +1058,7 @@ static const struct tune_params thunderx2t99_tunings = &thunderx2t99_vector_cost, &generic_branch_cost, &generic_approx_modes, + SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost. */ 4, /* issue_rate. */ (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC @@ -17862,6 +17877,25 @@ aarch64_speculation_safe_value (machine_mode mode, return result; } +/* Implement TARGET_ESTIMATED_POLY_VALUE. + Look into the tuning structure for an estimate. + VAL.coeffs[1] is multiplied by the number of VQ chunks over the initial + Advanced SIMD 128 bits. */ + +static HOST_WIDE_INT +aarch64_estimated_poly_value (poly_int64 val) +{ + enum aarch64_sve_vector_bits_enum width_source + = aarch64_tune_params.sve_width; + + /* If we still don't have an estimate, use the default. */ + if (width_source == SVE_SCALABLE) + return default_estimated_poly_value (val); + + HOST_WIDE_INT over_128 = width_source - 128; + return val.coeffs[0] + val.coeffs[1] * over_128 / 128; +} + /* Target-specific selftests. */ #if CHECKING_P @@ -18341,6 +18375,9 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_SPECULATION_SAFE_VALUE #define TARGET_SPECULATION_SAFE_VALUE aarch64_speculation_safe_value +#undef TARGET_ESTIMATED_POLY_VALUE +#define TARGET_ESTIMATED_POLY_VALUE aarch64_estimated_poly_value + #if CHECKING_P #undef TARGET_RUN_TARGET_SELFTESTS #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests From patchwork Fri Dec 7 15:44:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 1009527 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-491898-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="fcn+fxZb"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43BGxk5Fx4z9s3l for ; Sat, 8 Dec 2018 02:44:58 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; 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7 Dec 2018 15:44:41 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY autolearn=ham version=3.3.2 spammy=profitability X-HELO: foss.arm.com Received: from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 07 Dec 2018 15:44:39 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 081F915AD; Fri, 7 Dec 2018 07:44:38 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0822A3F575; Fri, 7 Dec 2018 07:44:36 -0800 (PST) Message-ID: <5C0A9563.2030201@foss.arm.com> Date: Fri, 07 Dec 2018 15:44:35 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: Marcus Shawcroft , "Richard Earnshaw (lists)" , James Greenhalgh , Richard Sandiford Subject: [PATCH][AArch64][2/2] Add sve_width -moverride tunable Hi all, On top of the previous patch that implements TARGET_ESTIMATED_POLY_VALUE and adds an sve_width tuning field to the CPU structs, this patch implements an -moverride knob to adjust this sve_width field to allow for experimentation. Again, reminder that this only has an effect when compiling for VLA-SVE that is, without msve-vector-bits=. This just adjusts tuning heuristics in the compiler,, like profitability thresholds for vectorised versioned loops, and others. It can be used, for example like -moverride=sve_width=256 to set the sve_width tuning field to 256. Widths outside of the accepted SVE widths [128 - 2048] are rejected as you'd expect. Bootstrapped and tested on aarch64-none-linux-gnu. Ok for trunk? Thanks, Kyrill 2018-12-07 Kyrylo Tkachov * config/aarch64/aarch64.c (aarch64_tuning_override_functions): Add sve_width entry. (aarch64_parse_sve_width_string): Define. 2018-12-07 Kyrylo Tkachov * gcc.target/aarch64/sve/override_sve_width_1.c: New test. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 7ccc6b78d5872d6b43491badbfa9f2d70580015c..bad687d33479f4b6f8cbeaca799824e29b8e9ed1 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1086,12 +1086,14 @@ struct aarch64_tuning_override_function static void aarch64_parse_fuse_string (const char*, struct tune_params*); static void aarch64_parse_tune_string (const char*, struct tune_params*); +static void aarch64_parse_sve_width_string (const char*, struct tune_params*); static const struct aarch64_tuning_override_function aarch64_tuning_override_functions[] = { { "fuse", aarch64_parse_fuse_string }, { "tune", aarch64_parse_tune_string }, + { "sve_width", aarch64_parse_sve_width_string }, { NULL, NULL } }; @@ -10834,6 +10836,34 @@ aarch64_parse_tune_string (const char *tune_string, "tune="); } +/* Parse the sve_width tuning moverride string in TUNE_STRING. + Accept the valid SVE vector widths allowed by + aarch64_sve_vector_bits_enum and use it to override sve_width + in TUNE. */ + +static void +aarch64_parse_sve_width_string (const char *tune_string, + struct tune_params *tune) +{ + int width = -1; + + int n = sscanf (tune_string, "%d", &width); + if (n == EOF) + error ("invalid format for sve_width"); + switch (width) + { + case SVE_128: + case SVE_256: + case SVE_512: + case SVE_1024: + case SVE_2048: + break; + default: + error ("invalid sve_width value: %d", width); + } + tune->sve_width = (enum aarch64_sve_vector_bits_enum) width; +} + /* Parse TOKEN, which has length LENGTH to see if it is a tuning option we understand. If it is, extract the option string and handoff to the appropriate function. */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/override_sve_width_1.c b/gcc/testsuite/gcc.target/aarch64/sve/override_sve_width_1.c new file mode 100644 index 0000000000000000000000000000000000000000..3752fdc2a7198783d2ed5c5f502c3227f98029b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/override_sve_width_1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -moverride=sve_width=512" } */ + +void __attribute__((noinline, noclone)) +vadd (int *dst, int *op1, int *op2, int count) +{ + for (int i = 0; i < count; ++i) + dst[i] = op1[i] + op2[i]; +}