From patchwork Wed Dec 5 06:29:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1008020 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="isQvo4fL"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 438pl33FMlz9s7W for ; Wed, 5 Dec 2018 17:30:39 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1B0A6C22487; Wed, 5 Dec 2018 06:30:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4D941C2247B; Wed, 5 Dec 2018 06:29:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 874D6C2248F; Wed, 5 Dec 2018 06:29:48 +0000 (UTC) Received: from mail-pg1-f194.google.com (mail-pg1-f194.google.com [209.85.215.194]) by lists.denx.de (Postfix) with ESMTPS id BC133C21E36 for ; Wed, 5 Dec 2018 06:29:43 +0000 (UTC) Received: by mail-pg1-f194.google.com with SMTP id 70so8536246pgh.8 for ; Tue, 04 Dec 2018 22:29:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bja5SvkQA8A3mzUoVv9YKHVzJ3w1ZD/U3kMyXnE8Nyo=; b=isQvo4fLRxJqOMUrNvKY2QJX1FTqcguv9QDw5joXq//mdAwPz3BnTtsNwdMWznIBYy lTW2KEB96QkmiNQJbC4Y3aARSkKmcV3ltH8Jw+4bwTH6II3z0pr2FowJpYRY7ak2ycxx Rwgg2Ibwjko0yOFH6y6LYJ5RlnUO9jduIhzvnv1YmSZEvKzt7EDkEwgm3HrGsukp0JKV U4eh6rC6NU8nqtK8RyUcrftKHA0Z7MgXKUA9g8vPeVD12g6xFD60N37JTppxYvxgaYhN ANmOZe/f/VWQwdNCbLxAZisSSKjz7QSb0SJDPvj+38zVPv0hiYt8CQM+JWN331+jPF/2 Ueiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bja5SvkQA8A3mzUoVv9YKHVzJ3w1ZD/U3kMyXnE8Nyo=; b=hBl9jZrfO0AJR0+EE6c6IErPWCjDPe/E8FHB6+HtdyY0fhgJe/gbK9gd5070DMXhm5 B5oKSo78bQLIaAgQDgj4k77Lb02U5aIPOKsw3BcnPpEdN3nNE1d1AOPwAbQw6KOBHwp9 G3yoV7e+TevjYZdOo9ktkmAgz6Nk/5Qk96JfdQ1KKsGWYjl4XlGluFRlGMV07HN3hwnO tkHv2YB8sKXYqyzYgqjk6Iflvv4Q6vVggycS6eQWqXeePbljvClWGmVYwUfk6KKY9iGV lctT9evpduhEOjZ/6pYE0rsh6ymYsB0qUxgkhFOmTzu45B3wCPo8IVdyOr0xb67sRjV8 z4gw== X-Gm-Message-State: AA+aEWY3nYlT3LJAuNl/a9ehezTrf8eaM2lbHpBBHJpQt2cMpK4NiMPf KIK+UddC2EmPbkf5x1+nlepM0g== X-Google-Smtp-Source: AFSGD/XjB0qdHZuDsNWScEcxHaNOqvBT+LXsyNEfJ5jpmvkCpwAL2LkoWo7lo4zZgRnVg9MBcqA0xg== X-Received: by 2002:a63:2ac9:: with SMTP id q192mr19294881pgq.58.1543991382148; Tue, 04 Dec 2018 22:29:42 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([49.207.50.107]) by smtp.googlemail.com with ESMTPSA id s184sm43934545pgc.38.2018.12.04.22.29.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Dec 2018 22:29:41 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Wed, 5 Dec 2018 11:59:23 +0530 Message-Id: <20181205062924.26640-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181205062924.26640-1-anup@brainfault.org> References: <20181205062924.26640-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH 1/2] drivers: serial: Add SiFive UART driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds SiFive UART driver. The driver is 100% DM driver and it determines input clock using clk framework. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt --- drivers/serial/Kconfig | 13 +++ drivers/serial/Makefile | 1 + drivers/serial/serial_sifive.c | 193 +++++++++++++++++++++++++++++++++ 3 files changed, 207 insertions(+) create mode 100644 drivers/serial/serial_sifive.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 3bcc61e731..30f7e00557 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -343,6 +343,13 @@ config DEBUG_UART_SANDBOX start up driver model. The driver will be available until the real driver model serial is running. +config DEBUG_UART_SIFIVE + bool "SiFive UART" + help + Select this to enable a debug UART using the serial_sifive driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + config DEBUG_UART_STM32 bool "STMicroelectronics STM32" depends on STM32_SERIAL @@ -685,6 +692,12 @@ config PXA_SERIAL If you have a machine based on a Marvell XScale PXA2xx CPU you can enable its onboard serial ports by enabling this option. +config SIFIVE_SERIAL + bool "SiFive UART support" + depends on DM_SERIAL + help + This driver supports the SiFive UART. If unsure say N. + config STI_ASC_SERIAL bool "STMicroelectronics on-chip UART" depends on DM_SERIAL && ARCH_STI diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index b6377b1076..b6781535a8 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o obj-$(CONFIG_OWL_SERIAL) += serial_owl.o obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o +obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c new file mode 100644 index 0000000000..cce05d5a01 --- /dev/null +++ b/drivers/serial/serial_sifive.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2012 Michal Simek + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_TXFIFO_FULL 0x80000000 +#define UART_RXFIFO_EMPTY 0x80000000 +#define UART_RXFIFO_DATA 0x000000ff +#define UART_TXCTRL_TXEN 0x1 +#define UART_RXCTRL_RXEN 0x1 + +struct uart_sifive { + u32 txfifo; + u32 rxfifo; + u32 txctrl; + u32 rxctrl; + u32 ie; + u32 ip; + u32 div; +}; + +struct sifive_uart_platdata { + unsigned int clock; + struct uart_sifive *regs; +}; + +/* Set up the baud rate in gd struct */ +static void _sifive_serial_setbrg(struct uart_sifive *regs, + unsigned long clock, unsigned long baud) +{ + writel((u32)((clock / baud) - 1), ®s->div); +} + +static void _sifive_serial_init(struct uart_sifive *regs) +{ + writel(UART_TXCTRL_TXEN, ®s->txctrl); + writel(UART_RXCTRL_RXEN, ®s->rxctrl); + writel(0, ®s->ie); +} + +static int _sifive_serial_putc(struct uart_sifive *regs, const char c) +{ + if (readl(®s->txfifo) & UART_TXFIFO_FULL) + return -EAGAIN; + + writel(c, ®s->txfifo); + + return 0; +} + +static int _sifive_serial_getc(struct uart_sifive *regs) +{ + int ch = readl(®s->rxfifo); + + if (ch & UART_RXFIFO_EMPTY) + return -EAGAIN; + ch &= UART_RXFIFO_DATA; + + return (!ch) ? -EAGAIN : ch; +} + +static int sifive_serial_setbrg(struct udevice *dev, int baudrate) +{ + int err; + struct clk clk; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + err = clk_get_by_index(dev, 0, &clk); + if (!err) { + err = clk_get_rate(&clk); + if (!IS_ERR_VALUE(err)) + platdata->clock = err; + } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { + debug("SiFive UART failed to get clock\n"); + return err; + } + + if (!platdata->clock) + platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0); + if (!platdata->clock) { + debug("SiFive UART clock not defined\n"); + return -EINVAL; + } + + _sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate); + + return 0; +} + +static int sifive_serial_probe(struct udevice *dev) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + /* No need to reinitialize the UART after relocation */ + if (gd->flags & GD_FLG_RELOC) + return 0; + + _sifive_serial_init(platdata->regs); + + return 0; +} + +static int sifive_serial_getc(struct udevice *dev) +{ + int c; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_sifive *regs = platdata->regs; + + while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ; + + return c; +} + +static int sifive_serial_putc(struct udevice *dev, const char ch) +{ + int rc; + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + while ((rc = _sifive_serial_putc(platdata->regs, ch)) == -EAGAIN) ; + + return rc; +} + +static int sifive_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct sifive_uart_platdata *platdata = dev_get_platdata(dev); + + platdata->regs = (struct uart_sifive *)dev_read_addr(dev); + if (IS_ERR(platdata->regs)) + return PTR_ERR(platdata->regs); + + return 0; +} + +static const struct dm_serial_ops sifive_serial_ops = { + .putc = sifive_serial_putc, + .getc = sifive_serial_getc, + .setbrg = sifive_serial_setbrg, +}; + +static const struct udevice_id sifive_serial_ids[] = { + { .compatible = "sifive,uart0" }, + { } +}; + +U_BOOT_DRIVER(serial_sifive) = { + .name = "serial_sifive", + .id = UCLASS_SERIAL, + .of_match = sifive_serial_ids, + .ofdata_to_platdata = sifive_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct sifive_uart_platdata), + .probe = sifive_serial_probe, + .ops = &sifive_serial_ops, + .priv_auto_alloc_size = sizeof(struct sifive_uart_platdata), +}; + +#ifdef CONFIG_DEBUG_UART_SIFIVE +static inline void _debug_uart_init(void) +{ + struct uart_sifive *regs = + (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + + _sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); + _sifive_serial_init(regs); +} + +static inline void _debug_uart_putc(int ch) +{ + struct uart_sifive *regs = + (struct uart_sifive *)CONFIG_DEBUG_UART_BASE; + + while (_sifive_serial_putc(regs, ch) == -EAGAIN) + WATCHDOG_RESET(); +} + +DEBUG_UART_FUNCS + +#endif From patchwork Wed Dec 5 06:29:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1008021 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="XHq7YbHy"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 438pll5kRFz9s7W for ; Wed, 5 Dec 2018 17:31:15 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 85FDEC22496; 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Tue, 04 Dec 2018 22:29:47 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([49.207.50.107]) by smtp.googlemail.com with ESMTPSA id s184sm43934545pgc.38.2018.12.04.22.29.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Dec 2018 22:29:46 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Wed, 5 Dec 2018 11:59:24 +0530 Message-Id: <20181205062924.26640-3-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181205062924.26640-1-anup@brainfault.org> References: <20181205062924.26640-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH 2/2] riscv: qemu: Enable SiFive UART driver in defconfigs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch enables SiFive UART driver in all QEMU RISC-V defconfigs. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt --- configs/qemu-riscv32_defconfig | 1 + configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv64_defconfig | 1 + configs/qemu-riscv64_smode_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 6334d8c0fc..79c8d54cc7 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -7,3 +7,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 0a84ec1874..b733dbed2f 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -8,3 +8,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index 2d9ead93a2..a9d19a5574 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -8,3 +8,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index b012443370..8adc23f826 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -9,3 +9,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y