From patchwork Mon Dec 3 20:38:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1007197 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UUASMDz4"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 437xkx562qz9s8J for ; Tue, 4 Dec 2018 07:42:33 +1100 (AEDT) Received: from localhost ([::1]:52372 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTv31-0008SY-5h for incoming@patchwork.ozlabs.org; Mon, 03 Dec 2018 15:42:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42260) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTuzR-0005zH-D8 for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTuzO-0005ZZ-9F for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:49 -0500 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:36332) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTuzO-0005YZ-4B for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:46 -0500 Received: by mail-ot1-x344.google.com with SMTP id k98so12988440otk.3 for ; Mon, 03 Dec 2018 12:38:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HgiPURpwkuNHglqGFtsbvHALu/51kR4r/LhZdFeceZ4=; b=UUASMDz4Cb7gfyNRGUH/Z7bWnRUISHp7nCq1GLtM7wQPAE8nMRSbnCwb978qI7uaOi oQ2rYo99L6N5zhMWb726xvV0N8Wf8zz+cerBkG8NezW4DK62W9+1QrSZwjbArSrxfjgR aUEO0MTHRWiQ0LpLC1bc7BbPNUSHsBXvkImGc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HgiPURpwkuNHglqGFtsbvHALu/51kR4r/LhZdFeceZ4=; b=fHpg+aZ/wkgTa+5g+zkOAsDKUWSj852EeTtR+eJOfC46k0iv3O/wblDa4+JN6S+ium gwOxAFkD9ZsZTaD9tjqb+ouPjJBiWZDlZUoBnDToVeSzx+4YKGHOEyh4WbMNUEj4AC77 aSck5lcvbfX8w2qn4T24sISEKzU58fC8e12Pkpg4pfcSQ5yWsMzn8ygHJiMLznurQ/90 fmX0EYhibAIxMeVihMVDLmt2voC4/smMkufIsWz8+vML6d92BMGieG9yBvB5K7zXY6iC q6MEEeb6vk6OH3jH2zkogrdLAOn9/xMlPZqFjvSpXLgu0LyOw8BJ/J02AB8qOwyfAH+g 3vIw== X-Gm-Message-State: AA+aEWZISLfRd0PoWCvVu1hXbg6rJvmv7SdE4fQFRNlNX967N/de0ogd MgFz/YpMcUw90PIhn0cS2pf/EC+80gA= X-Google-Smtp-Source: AFSGD/X/mJsG3cJhtQlUCGzsHO3LRap8QLUsVUTxQ0djJhNFMRGmvwQzvt5NMT7j8Cbo7HyWGxXwkA== X-Received: by 2002:a9d:8c6:: with SMTP id 64mr11674292otf.168.1543869525050; Mon, 03 Dec 2018 12:38:45 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:30 -0600 Message-Id: <20181203203839.757-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::344 Subject: [Qemu-devel] [PATCH v2 01/10] target/arm: Move id_aa64mmfr* to ARMISARegisters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" At the same time, define the fields for these registers, and use those defines in arm_pamax(). Signed-off-by: Richard Henderson ---- v2: Include the v8.5 fields; init the registers for kvm. Upcase all of the field names. Reviewed-by: Peter Maydell --- target/arm/cpu.h | 26 ++++++++++++++++++++++++-- target/arm/internals.h | 3 ++- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 4 ++++ 5 files changed, 35 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2a73fed9a0..656a96a8f8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -818,6 +818,8 @@ struct ARMCPU { uint64_t id_aa64isar1; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; + uint64_t id_aa64mmfr0; + uint64_t id_aa64mmfr1; } isar; uint32_t midr; uint32_t revidr; @@ -839,8 +841,6 @@ struct ARMCPU { uint64_t id_aa64dfr1; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint64_t id_aa64mmfr0; - uint64_t id_aa64mmfr1; uint32_t dbgdidr; uint32_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ @@ -1557,6 +1557,28 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64MMFR0, PARANGE, 0, 4) +FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) +FIELD(ID_AA64MMFR0, BIGEND, 8, 4) +FIELD(ID_AA64MMFR0, SNSMEM, 12, 4) +FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4) +FIELD(ID_AA64MMFR0, TGRAN16, 20, 4) +FIELD(ID_AA64MMFR0, TGRAN64, 24, 4) +FIELD(ID_AA64MMFR0, TGRAN4, 28, 4) +FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4) +FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4) +FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4) +FIELD(ID_AA64MMFR0, EXS, 44, 4) + +FIELD(ID_AA64MMFR1, HAFDBS, 0, 4) +FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4) +FIELD(ID_AA64MMFR1, VH, 8, 4) +FIELD(ID_AA64MMFR1, HPDS, 12, 4) +FIELD(ID_AA64MMFR1, LO, 16, 4) +FIELD(ID_AA64MMFR1, PAN, 20, 4) +FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) +FIELD(ID_AA64MMFR1, XNX, 28, 4) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/internals.h b/target/arm/internals.h index d208b70a64..78e026d6e9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -229,7 +229,8 @@ static inline unsigned int arm_pamax(ARMCPU *cpu) [4] = 44, [5] = 48, }; - unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4); + unsigned int parange = + FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE); /* id_aa64mmfr0 is a read-only register so values outside of the * supported mappings can be considered an implementation error. */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 873f059bf2..0babe483ac 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -141,7 +141,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->pmceid0 = 0x00000000; cpu->pmceid1 = 0x00000000; cpu->isar.id_aa64isar0 = 0x00011120; - cpu->id_aa64mmfr0 = 0x00001124; + cpu->isar.id_aa64mmfr0 = 0x00001124; cpu->dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ @@ -195,7 +195,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_aa64pfr0 = 0x00002222; cpu->id_aa64dfr0 = 0x10305106; cpu->isar.id_aa64isar0 = 0x00011120; - cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ + cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ cpu->dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ @@ -249,7 +249,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->pmceid0 = 0x00000000; cpu->pmceid1 = 0x00000000; cpu->isar.id_aa64isar0 = 0x00011120; - cpu->id_aa64mmfr0 = 0x00001124; + cpu->isar.id_aa64mmfr0 = 0x00001124; cpu->dbgdidr = 0x3516d000; cpu->clidr = 0x0a200023; cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 0da1424f72..04c4a91b04 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5207,11 +5207,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = cpu->id_aa64mmfr0 }, + .resetvalue = cpu->isar.id_aa64mmfr0 }, { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = cpu->id_aa64mmfr1 }, + .resetvalue = cpu->isar.id_aa64mmfr1 }, { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 0a502091e7..ad83e1479c 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -538,6 +538,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 6, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, ARM64_SYS_REG(3, 0, 0, 6, 1)); + err |= read_sys_reg64(fdarray[2], &achf->isar.id_aa64mmfr0, + ARM64_SYS_REG(3, 0, 0, 7, 0)); + err |= read_sys_reg64(fdarray[2], &achf->isar.id_aa64mmfr1, + ARM64_SYS_REG(3, 0, 0, 7, 1)); /* * Note that if AArch32 support is not present in the host, From patchwork Mon Dec 3 20:38:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1007193 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; 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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:31 -0600 Message-Id: <20181203203839.757-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v2 02/10] target/arm: Add HCR_EL2 bits up to ARMv8.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Post v8.3 bits taken from SysReg_v85_xml-00bet8. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 656a96a8f8..79d58978f7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1249,7 +1249,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_TIDCP (1ULL << 20) #define HCR_TACR (1ULL << 21) #define HCR_TSW (1ULL << 22) -#define HCR_TPC (1ULL << 23) +#define HCR_TPCP (1ULL << 23) #define HCR_TPU (1ULL << 24) #define HCR_TTLB (1ULL << 25) #define HCR_TVM (1ULL << 26) @@ -1261,6 +1261,26 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_CD (1ULL << 32) #define HCR_ID (1ULL << 33) #define HCR_E2H (1ULL << 34) +#define HCR_TLOR (1ULL << 35) +#define HCR_TERR (1ULL << 36) +#define HCR_TEA (1ULL << 37) +#define HCR_MIOCNCE (1ULL << 38) +#define HCR_APK (1ULL << 40) +#define HCR_API (1ULL << 41) +#define HCR_NV (1ULL << 42) +#define HCR_NV1 (1ULL << 43) +#define HCR_AT (1ULL << 44) +#define HCR_NV2 (1ULL << 45) +#define HCR_FWB (1ULL << 46) +#define HCR_FIEN (1ULL << 47) +#define HCR_TID4 (1ULL << 49) +#define HCR_TICAB (1ULL << 50) +#define HCR_TOCU (1ULL << 52) +#define HCR_TTLBIS (1ULL << 54) +#define HCR_TTLBOS (1ULL << 55) +#define HCR_ATA (1ULL << 56) +#define HCR_DCT (1ULL << 57) + /* * When we actually implement ARMv8.1-VHE we should add HCR_E2H to * HCR_MASK and then clear it again if the feature bit is not set in From patchwork Mon Dec 3 20:38:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1007200 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="CazHyfJr"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 437xnk55cDz9s8J for ; Tue, 4 Dec 2018 07:44:57 +1100 (AEDT) Received: from localhost ([::1]:52383 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTv5J-00033u-Nm for incoming@patchwork.ozlabs.org; Mon, 03 Dec 2018 15:44:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42284) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTuzS-0005zO-B8 for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTuzQ-0005e2-Pj for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:50 -0500 Received: from mail-ot1-x331.google.com ([2607:f8b0:4864:20::331]:36564) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTuzQ-0005cS-KL for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:48 -0500 Received: by mail-ot1-x331.google.com with SMTP id k98so12988541otk.3 for ; Mon, 03 Dec 2018 12:38:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ix6H+z3qtd8RuPgl3+zw+eNU6SEZ44uGBR+mWxb3seg=; b=CazHyfJrk1/sVVb1M1QKf7oleuEi7j/AuLUtWCTga+DIrwSq+DampGFE02mPGKqDO+ ZHcLg8DEeRP5E1DZ8o13FLCmoh7uloiF420tr6v0sZZFRC6d+Xx27xRHnaPCnR74b6An kCtE97pjLN+tmRXQ+1YsGH9kjVylyur36uAAk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ix6H+z3qtd8RuPgl3+zw+eNU6SEZ44uGBR+mWxb3seg=; b=iTRM4n4E1x1X5hi12FojpV/8DAMNlAd9ysoWp6O/eLdPUPQfdX3m+a8gjZRdGnkIqP Y8q90ubAd5ELa3bCfFD/PKqelNeoNnGowWNCqEL5ycUvx0GM+QkkPQEHiAVmJ/FvwsTw PkTKNMWZd1fE4ztHCCk0FowDwoIkgIU59M4vFu0b8YLXGGLEpG9REiC0tp4fn/6CzceA jj/ZjN4B8mJ+BF16h5nlPajoUCJb4JXJaY0LPM6PnXFvyKlmVKZ6KgCElDjucAQDIoZH +Au4DrUHpZ8zDJIQS8Yd6y6Mt7FIwkx1meYxAWvOWdCORIdnV0WiDCiRJkmS5LO4tjKZ QPbg== X-Gm-Message-State: AA+aEWbNXsYW47x7kjMxoTbudlN7dZuMoiVIIuUbgwlLHEkU1khvF8wt bKS/HDo9ihousSJAmgnCzSj/Yyjwcgg= X-Google-Smtp-Source: AFSGD/VHaD3udg8VoEynBSGPUdwTPY9QuDR+zpNsnRe6pjO2IZxPgqgvFBkvXTzsPxaSLqBlIZnjiw== X-Received: by 2002:a9d:dc3:: with SMTP id 61mr10944724ots.345.1543869527667; Mon, 03 Dec 2018 12:38:47 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:32 -0600 Message-Id: <20181203203839.757-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::331 Subject: [Qemu-devel] [PATCH v2 03/10] target/arm: Add SCR_EL3 bits up to ARMv8.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Post v8.4 bits taken from SysReg_v85_xml-00bet8. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 79d58978f7..20d97b66de 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1302,6 +1302,16 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_ST (1U << 11) #define SCR_TWI (1U << 12) #define SCR_TWE (1U << 13) +#define SCR_TLOR (1U << 14) +#define SCR_TERR (1U << 15) +#define SCR_APK (1U << 16) +#define SCR_API (1U << 17) +#define SCR_EEL2 (1U << 18) +#define SCR_EASE (1U << 19) +#define SCR_NMEA (1U << 20) +#define SCR_FIEN (1U << 21) +#define SCR_ENSCXT (1U << 25) +#define SCR_ATA (1U << 26) #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) From patchwork Mon Dec 3 20:38:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1007195 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="gkduhK9W"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 437xgV3kV0z9sCX for ; Tue, 4 Dec 2018 07:39:34 +1100 (AEDT) Received: from localhost ([::1]:52355 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTv07-000616-Rp for incoming@patchwork.ozlabs.org; Mon, 03 Dec 2018 15:39:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42301) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTuzT-0005zb-8i for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTuzS-0005gv-LW for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:51 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:37339) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTuzS-0005fM-E1 for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:50 -0500 Received: by mail-ot1-x342.google.com with SMTP id 40so12971746oth.4 for ; Mon, 03 Dec 2018 12:38:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TCX2H7S6T0GKan665ryQqRgHdROtacoqe/v4hfXwa1s=; b=gkduhK9WE0JwEwuxYXGu3xv6j4DkPQEdxK5gTekT4qVUPe/VA6a0A5VPEFAxCBOk9q 7AqpIhMkmS7CvrhvGxPu3vs2Z9jVyyZIAdKkl6O4JTd1kMHugBGn0DPnGErqhO08rfZy X/by8tJ8N9X7G1wTkRSwZUXHSE1vG8wlKURSk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TCX2H7S6T0GKan665ryQqRgHdROtacoqe/v4hfXwa1s=; b=F9LGWg2z4eqKpqBkIOQSbw01jChoTvw75LxroqpaUSTZ9pXrfkN5NZVz8CPYAKGuXl ip8lTm0M/fLadMOEZ8EZtpGBYQfkcSXaEgMBe8n+svjJOTPIOaI3PTRWfkajwpi3T6kP h48l4PhPumvY9gz6yvfmWgOT95jGoLAzkCpQX5op8/3jDJetBZXPUM6H98nBbXGBZUkf fPRZLai9rPT5UHgRLQ0f5rJwjFU9WInI9tTs6dSYRQWaHtKZ8X+632qABHpWZPBogcKo GVtw5SBKgwPN/kngbqHPItexMUmQQ1i118oev9DC365Q4jLufRlgFQajJj4NewMi7xMq C23Q== X-Gm-Message-State: AA+aEWYbocAIW64hNqjB7Z7fUPYDTDqyK2Q3PXX5zPyVBCogRNzecV8G m+7rLa/PzVHYIvUOoNGRBjYltoKzvAE= X-Google-Smtp-Source: AFSGD/VlA5lA+X9FuaSqpbLXAK/chyivj6Ii8bB/GVSBdHVnpuwZX87CGIIDuYA+3a2vQ4gYXtOByQ== X-Received: by 2002:a9d:64c8:: with SMTP id n8mr11687264otl.115.1543869528987; Mon, 03 Dec 2018 12:38:48 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:33 -0600 Message-Id: <20181203203839.757-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v2 04/10] target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The enable for TGE has already occurred within arm_hcr_el2_amo and friends. Moreover, when E2H is also set, the sense is supposed to be reversed, which has also already occurred within the helpers. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 04c4a91b04..bf020364e1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6537,9 +6537,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, break; }; - /* If HCR.TGE is set then HCR is treated as being 1 */ - hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE); - /* Perform a table-lookup for the target EL given the current state */ target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el]; From patchwork Mon Dec 3 20:38:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1007203 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Z+WNyaKc"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 437xs02pV8z9s0t for ; Tue, 4 Dec 2018 07:47:48 +1100 (AEDT) Received: from localhost ([::1]:52402 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTv86-0005sJ-16 for incoming@patchwork.ozlabs.org; Mon, 03 Dec 2018 15:47:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42360) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTuzW-00062o-Ne for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTuzU-0005kh-Ip for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:54 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:33462) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTuzU-0005jQ-BB for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:52 -0500 Received: by mail-ot1-x342.google.com with SMTP id i20so12982547otl.0 for ; Mon, 03 Dec 2018 12:38:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oN8m4vAK8btTHk7TQ4vcZxcGTzGuHhFiKL/ytYAgzj4=; b=Z+WNyaKcd4bod2PpH4RnZQO8RIn/idte5e9kDNOISDX1Qv++RkGY0ookLZzB3KHAUN rGBUWPrK6I70DgN/CDBw3cVkmckq/ddklV5K4iUGkHTyk+NwDt1OEiSnkuMZKPG9ivkN mlhnLGEbJ2eDFknFn8B+Zi7rZmBnhGhPM+2xc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oN8m4vAK8btTHk7TQ4vcZxcGTzGuHhFiKL/ytYAgzj4=; b=onU6oY3VzaiSfpe+TQm+ucFHL7+bEFhCmb+v4ndVkSoNJErFKbDCO/ibBPPHocYGIn k6yed+ztxnP0e2O+fZHqvP4X2qePm9h01NGgM+FLopHyhy+cWQaXZPaa8go13gLw+/XV PE9AMAHUTRmrM4d9ysL85t24z4yQJrAcD/tw6OkvxNP+9HoYMFVHOk7qngYvA5kgWdVQ 0m4U0gc6po42JFAlfdWsi536g0TZ42p8vfBmOXdHAFuptpNe6ghWdcdBSddJtOenpCHk znrefhRs/CeCSAaTWLWeX5eJwTQU25el++NqVi1KyW6gyqmi17WPRf0Hw9jA3BoN2PWZ VbBg== X-Gm-Message-State: AA+aEWbsfhWZ8xns5CC6WBxCMBYAe+PxPWgFpzCHPySvNlnIN7q3e+D1 OJQd7K2+YAY1kwDb5SQgX1/xeTRYy7Y= X-Google-Smtp-Source: AFSGD/UXqXTXvYh9MNAU9qPH8VhV07vk4mZiMmsix4eQcO/13zWL92p/H9FmtdzJ0xZ4XHDDUiQGxw== X-Received: by 2002:a9d:3ba5:: with SMTP id k34mr11410481otc.364.1543869530696; Mon, 03 Dec 2018 12:38:50 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:34 -0600 Message-Id: <20181203203839.757-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v2 05/10] target/arm: Introduce arm_hcr_el2_eff X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Replace arm_hcr_el2_{fmo,imo,amo} with a more general routine that also takes SCR_EL3.NS (aka arm_is_secure_below_el3) into account, as documented for the plethora of bits in HCR_EL2. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 67 +++++++++------------------------------ hw/intc/arm_gicv3_cpuif.c | 21 ++++++------ target/arm/helper.c | 65 +++++++++++++++++++++++++++++++------ 3 files changed, 82 insertions(+), 71 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 20d97b66de..e871b946c8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1722,6 +1722,14 @@ static inline bool arm_is_secure(CPUARMState *env) } #endif +/** + * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. + * E.g. when in secure state, fields in HCR_EL2 are suppressed, + * "for all purposes other than a direct read or write access of HCR_EL2." + * Not included here are RW, VI, VF. + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env); + /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { @@ -2407,54 +2415,6 @@ bool write_cpustate_to_list(ARMCPU *cpu); # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif -/** - * arm_hcr_el2_imo(): Return the effective value of HCR_EL2.IMO. - * Depending on the values of HCR_EL2.E2H and TGE, this may be - * "behaves as 1 for all purposes other than direct read/write" or - * "behaves as 0 for all purposes other than direct read/write" - */ -static inline bool arm_hcr_el2_imo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_IMO; - } -} - -/** - * arm_hcr_el2_fmo(): Return the effective value of HCR_EL2.FMO. - */ -static inline bool arm_hcr_el2_fmo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_FMO; - } -} - -/** - * arm_hcr_el2_amo(): Return the effective value of HCR_EL2.AMO. - */ -static inline bool arm_hcr_el2_amo(CPUARMState *env) -{ - switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { - case HCR_TGE: - return true; - case HCR_TGE | HCR_E2H: - return false; - default: - return env->cp15.hcr_el2 & HCR_AMO; - } -} - static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el) { @@ -2463,6 +2423,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, bool secure = arm_is_secure(env); bool pstate_unmasked; int8_t unmasked = 0; + uint64_t hcr_el2; /* Don't take exceptions if they target a lower EL. * This check should catch any exceptions that would not be taken but left @@ -2472,6 +2433,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, return false; } + hcr_el2 = arm_hcr_el2_eff(env); + switch (excp_idx) { case EXCP_FIQ: pstate_unmasked = !(env->daif & PSTATE_F); @@ -2482,13 +2445,13 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, break; case EXCP_VFIQ: - if (secure || !arm_hcr_el2_fmo(env) || (env->cp15.hcr_el2 & HCR_TGE)) { + if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { /* VFIQs are only taken when hypervized and non-secure. */ return false; } return !(env->daif & PSTATE_F); case EXCP_VIRQ: - if (secure || !arm_hcr_el2_imo(env) || (env->cp15.hcr_el2 & HCR_TGE)) { + if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { /* VIRQs are only taken when hypervized and non-secure. */ return false; } @@ -2527,7 +2490,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * to the CPSR.F setting otherwise we further assess the state * below. */ - hcr = arm_hcr_el2_fmo(env); + hcr = hcr_el2 & HCR_FMO; scr = (env->cp15.scr_el3 & SCR_FIQ); /* When EL3 is 32-bit, the SCR.FW bit controls whether the @@ -2544,7 +2507,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * when setting the target EL, so it does not have a further * affect here. */ - hcr = arm_hcr_el2_imo(env); + hcr = hcr_el2 & HCR_IMO; scr = false; break; default: diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 068a8e8e9b..cbad6037f1 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -85,8 +85,8 @@ static bool icv_access(CPUARMState *env, int hcr_flags) * * access if NS EL1 and either IMO or FMO == 1: * CTLR, DIR, PMR, RPR */ - bool flagmatch = ((hcr_flags & HCR_IMO) && arm_hcr_el2_imo(env)) || - ((hcr_flags & HCR_FMO) && arm_hcr_el2_fmo(env)); + uint64_t hcr_el2 = arm_hcr_el2_eff(env); + bool flagmatch = hcr_el2 & hcr_flags & (HCR_IMO | HCR_FMO); return flagmatch && arm_current_el(env) == 1 && !arm_is_secure_below_el3(env); @@ -1552,8 +1552,9 @@ static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, /* No need to include !IsSecure in route_*_to_el2 as it's only * tested in cases where we know !IsSecure is true. */ - route_fiq_to_el2 = arm_hcr_el2_fmo(env); - route_irq_to_el2 = arm_hcr_el2_imo(env); + uint64_t hcr_el2 = arm_hcr_el2_eff(env); + route_fiq_to_el2 = hcr_el2 & HCR_FMO; + route_irq_to_el2 = hcr_el2 & HCR_IMO; switch (arm_current_el(env)) { case 3: @@ -1895,8 +1896,8 @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState *env, if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || - (arm_hcr_el2_imo(env) == 0 && arm_hcr_el2_fmo(env) == 0)) { + /* Note that arm_hcr_el2_eff takes secure state into account. */ + if ((arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) == 0) { r = CP_ACCESS_TRAP_EL3; } break; @@ -1936,8 +1937,8 @@ static CPAccessResult gicv3_dir_access(CPUARMState *env, static CPAccessResult gicv3_sgi_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - if ((arm_hcr_el2_imo(env) || arm_hcr_el2_fmo(env)) && - arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) { + if (arm_current_el(env) == 1 && + (arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) != 0) { /* Takes priority over a possible EL3 trap */ return CP_ACCESS_TRAP_EL2; } @@ -1961,7 +1962,7 @@ static CPAccessResult gicv3_fiq_access(CPUARMState *env, if (env->cp15.scr_el3 & SCR_FIQ) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || !arm_hcr_el2_fmo(env)) { + if ((arm_hcr_el2_eff(env) & HCR_FMO) == 0) { r = CP_ACCESS_TRAP_EL3; } break; @@ -2000,7 +2001,7 @@ static CPAccessResult gicv3_irq_access(CPUARMState *env, if (env->cp15.scr_el3 & SCR_IRQ) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || !arm_hcr_el2_imo(env)) { + if ((arm_hcr_el2_eff(env) & HCR_IMO) == 0) { r = CP_ACCESS_TRAP_EL3; } break; diff --git a/target/arm/helper.c b/target/arm/helper.c index bf020364e1..5874c5a73f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1327,9 +1327,10 @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) { CPUState *cs = ENV_GET_CPU(env); + uint64_t hcr_el2 = arm_hcr_el2_eff(env); uint64_t ret = 0; - if (arm_hcr_el2_imo(env)) { + if (hcr_el2 & HCR_IMO) { if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |= CPSR_I; } @@ -1339,7 +1340,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) } } - if (arm_hcr_el2_fmo(env)) { + if (hcr_el2 & HCR_FMO) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |= CPSR_F; } @@ -3991,6 +3992,50 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, hcr_write(env, NULL, value); } +/* + * Return the effective value of HCR_EL2. + * Bits that are not included here: + * RW (read from SCR_EL3.RW as needed) + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env) +{ + uint64_t ret = env->cp15.hcr_el2; + + if (arm_is_secure_below_el3(env)) { + /* + * "This register has no effect if EL2 is not enabled in the + * current Security state". This is ARMv8.4-SecEL2 speak for + * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1). + * + * Prior to that, the language was "In an implementation that + * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves + * as if this field is 0 for all purposes other than a direct + * read or write access of HCR_EL2". With lots of enumeration + * on a per-field basis. In current QEMU, this is condition + * is arm_is_secure_below_el3. + * + * Since the v8.4 language applies to the entire register, and + * appears to be backward compatible, use that. + */ + ret = 0; + } else if (ret & HCR_TGE) { + if (ret & HCR_E2H) { + ret &= ~(HCR_TTLBOS | HCR_TTLBIS | HCR_TOCU | HCR_TICAB | + HCR_TID4 | HCR_ID | HCR_CD | HCR_TDZ | HCR_TPU | + HCR_TPCP | HCR_TID2 | HCR_TID1 | HCR_TID0 | HCR_TWE | + HCR_TWI | HCR_DC | HCR_BSU_MASK | HCR_FB | HCR_AMO | + HCR_IMO | HCR_FMO | HCR_VM); + } else { + ret &= ~(HCR_PTW | HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | + HCR_TACR | HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | + HCR_TRVM | HCR_TLOR); + ret |= HCR_FMO | HCR_IMO | HCR_AMO; + } + } + + return ret; +} + static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO, @@ -6505,12 +6550,13 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure) { CPUARMState *env = cs->env_ptr; - int rw; - int scr; - int hcr; + bool rw; + bool scr; + bool hcr; int target_el; /* Is the highest EL AArch64? */ - int is64 = arm_feature(env, ARM_FEATURE_AARCH64); + bool is64 = arm_feature(env, ARM_FEATURE_AARCH64); + uint64_t hcr_el2; if (arm_feature(env, ARM_FEATURE_EL3)) { rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW); @@ -6522,18 +6568,19 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, rw = is64; } + hcr_el2 = arm_hcr_el2_eff(env); switch (excp_idx) { case EXCP_IRQ: scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ); - hcr = arm_hcr_el2_imo(env); + hcr = hcr_el2 & HCR_IMO; break; case EXCP_FIQ: scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ); - hcr = arm_hcr_el2_fmo(env); + hcr = hcr_el2 & HCR_FMO; break; default: scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA); - hcr = arm_hcr_el2_amo(env); + hcr = hcr_el2 & HCR_AMO; break; }; From patchwork Mon Dec 3 20:38:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1007206 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="dIKV4CGW"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 437xvb5Hrqz9s0t for ; Tue, 4 Dec 2018 07:50:02 +1100 (AEDT) Received: from localhost ([::1]:52413 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTvAF-0000Mv-Aw for incoming@patchwork.ozlabs.org; Mon, 03 Dec 2018 15:49:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42367) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTuzX-00063N-2p for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTuzV-0005mn-OJ for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:55 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:36332) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTuzV-0005lT-Fg for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:53 -0500 Received: by mail-ot1-x342.google.com with SMTP id k98so12988772otk.3 for ; Mon, 03 Dec 2018 12:38:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6RfiLtXmRtrO+0NSs93kQ3AQ83RCZmslZZ/FXyGURgE=; b=dIKV4CGWmzcAzloLJ5WTuKaKhz4POEzSoF81vE3X8wk1kJHzVv8V5UvkARuFnjjYCO wYSQglVi6UeMMrjaUmnXZ01eT2zaAYB4V0bn0NBiTOqah/UgwY0rcydBL/ewoebCaRNi utTxuR1RPaI4/ArM5XfbNlo9QWeaTnStIw7r4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6RfiLtXmRtrO+0NSs93kQ3AQ83RCZmslZZ/FXyGURgE=; b=VuU1FMT5P91gE7H4ITJdlwr+NsosE4K0bDTwnXWIDKxa98MiVOQlklhUcPvpnbGJCH iBBI3mS1IfYdUaOuRuDjpAIcV844orEZG/Ibw3TH5FApqAYK9DfTk+1Tl3RPFIXxiJh5 FKrdb4F1jys+49a5esMiRS0i508vaTdxOL4GhBJ4u9u5a8F4ygcYjyjhlIVRlkc1wpL1 c8YhduD7c74MoPG4cdADj36fDz5HL4S/gZESW2W7voXgdQtLwYZMCrPoYEFhI2ZekPoX LJP7zgJOxRipwmJVwLxhIQxpQwUP8h2C/xvMZw8cYlzGGcToT3UUpYSJA+v6jE3CN649 gakg== X-Gm-Message-State: AA+aEWbyEptCQzSpVqnSwnu0wUi55J+geMl39LLc/gTnXHqbMR1ASnBL QL1lMus27MOD6iR5LaeCbYRbviIKza8= X-Google-Smtp-Source: AFSGD/WPEbZQnzjoqaoOKdJj/7w365T4snFiyGqwhZzlI+cDnTtuHat2O+PrWC33gwZTRUc5iQy44A== X-Received: by 2002:a9d:491e:: with SMTP id e30mr11657639otf.131.1543869532493; Mon, 03 Dec 2018 12:38:52 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:35 -0600 Message-Id: <20181203203839.757-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v2 06/10] target/arm: Use arm_hcr_el2_eff more places X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Since arm_hcr_el2_eff includes a check against arm_is_secure_below_el3, we can often remove a nearby check against secure state. In some cases, sort the call to arm_hcr_el2_eff to the end of a short-circuit logical sequence. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 22 ++++++++++++---------- target/arm/op_helper.c | 14 ++++++-------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5874c5a73f..b248dfcd39 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -448,7 +448,7 @@ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri, int el = arm_current_el(env); bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -468,7 +468,7 @@ static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, int el = arm_current_el(env); bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -488,7 +488,7 @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, int el = arm_current_el(env); bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) || (env->cp15.mdcr_el2 & MDCR_TDE) || - (env->cp15.hcr_el2 & HCR_TGE); + (arm_hcr_el2_eff(env) & HCR_TGE); if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; @@ -4548,8 +4548,7 @@ int sve_exception_el(CPUARMState *env, int el) if (disabled) { /* route_to_el2 */ return (arm_feature(env, ARM_FEATURE_EL2) - && !arm_is_secure(env) - && (env->cp15.hcr_el2 & HCR_TGE) ? 2 : 1); + && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1); } /* Check CPACR.FPEN. */ @@ -6194,9 +6193,8 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type) * and CPS are treated as illegal mode changes. */ if (write_type == CPSRWriteByInstr && - (env->cp15.hcr_el2 & HCR_TGE) && (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON && - !arm_is_secure_below_el3(env)) { + (arm_hcr_el2_eff(env) & HCR_TGE)) { return 1; } return 0; @@ -8797,6 +8795,8 @@ static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) static inline bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) { + uint64_t hcr_el2; + if (arm_feature(env, ARM_FEATURE_M)) { switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { @@ -8815,19 +8815,21 @@ static inline bool regime_translation_disabled(CPUARMState *env, } } + hcr_el2 = arm_hcr_el2_eff(env); + if (mmu_idx == ARMMMUIdx_S2NS) { /* HCR.DC means HCR.VM behaves as 1 */ - return (env->cp15.hcr_el2 & (HCR_DC | HCR_VM)) == 0; + return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; } - if (env->cp15.hcr_el2 & HCR_TGE) { + if (hcr_el2 & HCR_TGE) { /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) { return true; } } - if ((env->cp15.hcr_el2 & HCR_DC) && + if ((hcr_el2 & HCR_DC) && (mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0d6e89e474..780caf387b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -33,8 +33,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, { CPUState *cs = CPU(arm_env_get_cpu(env)); - if ((env->cp15.hcr_el2 & HCR_TGE) && - target_el == 1 && !arm_is_secure(env)) { + if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { /* * Redirect NS EL1 exceptions to NS EL2. These are reported with * their original syndrome register value, with the exception of @@ -428,9 +427,9 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the * bits will be zero indicating no trap. */ - if (cur_el < 2 && !arm_is_secure(env)) { - mask = (is_wfe) ? HCR_TWE : HCR_TWI; - if (env->cp15.hcr_el2 & mask) { + if (cur_el < 2) { + mask = is_wfe ? HCR_TWE : HCR_TWI; + if (arm_hcr_el2_eff(env) & mask) { return 2; } } @@ -995,7 +994,7 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) exception_target_el(env)); } - if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) { + if (!secure && cur_el == 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) { /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. * We also want an EL2 guest to be able to forbid its EL1 from * making PSCI calls into QEMU's "firmware" via HCR.TSC. @@ -1098,8 +1097,7 @@ void HELPER(exception_return)(CPUARMState *env) goto illegal_return; } - if (new_el == 1 && (env->cp15.hcr_el2 & HCR_TGE) - && !arm_is_secure_below_el3(env)) { + if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { goto illegal_return; } From patchwork Mon Dec 3 20:38:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1007199 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="SlFAKUcz"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 437xlz3xgWz9sBZ for ; Tue, 4 Dec 2018 07:43:27 +1100 (AEDT) Received: from localhost ([::1]:52378 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTv3t-00011M-32 for incoming@patchwork.ozlabs.org; Mon, 03 Dec 2018 15:43:25 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTuzb-000689-6E for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:39:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTuzX-0005pE-DC for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:59 -0500 Received: from mail-oi1-x233.google.com ([2607:f8b0:4864:20::233]:40813) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTuzX-0005nq-7a for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:55 -0500 Received: by mail-oi1-x233.google.com with SMTP id t204so12202010oie.7 for ; Mon, 03 Dec 2018 12:38:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AJQZzqFLlfuj708kX3oy8RQC53MDVoDX42PYSFxzklA=; b=SlFAKUczHxErsjJKhv8S5p3qh98lH/Fis637HBpIBjl5iWkkpJwFt7BYjFTY6yr0VG S2ZnQzozuAzg7tJL3gjXlFtzD09w3mNXWqEk/2AiKxvnFik5viC/WVowNtJ91+1mPIvp rPt7h0gaUxVhk4ihkRQhWOP7T/iuqtl5staF4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AJQZzqFLlfuj708kX3oy8RQC53MDVoDX42PYSFxzklA=; b=LIMSW8XFCohrBtXNot6a5gIjBnOAZaYO2Mhh2Hrhq57S71xeTqmXRUfd+SjdTaPlza e51CQzZIZ3uGMbVLNL2W1laErRvAEw7DEPL0fkeyExu60JOLw0N7jNJo03b21J++3zGW FdUugqwzyVFUfN9Inpk05Krp9Zcoh0/SckbdbzOW4SUImiTQSI/P/nOmq7jlm7sBzJQF 3vQUAE/QRdIQzn5YG8BscYdVOdyUtN76JSbgQb4/SSXv4QUY+vYq3O2r54pJjIlhGrXr FWjJHe15fLg+qgx3ZB+ysfllGwJSBvFOIlhbSav6v3HTXpnphi48Nf+tO9SeC6uJQH+c rpng== X-Gm-Message-State: AA+aEWa4YQsJzPjlnZGetHcZyFXL0SDJDkUkJjiW7VrbpBVhtBH3LQ44 MxfmfSADvoF6IbHUQ6i+GROrFP2bF24= X-Google-Smtp-Source: AFSGD/UF7cpDuMA4fvGCn2w0/Txso0pD1PAHsP/hrG4glm8ENr8sSg/E3EHWPBAN6XpGfxTSEnbe0w== X-Received: by 2002:aca:53cd:: with SMTP id h196mr11407859oib.355.1543869533899; Mon, 03 Dec 2018 12:38:53 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:36 -0600 Message-Id: <20181203203839.757-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::233 Subject: [Qemu-devel] [PATCH v2 07/10] target/arm: Tidy scr_write X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Because EL3 has a fixed execution mode, we can properly decide which of the bits are RES{0,1}. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 2 -- target/arm/helper.c | 14 +++++++++----- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e871b946c8..a84101efa9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1312,8 +1312,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_FIEN (1U << 21) #define SCR_ENSCXT (1U << 25) #define SCR_ATA (1U << 26) -#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) -#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET) /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index b248dfcd39..faf7f922bf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1279,11 +1279,15 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* We only mask off bits that are RES0 both for AArch64 and AArch32. - * For bits that vary between AArch32/64, code needs to check the - * current execution mode before directly using the feature bit. - */ - uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK; + /* Begin with base v8.0 state. */ + uint32_t valid_mask = 0x3fff; + + if (arm_el_is_aa64(env, 3)) { + value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ + valid_mask &= ~SCR_NET; + } else { + valid_mask &= ~(SCR_RW | SCR_ST); + } if (!arm_feature(env, ARM_FEATURE_EL2)) { valid_mask &= ~SCR_HCE; From patchwork Mon Dec 3 20:38:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1007198 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="LH6K3IOF"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 437xlF2wK9z9s8J for ; Tue, 4 Dec 2018 07:42:49 +1100 (AEDT) Received: from localhost ([::1]:52374 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTv3G-0000Bz-DD for incoming@patchwork.ozlabs.org; Mon, 03 Dec 2018 15:42:46 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42411) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTuzb-000688-6C for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:39:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTuzY-0005rJ-Pi for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:59 -0500 Received: from mail-ot1-x341.google.com ([2607:f8b0:4864:20::341]:35473) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTuzY-0005qE-Kg for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:56 -0500 Received: by mail-ot1-x341.google.com with SMTP id 81so12996442otj.2 for ; Mon, 03 Dec 2018 12:38:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z43Io25FDRfAJAuHVfPMb9jTaGXjo3dOTCEiU/3353I=; b=LH6K3IOF8/SuPhQy0BLXEH89DGfboHfMMnOuPIF1wzmD2qbvtiIi3nSJ/CYKxFOBKa gSem0LtVy9Kt1s7QFAYcMpSvaNHYeFY4s/JxGaEA6JJvQX+LI5zWqhuQkMnddDtYj3sa lVWnOgL+Zq8Eh1q6wboHXeegbhKttlyPy8xfc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z43Io25FDRfAJAuHVfPMb9jTaGXjo3dOTCEiU/3353I=; b=kW823GmxBWCVHbuou89CNKr+FVwBDw+7KbPOe38z/ANe6Co4LB0brQKbdqWjEQibYA TM39G1L7Pa+lXivH9swfuJs/2YUATQ1BBP2u/ZVu+Seg9VNUTpLA8/q8s9tfm4OqQ84V PSI6a4emqaO0qP0lf+Kiabo82WqyYasDAOZ5Kd8xjkJXlS2s9cp4QAfhccLqs3rppDzr YjQMdzlno21Gajz10w8uUwijGjnG+SfvvvDLuadtK3kJW6ruYiekN2WWBLK5mfoBVUeI nuVEhNz9Th+IBxMFu4EXMNaNqcX7UgZrtH6mnTUJ+MaInbX2ITbIuQEzTPab8KZ0shCc ThJg== X-Gm-Message-State: AA+aEWah3QPFj09y4Ao+JbtmwTbu4sN7dWY0Ofbo+ygjIpdbluuJFDkm ebsJq/ONEOOW9PS0l11LgmN2n37OjqE= X-Google-Smtp-Source: AFSGD/V5s3mqIAFt0NpJP3YZYwTw50hhmIsfKs+4Pofh0lOB2uCPkp7NRsLK0yRyqyNTI3qw9BC20g== X-Received: by 2002:a9d:5f13:: with SMTP id f19mr1235818oti.267.1543869535605; Mon, 03 Dec 2018 12:38:55 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:37 -0600 Message-Id: <20181203203839.757-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v2 08/10] target/arm: Implement the ARMv8.1-LOR extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Provide a trivial implementation with zero limited ordering regions, which causes the LDLAR and STLLR instructions to devolve into the LDAR and STLR instructions from the base ARMv8.0 instruction set. Signed-off-by: Richard Henderson --- v2: Mark LORID_EL1 read-only. Add TLOR access checks. Conditionally unmask TLOR in hcr/scr_write. --- target/arm/cpu.h | 5 +++ target/arm/cpu64.c | 4 ++ target/arm/helper.c | 91 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 12 +++++ 4 files changed, 112 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a84101efa9..ba0c368292 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3285,6 +3285,11 @@ static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0; } +static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR1, LO) != 0; +} + static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0babe483ac..aac6283018 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -324,6 +324,10 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); cpu->isar.id_aa64pfr0 = t; + t = cpu->isar.id_aa64mmfr1; + t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); + cpu->isar.id_aa64mmfr1 = t; + /* Replicate the same data to the 32-bit id registers. */ u = cpu->isar.id_isar5; u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ diff --git a/target/arm/helper.c b/target/arm/helper.c index faf7f922bf..a0ee1fbc5a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1281,6 +1281,7 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Begin with base v8.0 state. */ uint32_t valid_mask = 0x3fff; + ARMCPU *cpu = arm_env_get_cpu(env); if (arm_el_is_aa64(env, 3)) { value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ @@ -1303,6 +1304,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) valid_mask &= ~SCR_SMD; } } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |= SCR_TLOR; + } /* Clear all-context RES0 bits. */ value &= valid_mask; @@ -3950,6 +3954,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) */ valid_mask &= ~HCR_TSC; } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |= HCR_TLOR; + } /* Clear RES0 bits. */ value &= valid_mask; @@ -5004,6 +5011,58 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr0; } +static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (arm_is_secure_below_el3(env)) { + /* Access ok in secure mode. */ + return CP_ACCESS_OK; + } + if (el < 2 && arm_el_is_aa64(env, 2)) { + uint64_t hcr = arm_hcr_el2_eff(env); + if (hcr & HCR_E2H) { + hcr &= HCR_TLOR; + } else { + hcr &= HCR_TGE | HCR_TLOR; + } + if (hcr == HCR_TLOR) { + return CP_ACCESS_TRAP_EL2; + } + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_lor_other(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + int el = arm_current_el(env); + + if (arm_is_secure_below_el3(env)) { + /* Access denied in secure mode. */ + return CP_ACCESS_TRAP; + } + if (el < 2 && arm_el_is_aa64(env, 2)) { + uint64_t hcr = arm_hcr_el2_eff(env); + if (hcr & HCR_E2H) { + hcr &= HCR_TLOR; + } else { + hcr &= HCR_TGE | HCR_TLOR; + } + if (hcr == HCR_TLOR) { + return CP_ACCESS_TRAP_EL2; + } + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -5741,6 +5800,38 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &sctlr); } + if (cpu_isar_feature(aa64_lor, cpu)) { + /* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ + static const ARMCPRegInfo lor_reginfo[] = { + { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, + .access = PL1_R, .accessfn = access_lorid, + .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, lor_reginfo); + } + if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fd36425f1a..5952a9d1cc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2290,6 +2290,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } return; + case 0x8: /* STLLR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* StoreLORelease is the same as Store-Release for QEMU. */ + /* fallthru */ case 0x9: /* STLR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn == 31) { @@ -2301,6 +2307,12 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; + case 0xc: /* LDLAR */ + if (!dc_isar_feature(aa64_lor, s)) { + break; + } + /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ + /* fallthru */ case 0xd: /* LDAR */ /* Generate ISS for non-exclusive accesses including LASR. */ if (rn == 31) { From patchwork Mon Dec 3 20:38:38 2018 Content-Type: text/plain; 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[189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:38 -0600 Message-Id: <20181203203839.757-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH v2 09/10] target/arm: Implement the ARMv8.1-HPD extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Since the TCR_*.HPD bits were RES0 in ARMv8.0, we can simply interpret the bits as if ARMv8.1-HPD is present without checking. We will need a slightly different check for hpd for aarch32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 1 + target/arm/helper.c | 27 ++++++++++++++++++++------- 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index aac6283018..1d57be0c91 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -325,6 +325,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64pfr0 = t; t = cpu->isar.id_aa64mmfr1; + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); cpu->isar.id_aa64mmfr1 = t; diff --git a/target/arm/helper.c b/target/arm/helper.c index a0ee1fbc5a..9bb3e364d4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9776,6 +9776,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, bool ttbr1_valid = true; uint64_t descaddrmask; bool aarch64 = arm_el_is_aa64(env, el); + bool hpd = false; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -9890,6 +9891,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (tg == 2) { /* 16KB pages */ stride = 11; } + if (aarch64) { + if (el > 1) { + hpd = extract64(tcr->raw_tcr, 24, 1); + } else { + hpd = extract64(tcr->raw_tcr, 41, 1); + } + } } else { /* We should only be here if TTBR1 is valid */ assert(ttbr1_valid); @@ -9905,6 +9913,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (tg == 1) { /* 16KB pages */ stride = 11; } + if (aarch64) { + hpd = extract64(tcr->raw_tcr, 42, 1); + } } /* Here we should have set up all the parameters for the translation: @@ -9998,7 +10009,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, descaddr = descriptor & descaddrmask; if ((descriptor & 2) && (level < 3)) { - /* Table entry. The top five bits are attributes which may + /* Table entry. The top five bits are attributes which may * propagate down through lower levels of the table (and * which are all arranged so that 0 means "no effect", so * we can gather them up by ORing in the bits at each level). @@ -10023,15 +10034,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, break; } /* Merge in attributes from table descriptors */ - attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ - attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ + attrs |= nstable << 3; /* NS */ + if (hpd) { + /* HPD disables all the table attributes except NSTable. */ + break; + } + attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 * means "force PL1 access only", which means forcing AP[1] to 0. */ - if (extract32(tableattrs, 2, 1)) { - attrs &= ~(1 << 4); - } - attrs |= nstable << 3; /* NS */ + attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */ + attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */ break; } /* Here descaddr is the final physical address, and attributes From patchwork Mon Dec 3 20:38:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 1007202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="TavhSzEl"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 437xpB398kz9s8J for ; Tue, 4 Dec 2018 07:45:22 +1100 (AEDT) Received: from localhost ([::1]:52386 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTv5j-0003OX-RS for incoming@patchwork.ozlabs.org; Mon, 03 Dec 2018 15:45:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42445) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gTuzc-00069u-QV for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:39:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gTuzb-0005vW-PO for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:39:00 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]:36566) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gTuzb-0005uJ-Jc for qemu-devel@nongnu.org; Mon, 03 Dec 2018 15:38:59 -0500 Received: by mail-oi1-x241.google.com with SMTP id x23so12216596oix.3 for ; Mon, 03 Dec 2018 12:38:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8zBIr54yy4Wx+NC0wja/S07a0aK29AJFkz7XU3SN6ps=; b=TavhSzEls7W/F6E/cQ4bpa5mim0XK5pQdcFn9iCKcNqTdsDR0h5h0f6gbox7E71PYT 2DhvAVF4YHEpsjFZyC8x4th2D33uXczHcde5qj2BTNIswOWkViX5K0vwo8KsYtfr2llr bv+z1a341YclE0dldmFdyYBFx+4OqZEu8/yaY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8zBIr54yy4Wx+NC0wja/S07a0aK29AJFkz7XU3SN6ps=; b=svoBmi0sfr0+NIGrJ2FhhqQZe1ez2Ai1HzI/v3e7rC/ZO6K+fsz7xsINIRn1j9m5lV ANcewt0kP/klz8VZ5i/fv/AQrZWgRaf4IU68L6YKGhpcCTJAKuxzjIYo0re00esifJIs HtJRHjI1IiNUHccFv7x69LtGrAgjZWjx+2NwKpEAdYOeIEO0UL0HdAQzMxW6MdZz7uzU JB4CVwmYca5Jb0oviAZn9wtBH6u1i4gRUQk6Oh+jg/RLjH+mOh/LWARRO7nBdFdDmSLo 65zPFFIh+QgNiUnm4TewGSt35Gj1K4mLb3iAdXtPhETsA3EAgz7sxj2NIuZ99fK/IWVf 2cpw== X-Gm-Message-State: AA+aEWbv3uJjCSswhDt8XfGKiLKZSAqgtA+UOou0eXJzd3OcElnT5Acd WKtUZovcZ9BU/uMWHEjpXZpncl8yTT4= X-Google-Smtp-Source: AFSGD/UfEDNyvAjnPCzxGm7In7jfNjPseMZRlWMG6PGBqpt18pVtEQ79xXeYY+2W9/oUA7oD88wEyg== X-Received: by 2002:aca:5a06:: with SMTP id o6mr11158118oib.341.1543869538514; Mon, 03 Dec 2018 12:38:58 -0800 (PST) Received: from cloudburst.twiddle.net (172.189-204-159.bestel.com.mx. [189.204.159.172]) by smtp.gmail.com with ESMTPSA id m133sm6330063oib.52.2018.12.03.12.38.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Dec 2018 12:38:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 3 Dec 2018 14:38:39 -0600 Message-Id: <20181203203839.757-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181203203839.757-1-richard.henderson@linaro.org> References: <20181203203839.757-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::241 Subject: [Qemu-devel] [PATCH v2 10/10] target/arm: Implement the ARMv8.2-AA32HPD extension X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The bulk of the work here, beyond base HPD, is defining the TTBCR2 register. In addition we must check TTBCR.T2E, which is not present (RES0) for AArch64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 9 +++++++++ target/arm/cpu.c | 4 ++++ target/arm/helper.c | 37 +++++++++++++++++++++++++++++-------- 3 files changed, 42 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ba0c368292..15daa2c050 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1548,6 +1548,15 @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) +FIELD(ID_MMFR4, SPECSEI, 0, 4) +FIELD(ID_MMFR4, AC2, 4, 4) +FIELD(ID_MMFR4, XNX, 8, 4) +FIELD(ID_MMFR4, CNP, 12, 4) +FIELD(ID_MMFR4, HPDS, 16, 4) +FIELD(ID_MMFR4, LSM, 20, 4) +FIELD(ID_MMFR4, CCIDX, 24, 4) +FIELD(ID_MMFR4, EVT, 28, 4) + FIELD(ID_AA64ISAR0, AES, 4, 4) FIELD(ID_AA64ISAR0, SHA1, 8, 4) FIELD(ID_AA64ISAR0, SHA2, 12, 4) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 60411f6bfe..0b185f8d30 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1932,6 +1932,10 @@ static void arm_max_initfn(Object *obj) t = cpu->isar.id_isar6; t = FIELD_DP32(t, ID_ISAR6, DP, 1); cpu->isar.id_isar6 = t; + + t = cpu->id_mmfr4; + t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + cpu->id_mmfr4 = t; } #endif } diff --git a/target/arm/helper.c b/target/arm/helper.c index 9bb3e364d4..5df7a9e637 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2733,6 +2733,7 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = arm_env_get_cpu(env); + TCR *tcr = raw_ptr(env, ri); if (arm_feature(env, ARM_FEATURE_LPAE)) { /* With LPAE the TTBCR could result in a change of ASID @@ -2740,6 +2741,8 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, */ tlb_flush(CPU(cpu)); } + /* Preserve the high half of TCR_EL1, set via TTBCR2. */ + value = deposit64(tcr->raw_tcr, 0, 32, value); vmsa_ttbcr_raw_write(env, ri, value); } @@ -2842,6 +2845,16 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { REGINFO_SENTINEL }; +/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing + * qemu tlbs nor adjusting cached masks. + */ +static const ARMCPRegInfo ttbcr2_reginfo = { + .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, + .access = PL1_RW, .type = ARM_CP_ALIAS, + .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), + offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, +}; + static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5540,6 +5553,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } else { define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); + /* TTCBR2 is introduced with ARMv8.2-A32HPD. */ + if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) != 0) { + define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); + } } if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); @@ -9891,12 +9908,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (tg == 2) { /* 16KB pages */ stride = 11; } - if (aarch64) { - if (el > 1) { - hpd = extract64(tcr->raw_tcr, 24, 1); - } else { - hpd = extract64(tcr->raw_tcr, 41, 1); - } + if (aarch64 && el > 1) { + hpd = extract64(tcr->raw_tcr, 24, 1); + } else { + hpd = extract64(tcr->raw_tcr, 41, 1); + } + if (!aarch64) { + /* For aarch32, hpd0 is not enabled without t2e as well. */ + hpd &= extract64(tcr->raw_tcr, 6, 1); } } else { /* We should only be here if TTBR1 is valid */ @@ -9913,8 +9932,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, if (tg == 1) { /* 16KB pages */ stride = 11; } - if (aarch64) { - hpd = extract64(tcr->raw_tcr, 42, 1); + hpd = extract64(tcr->raw_tcr, 42, 1); + if (!aarch64) { + /* For aarch32, hpd1 is not enabled without t2e as well. */ + hpd &= extract64(tcr->raw_tcr, 6, 1); } }